Class Notes Digital Lec02

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  • 8/7/2019 Class Notes Digital Lec02

    1/2

    May 16, 2010

    `~ivjvcbx twc,G,we,G, 9661920-73/4980

    dwjZ c`v_wevb, BjKUwbIKwgDwbKkb Bwwbqvwis wefvMXvKv wekwe`vjqXvKv-1000, evsjv`k

    Telephone :

    PABX : 9661920-73/4980

    DEPT. OF APPLIED PHYSICS, ELECTRONICS &

    COMMUNICATION ENGINEERING

    UNIVERSITY OF DHAKA

    DHAKA-1000, BANGLADESH

    FAX: 880-2-8615583

    E-MAIL: [email protected]

    Ref. No............................ Dated, the.

    In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

    Data Routing Using MUX:

    Fig.: System for displaying two multidigit BCD counters one at a time.Multiplexers can route data from one of several sources to one destination. For example, 74157 multiplexers areused to select and display the contents of either of two BCD counters using a single set of decoder/drivers and LEDdisplays.

    Each counter consists of two cascaded BCD stages, and each one is driven by its own clock signal. When theCOUTER SELECT line is HIGH, the outputs of counter 1 will be allowed to pass through the multiplexers to thedecoder/drivers to be displayed on the LED readouts. When COUNTER SELECT line is LOW, the outputs of counter2 will pass through the multiplexers to the displays.Here the purpose of multiplexing is to time-share the decoder/drivers and display circuits between the two countersrather than have a separate set of decoder/drivers and displays for each counter. This results

    (I) in a significant saving in the number of wiring connections and(II) it represents a significant decrease in power consumption.

    This technique has the limitation that only one counters contents can be displayed at a time.

    BCDcounter

    BCD

    counter

    BCD

    counter

    BCDcounter

    74ALS157MUX

    (tens)

    74ALS157MUX

    (units)

    BCD- o-7-segmentdecoder/driver (7447)

    BCD- o-7-segment

    decoder/driver (7447)

    TENS UNITS

    LED display LED display

    Za Zb Zc Zd

    Za Zb Zc Zd

    S

    E

    S

    E

    I0I1

    I0I1

    COUNTERSELECT

    Tens Units Tens Units

    Clock #1 Clock #2

    Counter 1 Counter 2

    Lec-02, Pg-01

  • 8/7/2019 Class Notes Digital Lec02

    2/2

    May 16, 2010

    `~ivjvcbx twc,G,we,G, 9661920-73/4980

    dwjZ c`v_wevb, BjKUwbIKwgDwbKkb Bwwbqvwis wefvMXvKv wekwe`vjqXvKv-1000, evsjv`k

    Telephone :

    PABX : 9661920-73/4980

    DEPT. OF APPLIED PHYSICS, ELECTRONICS &

    COMMUNICATION ENGINEERING

    UNIVERSITY OF DHAKA

    DHAKA-1000, BANGLADESH

    FAX: 880-2-8615583

    E-MAIL: [email protected]

    Ref. No............................ Dated, the.

    In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

    Parallel-to-Serial Conversion Using MUX:

    Fig.: Parallel-to-serial converter and waveforms for X7X6X5X4X3X2X1X0=10110101.One method for performing parallel-to-serial conversion using a multiplexer is illustrated in the figure.The data are present in parallel form at the outputs of X register and are fed to the eight-input multiplexer. A three-bitMOD-8 counter is used to provide the select code bits S2S1S0 so that they cycle through from 000 to 111 as clockpulses are applied.

    The output of the multiplexer will be X0 during the first clock period, X1 during the second clock period, and so on. Theoutput Z is a waveform that is a serial representation of the parallel input data.[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

    CLOCK

    S0

    S1

    S2

    Z

    1

    0

    X0 X1 X2 X3 X4 X5 X6 X7 X0 X1 X2 X3 X4 X5

    X0

    X1

    X2

    X3

    X4

    X5

    X6

    X7

    I0

    I1

    I2

    I3

    I4

    I5

    I6

    I7

    74HC1518-input

    MUXZ

    S2 S1 S0

    J

    K

    CLK

    C1

    1

    J

    K

    CLK

    B

    1

    1

    J

    K

    CLK

    A

    1

    1

    CLOCK

    EStorage

    register

    Lec-02, Pg-02