Cisco ASR 9000 System - clnv.s3.amazonaws.com · Cisco ASR 9000 System ... Cisco ASR 9906 Overview...

Cisco ASR 9000 System Architecture

Yongzhong Peng

Manager, Technical Marketing

SP Routing Infrastructure

BRKARC-2003

© 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public

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cs.co/ciscolivebot#BRKARC-2003

• ASR9000 Products Introduction

• ASR9000 System Hardware Architecture

• ASR9000 Distributed Control Plane

• ASR9000 Data Packet Processing

• ASR9000 QoS Architecture

• IOS-XR & IOS-XR 64 Bit

• Conclusion

Agenda

ASR 9000 Products Introduction


Compact & Powerful

Access/AggregationFlexible Service Edge

High Density Service Edge

and Core

• Small footprint with full IOS-XR for distributed environments

• Optimized for ESE and MSE with high M-D scale for medium to large sites

• Scalable, ultra high density service routers for large, high-growth sites

One Platform, One OS, One Family

Fixed 2RU

240 Gbps

2 LC/6RU

16 Tbps

8 LC/21RU

14 Tbps

10 LC/30RU

80 Tbps

20 LC/44RU

160 Tbps

4 LC/10RU

7 Tbps

ASR 9904

ASR 9001

ASR 9006

ASR 9010

ASR 9912

ASR 9922

MSE E-MSE Peering P/PE Mobility Broadband

nV Satellites ASR 9000v, NCS5000

CE

8 LC/21RU

64 Tbps

ASR 9910

4 LC/14RU

32 Tbps

ASR 9906ASR 9901

Cisco ASR 9000 System Comprehensive Portfolio

6BRKARC-2003


ASR 9901 Highlights

Form Factor & BW

• 2 RU box with 2 Tomahawk NPU(ASR 9001 is 2 RU with 2

Typhoons)

• Depth of ~23 inches,(9001 is 18”)

• 456G Duplex BW(9001 is 120G Duplex)

• Fixed ports available; no MPAs

• 42 ports on the faceplate : 16X1G, 24X1/10G, 2X100G(QSFP28)

• 1G ports : LAN & MACSEC10G ports: LAN & MACSEC100G port : LAN & MACSEC

Ports / Port Density

• Redundant Power & Fan-trays

• Front to back Airflow

• NEBS, EMC Compliant

• All ports/power cabling on front plate; fan trays on backside

• Typical Power Consumed : 1200W

Mechanicals & Commons

• 64 bit XR only

• PAYG mode for 120G,240G,360G and 456G

• Full feature parity with Tomahawk feature-set

SW & Licensing

BRKARC-2003 7


ASR 9901 Port mapping

BRKARC-2003 8


Scalable for Dense 100GE

Applications for future investment

protection

Greater Capacity, Greater Flexibility:

Start with 2 RSPs, then add fabric

cards to scale beyond 460G and

enable N+1 fabric redundancy

Mid-Plane design allows for compact

chassis footprint

5 Fabric

Cards

2 Fan Trays

2 RSPs

4 Line Card

Slots

1 Power

Tray

Cisco ASR 9906 Overview

BRKARC-2003 9


• RSP880-LT is the 3rd generation route processor card

• 880Gbps/slot throughput (redundant configuration)

• 4 Core Intel Broadwell1.8GHz processor

• Available in both TR (16GB)/ SE (32GB) variants

• Line Cards Supported

• Tomahawk

• Typhoon

• VSM

• SIP-700

• Chassis Supported

• 9006/9010/9910/9906/9904

• Feature parity cXR with RSP880 at FCS (eXR support planned for 6.4.x)

• Similar Control Plane Scale to RSP880

• No support for nV-Cluster and 3rd party applications

RSP880-LT

Hardware Differences

RSP880 RSP880-LT

8 Cores, 1.9Ghz 4 Cores, 2.4Ghz

4 SFP+ external ports No external SFP+ ports

2x32GB SSD 2x128GB SSD

RSP880-LT provides is a cost effective migration

path for RSP440 customers.

BRKARC-2003 11


Comparison of RSP880-LT to RSP880

RSP880-LT RSP880/A99-RSP

Bandwidth/Slot 880Gbps (Dual RSP)*** 880Gbps (Dual RSP)

RIB Scale** 26M/27M (IPv4/IPv6) 26M/27M (IPv4/IPv6)

RIB Learning Rate 95K IPv4 Routes/sec 78K IPv4 Routes/sec

Platforms Supported ASR 9904, 9006, 9010, 9910, 9906 RSP880: ASR 9904, 9006, 9010

A99-RSP: ASR 9910, 9906

3rd Party Application Support Not Supported Supported

eXR Support Planned for support in 6.4.x Supported

BRKARC-2003 12


ASR 9000 Linecards Evolution

14

3rd Gen

Tomahawk Class

1.2TTomahawk

28nm

240 Gbps

Tigershark

28nm

200 Gbps

SM15

28nm

1.20 Tbps

X86

6 Core

2 Ghz

2nd Gen

Typhoon Class

360GTyphoon

55nm

60 Gbps

Skytrain

65nm

60 Gbps

Sacramento

65nm

220 Gbps

PowerPC

Quad Core

1.5 Ghz

Trident

90nm

15 Gbps

Octopus

130nm

60 Gbps

Santa Cruz

130nm

90 Gbps

PowerPC

Dual Core

1.2 Ghz

1st Gen

Trident Class

120G

BRKARC-2003

4th Gen

Lightspeed Class

3.2TLightspeed

400 GbpsSkybolt X86

16 Core

BRKARC-2003


ASR 9K Ethernet Line Card Overview

A9K-MOD80 A9K-MOD160

MPAs20x1GE2x10GE4x10GE1x40GE2x40GE

-TR, -SE

MPAs1x100GE2x100GE20x10GE

+ Typhoon MPAs

MOD400/MOD200A9K-4x100GE A9K-12x100GE

A9K-36x10GE A9K-24x10GEA9K-2x100GE

A9K-40GE

A9K-4T16GE

2nd LC Typhoon

NPU: 60Gbps,

~45Mpps

3rd LC Tomahawk

NPU: 240Gbps,

~150Mpps

A9K-8x100GE A9K-400G-DWDM24/48x10/1G LC

15BRKARC-2003


Cost Optimized 4x100GE LAN Line card

• Tomahawk based, 5-fabric linecard with: 2x NPU and 5Mbit internal TCAM

• Supported on all ASR 90xx and 99xx systemsHW Specs

• Parity with Tomahawk TR linecards at FCS except for Timings features (post FCS)

• Features not supported: VidMon, Cluster, LISP, NSH, BNG, Satellite, MPLS-TPFeatures

• cXR: 6.2.3, 6.3.2, 6.4.1 and onwards. SMU option possible for 6.1.4, 6.3.1, subject to business case

• eXR: 6.4.1SW support

• Limited scale for TCAM dependent features; rest of the scale on-par with other Tomahawk –TR

cardsScale

BRKARC-2003 16


Pop Quiz ????

18BRKARC-2003

Which of the following RSP is supported in all of ASR9006, ASR9010, ASR9904, ASR9906 and ASR9910?

• RSP880-LT

• RSP880

ASR 9000 Hardware Architecture


ASR 9000 System Architecture “At-a-Glance”

Fully Distributed Architecture for

High Performance and High Multi-

dimensional Control Plane Scale

Active-Active Switch Fabric

RSP

RSP/RP

FIC

CPU

BITS/DTI

FIA

CPU

Switch

Fabric

FIA

FIA

FIA

FIANP

NP

NP

NP

PHY

PHY

PHY

PHY

CPAK

CPAK

CPAK

CPAK

CPAK

CPAK

CPAK

CPAK

CPU

CPU

Switch

Fabric

FIA

FIA NP

NP

SerDes

XBAR

Bay

Bay

CPU

Switch Fabric

Line Card

Data forwarding is fully

distributed across NPs

Control plane split

among RSP/RP

and LC CPU

Network Processor

Network Processor

23BRKARC-2003


ASR 9000 Switch Fabric High-Level Architecture3-Stage Non-Blocking Fabric (Separate Unicast and Multicast Crossbars)

FIAFIA

FIARSP0

Arbiter

fabric

RSP1

Arbiter

fabric

fabricFIAFIA

FIA

fabric

Fabric frame format:

Super-frame

Fabric load balancing:

Unicast is per-packet

Multicast is per-flow

Virtual Output Queue

Arbitration

Stage 1 Stage 2 Stage 3

TomahawkTyphoon LC

Ingress LinecardEgress Linecard

Active-Active Fabric

Unicast

Crossbar

Multicast

Crossbar

BRKARC-2003 24


ASR90xx – RSP880 and Mixed LC

FIAFIA

FIARSP880

Arbiter

RSP880

FIAFIA

FIA

Stage 1 Stage 2 Stage 3

Tomahawk Line CardTyphoon Linecard

Ingress LinecardEgress Linecard

Fabric bandwidth:

8x115Gbps ~ 900Gbps/slot with dual RSP

4x115Gbps ~ 450Gbps/slot with single RSP

8x115Gbps

8x55GbpsFabric bandwidth:

8x55Gbps =440Gbps/slot with dual RSP

4x55Gbps =220Gbps/slot with single RSP

Fabric

Fabric

SM15

Fabric

SM15

Arbiter

FabricSM15

BRKARC-2003 25


SFC v2

Tomahawk Line Card

FIAFIA

FIA

ASR99xx Switch Fabric Card (FC2)6+1 All Active 3-Stage Fabric Planes, Scale to 1.6Tbps/LC, Separated Ucast/Mcast Crossbars

Tomahawk Line Card

FIAFIA

FIA

5x 2x115G bi-directional

= 1.15Tbps7x2x115G bi-directional

= 1.6Tbps

Fabric

SM15

Fabric

SM15

Fabric frame format:

Super-frame

Fabric load balancing:

Unicast is per-packet

Multicast is per-flow

Fabric bandwidth:

10x115Gbps ~ 1.15 Tbps/slot with 5x FC2

14x115Gbps ~ 1.6 Tbps/slot with 7x FC2

5-Fabric LC 7-Fabric LC

BRKARC-2003 26


Tomahawk LC: 8x100GE Architecture

XB

AR

Se

pa

rate

d S

witc

h F

ab

ric

LC CPU

TomahawkNP

FIAPHY

TomahawkNP

FIAPHY

TomahawkNP

FIAPHY

TomahawkNP

TigersharkFIA

PHY

CPAK:

100G, 40G, 10G

L2/L3/L4 lookups, all VPN types, all

feature processing, mcast

replication, QoS/Queuing, ACL, etc …

Slice Based Architecture

Macsec Suite B+, G.709, OTN,

Clocking

VoQ buffering, Fabric credits,

mcast hashing, scheduler for fabric

and egress port

240G

240G

240G

240G

240G

240G

240G

240G

FPOE, Auto-Spread,

DWRR, RBH, replication

Per Slice Power Management: (100-200W Power Savings)

PE1(admin-config)# hw-module power saving location ? slice [0-3]

Up to

14x115G

28BRKARC-2003


4x100GE LAN-based linecard architecture

Switch Fabric(SM15)

FIAQSFP 2

NPQSFP 3

PHY

FIAQSFP 0

NPQSFP 1

PHY

2x 8x15G = 240G raw bw

3x Fencer ports

Interlaken

2x 16x 10.9375G

= 350G raw bw

CPU

Up to 10x115G

BRKARC-2003 29


• Supports all 1G and 10G. 1G and 10G are configurable follow certain rule

• 48-port has a two NPU slices with shared 80Mb TCAM

• Phy does not support OTN Framing or MACSec

Ports0-7 PHY0

FIA SM15Ports8-15 PHY1

Ports16-23 PHY2

NPU 0

SFPs0-7

SFPs8-15

SFPs16-23

IFE

0IF

E1

Ports24-31 PHY3

FIA SM15Ports32-39 PHY4

Ports40-47 PHY5

NPU 1

SFPs24-31

SFPs32-39

SFPs40-47

IFE

0IF

E1

• 240G Raw Bandwidth/ 200G

Data Traffic Bandwidth

• Potentially Oversubscribed

8 Ports

8 Ports

4 Ports

4 Ports

A9K-48x10G-1G Architecture

31BRKARC-2003

© 2018 Cisco and/or its affiliates. All rights reserved. Cisco Public 32

A9K-48x10G-1G Port Organization

• A9K-48X10GE-1G-SE/TR has two NPU slices, A9K-24X10GE-1G-SE/TR has one

• Each NPU slice consists of two Interface Engines (IFE)

• Interface Ports are organized in port-groups

• Each IFE consists of three port-groups

• Each port-group consists of 4 interface ports

A9K-48X10GE-1G-SE/TR

00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

TOMAHAWK NPU

IFE

TOMAHAWK NPU

IFE IFE IFE

12 ports per IFE 12 ports per IFE 12 ports per IFE 12 ports per IFE

port-group port-group port-group port-group port-group port-group port-group port-group port-group port-group port-group port-group

BRKARC-2003


A9K-48x10-1G Port Speed Rules

• Interface Port Speed is configurable: 1G / 10G

• Per default, all ports are 10G

• The 4 Rules:

1. All ports in a port-group (group of four ports) have to have the same speed.

2. If the first port-group on an IFE (group of three port-groups) is configured for 1G, then all ports in that same IFE must be 1G.

3. If the first port-group of an IFE is 10G, then the other two port-groups in that same IFE can be any combination of 1G or 10G.

4. When configuring port speeds, all ports of a given linecard need to be configured together in one single CLI command.

• Deviations from these rules will results in a CLI rejection

• Changing port speed on an interface does not impact traffic on other interfaces

BRKARC-2003


Possible Port Speed Combination per IFE

P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11

Configuration 1 1G 1G 1G 1G 1G 1G 1G 1G 1G 1G 1G 1G





Interface Engine (IFE)

• 5 possible port speed combinations for each IFE

• IFE are independent of each other for port speed configuration

BRKARC-2003


Line Card Components

NPUFIA Switch

Fabric ASIC

TM

PHY

CPU

P1

P2

P3

BEP1

P2

P3

BE

Runs distributed control plane protocols for increased scale

BFD, CFM, ARP

Receive FIB table from RP and program hardware forwarding table

Provides data connection to switch fabric

Manage VoQ, Superframe and loadbalancingdata traffic across switch fabric

Mcast replication table for replication toward NPs

Main forwarding engine L2 and L3 lookups

Multicast replication toward Optics

User level QoS and Security features

Dedicated queue ASIC – TM (traffic

manager) per NPU for QoS functions

User Configurable Queue on TM.

Default Port Queue Always Created.

36BRKARC-2003


Network Processor Architecture Details

• TCAM: VLAN tag, QoS and ACL classification

• Stats memory: interface statistics, forwarding statistics etc

• Frame memory: buffer, Queues

• Lookup Memory: forwarding tables, FIB, MAC, ADJ

• TR/SE

• Different TCAM/frame/stats memory size for different per-LC QoS, ACL, logical interface scale

• Same lookup memory for same system wide scale mixing different variation of LCs doesn’t impact system wide scale

-

STATS MEMORY

FRAME MEMORYLOOKUP

MEMORY TCAM

FIB MAC

NPU Complex

Forwarding chip (multi core)

TR and SE has different

memory sizeTR and SE has same

memory size

-TR: transport optimized, -SE: Service edge optimized

37BRKARC-2003


Pop Quiz ????

38BRKARC-2003

For the A9K-48x10G-1G linecard, if the first port-group of an IFE is configured as 1G, what is the possible port speed for the other two port-groups of the same IFE?

• 10G

• 10G or 1G

• 1G

ASR 9000 Distributed Control Plane


Switch

Fabric

FIA

FIA

FIA

FIANP

NP

NP

NP

PHY

PHY

PHY

PHY

CPAK

CPAK

CPAK

CPAK

CPAK

CPAK

CPAK

CPAK

CPU

ASR9000 Fully Distributed Control Plane

Switch Fabric

PuntFPGA FIA

Switch Fabric

RP

LPTS

LC CPU: ARP, ICMP, BFD, NetFlow,

OAM/CFM, L2 Protocols etc

RP CPU: Routing, MPLS, IGMP, PIM,

HSRP/VRRP, etc

LPTS (local packet transport service):

control plane policing

Control packet

Punt Switch

CPU

CPU

NP Offloading: BFD

LC

40BRKARC-2003


LC NP

L3 Control Plane Architecture

LC CPU

RSP/RP CPU

LDP RSVP-TEBGP

ISIS

OSPF

EIGRP

Static

HW FIB Adjacency

ARP/NDP

LSD RIB

AIB

SW FIB

AIB: Adjacency Information Base

RIB: Routing Information Base

FIB: Forwarding Information Base

LSD: Label Switch Database

RSP/RP

LC

41BRKARC-2003


Distributed ARP Processing

LC

CPU

PHY NP FIALPTS

Punt Switch

ARP

spio netio

Tsec Driver

SPP

Line card

FIA

Sw

itch

Fa

bric

RP

Sw

itch

Fab

ric

ARP

RP CPUIncomplete ADJ Packets

Incoming ARP Packets

Outgoing ARP Packets

42BRKARC-2003


NP

Switch Fabric

3x10GE

SFP +

3x10GE

SFP +

3x10GE

SFP +

3x10GE

SFP +

3x10GE

SFP +

3x10GE

SFP +

3x10GE

SFP +

3x10GE

SFP +

FIA

FIA

FIA

FIA

Sw

itch

Fab

ric A

SIC

CPU

PuntFPGA FIA

CPU

Switch Fabric

RP

LC1

3x10GE

SFP +

3x10GE

SFP +

NP

NP

3x10GE

SFP +

3x10GE

SFP +

NP

NP

3x10GE

SFP +

3x10GE

SFP +

NP

NP

3x10GE

SFP +

3x10GE

SFP +

NP

NPFIA

FIA

FIA

FIA

Sw

itch

Fab

ric A

SIC

CPULC2

1 2

2

NP learn MAC address in hardware (around

4M pps)

NP flood MAC notification (data plane)

message to all other NPs in the system to sync

up the MAC address system-wide. MAC

notification and MAC sync are all done in

hardware

1

2

NP

NP

NP

NP

NP

NP

NP

Hardware based MAC learning: ~4Mpps/NP

MAC Learning and Sync

Data packet

BRKARC-2003 43


Distributed BFD Architecture

OSPF ISIS BGP

BFD Session Tables on RP

BFD Events

BFD session info

RP

BFD Session Tables on LC

BFD EventsBFD Session info

LC1-CPU

BFD Hellos

BFD Session Tables on LC

BFD Hellos

BFD Session info

……

LCn-CPU

44BRKARC-2003


HW-offloaded BFD

OSPF ISIS BGP

BFD Session Tables on RP

BFD Events

BFD session info

RP

BFD EventsBFD Session info BFD Session info

……

BFDOnNP

LCn-CPU

BFD Hellos

BFDOnNP

BFDOnNP

BFDOnNP

BFDOnNP

LC1-CPU

BFD Hellos

BFDOnNP

BFDOnNP

BFDOnNP

hw-module bfd-hw-offload enable location 0/0/CPU0

45BRKARC-2003


Distributed Netflow Architecture

NPU

LC-CPU1M Record Cache

NPU NPU NPU

RPNetflow show/clear

Command

Netflow

Configure

NPU: • Traffic Filtering

• Traffic Sampling

• Extract flow

header information

• LPTS Policer

• Aggregate 200Kpps netflow

policer rate

• Evenly Divided among

netflow-enabled NPs

netIO

EXPORT

• Manage flow table

• Export flow

information

LC

BRKARC-2003 46


Pop Quiz ????

47BRKARC-2003

In an ASR9906 system which has 2 RSP, 4 linecards and 5 switch fabric cards, how many total CPUs are available to host ASR9000 control-plane functionalities?

• 2

• 4

• 6

• 11

ASR 9000 Data Packet Processing


CPAK 0

NP FIA

FIA

FIA

FIA

CPU

CPAK 1

PHY

CPAK 2

NP CPAK 3

PHY

CPAK 4

NP CPAK 5

PHY

CPAK 6

NP CPAK 7

PHY

…

Up to

14x120

G

Switch Fabric (SM15)

CPAK 0

NP FIA

FIA

FIA

FIA

CPU

CPAK 1

PHY

CPAK 2

NP CPAK 3

PHY

CPAK 4

NP CPAK 5

PHY

CPAK 6

NP CPAK 7

PHY …

Up to

14x120G

Switch Fabric (SM15)

Switch Fabric

Switch Fabric

Distributed Two-Stage Packet Processing

Uniform packet flow for simplicity and predictable performance

12

1

2

• Ingress lookup yields packet egress port and applies ingress features

• Egress lookup performs packet-rewrite and applies egress features

49BRKARC-2003


ASR9000 Life of a Packet – Tomahawk LC

• MACSEC Decryption• G.709/OTN/WAN-

PHY/LAN-PHY• Line Clocking

PHY

FIA

CPUCPU

Switch Fabric

CPAK 0

NP FIACPAK 1

PHY

TM

12

3

4

5

NPTM

6

7

8

1

• Ingress L2/L3 FIB lookup, ACL/QoS lookup

• Ingress PBR/ABR, ACL, uRPF• Ingress QoS: classification,

marking, policing• Packet Punting• Ingress ECMP/LAG hashing

2

Ingress side of LC

Egress side of LC

• Ingress Queuing Processing

• Bypassed in case no ingress queuing support

3

• Buffering packet from NP• Requesting fabric credit• Manage superframe and

load-balancing packet across fabric

• Manage system VoQ

4

• Re-assembling packets from superframe

• Send packet to corresponding NP

• Release buffer and fabric credit

5

• Egress L2/L3 FIB lookup, ACL/QoS lookup

• Egress PBR/ABR, ACL, uRPF• Egress QoS: classification,

marking, policing, shaping• Incomplete Adj Packet Punting• Egress ECMP/LAG hashing

6

• MACSEC Emcryption• G.709/OTN/WAN-

PHY/LAN-PHY• Line Clocking

8

• Egress Queuing Processing

7

50BRKARC-2003


Switch Fabric Arbitration

Fabric ASIC

and VOQ

SFC or RSP1

Arbitration

Fabric

ASIC

Fabric

ASIC

Fabric

ASIC

Fabric

ASIC

ArbitrationFabric ASIC

and VOQ SFC or RSP0

1: Fabric Request

3: Fabric Grant

2: Arbitration

4: load-balanced transmission across fabric links

5: credit return

BRKARC-2003 52


• Multiple unicast frames from/to same destinations aggregated into one super frame

• Super frame is created if there are frames waiting in the queue, up to 32 frames or when min threshold met, can be aggregated into one super frame

• Super frame only apply to unicast, not multicast

• Super-framing significantly improves total fabric throughput

0 (Empty)Max

Super-frame

Packet 1 Jumbo

Packet 1 No super-framing

Packet 1 Max reachedPacket 2Packet 3

Min

Super-frame

Packet 1 Min reachedPacket 2

Fabric Super-framing Mechanism

BRKARC-2003


• Unicast traffic sent across first available fabric link to destination (maximizes efficiency)

• Each frame (or super frame) contains sequencing information

• All destination fabric ASIC have re-sequencing logic

• Additional re-sequencing latency is measured in nanoseconds

Fabric Load Balancing – Unicast

Fabric ASIC

and VOQ

SFC or RSP1

Arbitration

Fabric

ASIC

Fabric

ASIC

Fabric

ASIC

Fabric

ASIC


and VOQ SFC or RSP04 3 2 1

54BRKARC-2003


• Multicast traffic hashed based on (S,G) info to maintain flow integrity

• Very large set of multicast destinations preclude re-sequencing

• Multicast traffic is non arbitrated – sent across a different fabric plane

Fabric Load Balancing – Multicast

Fabric ASIC

and VOQ

SFC or RSP1

Arbitration

Fabric

ASIC

Fabric

ASIC

Fabric

ASIC

Fabric

ASIC


and VOQ SFC or RSP0A

1

A

2

B

1

A

3

B

2

C

1

Flows exit in-order

56BRKARC-2003

ASR 9000 QoS Architecture


ASR9000 Priority-Based QoS Architecture

• Ingress (sub-)interface QoS Queues

• User Configurable Ingress QoS Policy

• 4xVOQ per VQI• Up to 8K VOQs per TSK FIA

(vs 4k per SKT FIA)

4x Egress Destination Qs per VQI, aggregated at egress port rate

• Dedicated Traffic Manager(TM) for Traffic Queuing

• User Configurable QoS Policy on Ingress/Egress NP

• End-to-End priority propagation Guarantee bandwidth, low latency for high priority traffic

• Unicast VOQ and back pressure

User-configuration with Ingress MQC

Egress (sub-)interface QoS Queues

User-configuration with Egress MQC

Implicit ConfigurationNot User-controllable

Ingress side of LC Egress side of LC

NP0 PHY

NP2 PHY

NP3 PHY

NP1 PHYFIA

CPUCPU

Switch Fabric

3

4

1 2 34

CPAK 0

NP FIACPAK 1

PHY

1

2

P1

P2

P3

BE

P1

P2

P3

BE

P1

P2

P3

BETM

TM

P1

P2

P3

BE

BRKARC-2003 58


Default Implicit Trust Model

internal

cos = 1L2 Bridging

802.1p = 1 *

802.1p = 1IPP=5 DSCP=44

IPP=5 DSCP=44

IPP=5 DSCP=44

internal

cos = 0L2 Bridging

UntaggedIPP=5 DSCP=44

802.1p = 0 *IPP=5 DSCP=44

IPP=5 DSCP=44

Ingress line card Egress line card

Carried in internal buffer header,

by default, internal cos is used for impositioned fields only,

For example, added vlan tag, impositioned MPLS label,

It doesn’t include VLAN tag translation or MPLS label swap

ASR 9000 would never modify

packet DSCP/IP without

a policy-map configured

L2 IF: trust outer Cos

L3 IF: trust DSCP

L3 MPLS: trust outer EXP

60BRKARC-2003BRKARC-2003


•Priority Level 1•Priority Level 2•Shape, •bandwidth or bandwidth remaining•(W)RED•Police•Set (marking)

•Priority Level 1•Priority Level 2•Shape, •bandwidth or bandwidth remaining•(W)RED•Police•Set (marking)

•Shape

•Bandwidth

remaining

•1R2C policer

L4

Child policy (child of

Parent) with user-

defined classes &

class-default

L3Parent Policy on L2 (EFP) or L3 subint. class-

default or physical port /w user-

defined classes

L2Grand-Parent

Policy

L1

Port

scheduler

not

configurable

•N/A

3-Layer Hierarchical QoS (H-QoS)

L0

Port Group

scheduler

not

configurable

•N/A

63BRKARC-2003

policy-map child

class Pr1

police rate 64 kbps

priority level 1

class Pr2

police rate 10 mbps

priority level 2

class Cl3

bandwidth 3 mbps

class Cl4

bandwidth 1 mbps

!

policy-map parent

class parent1

shape average 100 mbps

service-policy child

class parent2



class class-default

!

policy-map grand-parent

class class-default


service-policy parent


H-QoS – Supported Classification/Policy

Policy-map hierarchy level Classification support Policy Support

Grand-parent Only class-default

• Shape Average

• Bandwidth remaining

• 1R2C policer with only drop/transimit

action(no set/mark, Tomahawk card only)

Parent

User defined fields with

restrictions based on

format/interface types.

• Priority/WRED Queue and Queue-limit on

Leaf only

• Policer/Shaper/Marking/non-Priority

Queue/Bandwidth/Bandwidth Remaining

Child

User defined fields with

restrictions based on

format/interface types.

• Priority/WRED Queue and Queue-limit on

Leaf only

• Policer/Shaper/Marking/non-Priority

Queue/Bandwidth/Bandwidth Remaining

64BRKARC-2003


Default Interface Queues P1 P2 P3 L

Level 4

Level 3

Level 2

Level 1

Queues

Schedulers

Schedulers

Schedulers

66BRKARC-2003


MQC Hierarchy in Queuing ASIC

policy-map child

class c1

priority level 1

police rate 640 kbps

class c2

bandwidth 20 mbps

class class-default

bandwidth 1 mbps

!

policy-map parent

class class-default



!

interface GigabitEthernet0/0/0/0

service-policy output parent

P1 P2 P3 L

Port default queues

c1 c2 cd-c

MQC queues

Inactive entity

Active entity

cd-p

L1

L2

L3

L4

cd-c

cd-p

67BRKARC-2003


MQC Hierarchy in Queuing ASICpolicy-map child

class c1

priority level 1

police rate 640 kbps

class c2

bandwidth 20 mbps

class class-default

bandwidth 1 mbps

!

policy-map parent

class class-default



!

interface GigabitEthernet0/0/0/0.1


!

interface GigabitEthernet0/0/0/0.2


Port default queues

c1 c2 cd-c

G0/0/0/0.1

Inactive entity

Active entity

P1 P2 P3 L c1 c2 cd-c

G0/0/0/0.2

cd-p

L1

L2

L3

L4

cd-p

cd-c

cd-p

68BRKARC-2003


Pop Quiz ????

69BRKARC-2003

For an incoming untagged layer 2 frame, what is the priority value used when the frame is processed inside ASR9000?

• 2

• COS bit

• 802.1p Value

• 0

IOS-XR & IOS-XR 64 Bit


IOSd

Kernel

Linux-BinOSH

oste

d A

pp

1

Ho

ste

d A

pp

2

Operational Infra

Virtualization Layer

IOS “Blob”

Cisco IOS Cisco IOS-XE Classic IOS-XR IOS-XR 64 Bit

XR Code v2

Kernel

Linux, 64bit

Distributed Infra

BG

P

OS

PF

PIM

AC

L

QoS

LP

TS

SN

MP

XM

L

NetF

low

Kernel

Linux, 64bit

System

Admin

XR Code v1

Kernel

Linux, 64bit

Distributed Infra

BG

P

OS

PF

PIM

AC

L

QoS

LP

TS

SN

MP

XM

L

NetF

low

Kernel

QNX, 32bit

Distributed Infra

BG

P

OS

PF

PIM

AC

L

QoS

LP

TS

SN

MP

XM

L

NetF

low

Control

Plane

Data

Plane

Mgmt

Plane

1990s 2000s 2003-04 Present Day

Cisco IOS – A Recap

Incremental Development, with Industry leading investment protection

71BRKARC-2003


IOS XR Evolution: XR 64 bit Architecture

IOS-XR

IOS XR

QNX

QNX

Linux

Linux

Routing Apps

SystemAdmin

Routing Control Plane

Admin Plane

LC-CPUs

RP

Lin

e C

ard

LC-CPU

Separate Admin Plane

64 bit Linux Kernel

Linux VM

64-bit IOS XR.

Admin Plane

Linux-based Virtualized

IOS XR 64 Bit

RP

Lin

e C

ard

IOS-XR

IOS-XR

Linux Linux

Linux Linux

Classic IOS XR

72BRKARC-2003


IOS XR 64 Bit Packaging

74BRKARC-2003

Bootable Images

Minimum Image asr9k-mini-x64-6.1.2.iso Core packages: OS, Admin, Forwarding, Modular Services

Card, Basic Routing, SNMP, Alarm Correlation

Golden ISO Customized ISO image includes mini ISO + required packages + SMUs + XR config

Optional Feature Packages

asr9k-eigrp-x64-1.0.0.0-r612.x86_64.rpm

asr9k-isis-x64-1.1.0.0-r612.x86_64.rpm

asr9k-ospf-x64-1.1.0.0-r612.x86_64.rpm

asr9k-m2m-x64-2.0.0.0-r612.x86_64.rpm

asr9k-mgbl-x64-3.0.0.0-r612.x86_64.rpm

asr9k-mpls-te-rsvp-x64-1.2.0.0-r612.x86_64.rpm

asr9k-mpls-x64-2.1.0.0-r612.x86_64.rpm

asr9k-mcast-x64-2.0.0.0-r612.x86_64.rpm

asr9k-optic-x64-1.0.0.0-r612.x86_64.rpm

asr9k-li-x64-1.1.0.0-r612.x86_64.rpm

asr9k-k9sec-x64-3.1.0.0-r612.x86_64.rpm


IOS XR 64 Bit Packaging - GISO – Golden ISO

• GISO is a customized iso which is built as per individual customer needs.

• GISO contains Mini ISO + rpms + SMUs + config

How to build GISO: use tool provided on the router at /pkg/bin/gisobuild.py in XR domain.

Usage: gisobuild.py [-h] -i BUNDLE_ISO [-r RPMREPO] [-c XRCONFIG] [-l GISOLABEL]

[–m] [-v]

Example: gisobuild.py -i asr9k-mini-x.iso -r . -c config-file -l v1

Script Parameter Expansion Explanation Required/optional

-I BUNDLE_ISO Path to mini ISO Required

-r RPMREPO Path to RPM repo Optional

-c XRCONFIG Optional

-l GISOLABEL GISO Label Optional

-m migration To build migration tar for ASR9K only. Optional

-v version Print script version and exit Optional

-h help Print help menu N/A

BRKARC-2003 75


Migrating Classic XR to IOS XR 64 Bit

Follow below link for details:

https://www.cisco.com/c/en/us/td/docs/routers/asr9000/migration/guide/b-migration-to-ios-xr-64-

bit/b-migration-to-ios-xr-64-bit_chapter_011.html

Pre-6.1.3

5.x.y/4.x.y

cXRcXR 6.2.x

or later

FPDUpgrade

eXR 6.2.x

eXR 6.3.x

eXR

Classic XRCorresponding

To Target 64 Bit XR

Target 64 Bit XR

Two Ways to Migrate:1. CSM Orchestrated Migration2. MOP: Manual Migration

eXR Migration

BRKARC-2003 76

https://www.cisco.com/c/en/us/td/docs/routers/asr9000/migration/guide/b-migration-to-ios-xr-64-bit/b-migration-to-ios-xr-64-bit_chapter_011.html


Migration Pre-requisites

• Back up admin/XR configuration to external server

Backup cfg to External Server

(Calvados, XR)

• Any pre-6.1.3 release needs to be upgraded to classic XR corresponding to target IOS XR 64 Bit version

Upgrade cXR

• All hardware components, Chassis, RSP/RP, LC, FC, FAN and PEM, should be supported in ASR9K 64 bit. Any unsupported hardware may fail to boot after migration

HW Component Check

• All hardware components must be in operational state before migration

Operational Status

BRKARC-2003 77


ASR 9000 System Migration Example to Lightspeed

RP2/RSP4

RP2/RSP4

SFC2

SFC2

SFC2

SFC2

SFC2

Classic XR 5.3.4

RP2/RSP4

RP2/RSP4

SFC2

SFC2

SFC2

SFC2

SFC2

Classic XR 6.5.1

RP2/RSP4

RP2/RSP4

SFC2

SFC2

SFC2

SFC2

SFC2

64 Bit XR 6.5.1

RP3/RSP5

RP3/RSP5

SFC3

SFC3

SFC3

SFC3

SFC3

64 Bit XR 6.5.1

Tomahawk Tomahawk Tomahawk Lightspeed

Upgrade FPD with cXR 6.5.1 FPD

BRKARC-2003 78


Questions?

BRKARC-2003 79

Conclusion

• ASR9000 - Truly Carrier-Class Edge Router Provides:

• Rich Features, Flexible Service Capability

• Variety of Hardware to Meet Different Capacity Requirements

• Fully Distributed Architecture for High Performance

and System Scalability

• Uniform, Open and Modularized Software Architecture


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83BRKARC-2003

Thank you

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