CISC RISC - staffweb.worc.ac.uk fileHere’s Sam-RISC Data Memory Instruction reg Code Memory ALU r1...
Transcript of CISC RISC - staffweb.worc.ac.uk fileHere’s Sam-RISC Data Memory Instruction reg Code Memory ALU r1...
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CPU CPU Mem Mem
CISC RISC
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add eax, [ebx] add[ecx],eax
ld r1, [r2] add r1,r1,r3 add r1,r1,r4 st r1 [r5]
add eax, [1] add[2],eax
ld r1, [1] add r1,r1,r2 add r1,r1,r3 st r1 [2]
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Example
add r3,r1,r1 add rd,rs,rt
str r6,[r1 + 1] str rd, [rs + c]
st r0, [r1] st rd, [rs]
ldr r2,[r3 + 4] ldr rd, [rs + c]
ld r2,[4] ld rd, [rs]
ldi r0,3 ldi rd,C
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Let’s build a Computer
Let’s take a RISC. What do we need ?
• Memory
• Registers
• ALU
• Control Circuits
• A programming language
• A good Name - Simple Although Meaningful
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Here’s Sam-RISC
Data
Memory
Instruction reg
Code
Memory ALU
r1
r2
r0
X
Y
W
X Y
W
0
1
7 mar
mdr
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The Instruction Register
001010 00010 00001 00011 unused Code
Memory
Add r2,r1,r3
add 2 1 3
3 1 2
Loaded with the instruction, the IR decodes this into bits which drive the
CPU digital logic circuits
add
Electronic Wires
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Control Path
001010 00010 00001 00011 unused
000101 00010 00001 00011 unused
add r2, r1, r3
sub r2, r1, r3
ALU
ALU
+
+
-
-
The add instruction is decoded and produces digital signals which select the + function in the ALU Add !
Subtract !
The sub function decoded produces different digital signals
r1 r3
r1 r3
r2
r2
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Sam-RISC and ARM-Cortex are 32 bit
001010 00110 01001 00011 unused
001010 00110
001010 00010 00001 0101001111111011
opcode rd rs rt unused
opcode rd rs c (16-bit address)
add rd,rs,rt
ldr rd,[rs+c]
ldr rd,[c]
opcode rd c (21-bit address)
32 bits wide
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‘Load Immediate’
Constant C rd ldi
opcode destination
In load immediate we get the constant C immediately following the opcode into the reg.
ldi r9 , 5
5
5 r9
All reference to memory has
gone!
Load ‘5’ straight into r9
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unused
A simple ‘Load’ instruction
‘Load into rd the contents of memory at address which is in reg rs.’ Simple!
7
69 6
231 5
115 4
145 3
2
1
0
ldr r9 , [r1]
3
145 r9
145
rs rd ld
opcode destination
Single source reg
1. Let’s say have already
loaded r1 with 3 2. Get data from mem at addr r1 (=3)
2. Load the data into r9
memory
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A more complex ‘Load’
constant c rs rd ldr
opcode destination
Source
Load register rd with the contents of memory which you find at address r1 + c.
7
69 6
231 5
115 4
145 3
2
1
0
ldr r9 , [r1 + 2]
3 + 2
5
231 r9
231
The mem address
is formed as a sum
memory
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