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Circulating Current Suppression in Parallel Interleaved 2L VSIs Using Modified CM OffsetBased Method during Inductors Mismatch Condition

Shukla, Kapil; Maheshwari, Ramkrishan

Published in:IEEE Transactions on Industry Applications

DOI:10.1109/TIA.2020.3006464

Publication date:2021

Document version:Accepted manuscript

Citation for pulished version (APA):Shukla, K., & Maheshwari, R. (2021). Circulating Current Suppression in Parallel Interleaved 2L VSIs UsingModified CM Offset Based Method during Inductors Mismatch Condition. IEEE Transactions on IndustryApplications, 57(3), 3143-3153. [9133297]. https://doi.org/10.1109/TIA.2020.3006464

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Abstract— Parallel interleaved two-level (2L) voltage

source inverters (VSIs) could be analyzed as a single multilevel VSI and hence a significance reduction in the grid side voltage and current ripple could be achieved. However, the parallel interleaved VSIs have a major issue of circulating current. The circulating current is mainly composed of two frequency components: high frequency component and low frequency component. The high frequency component is generated due to the instantaneous difference in the common-mode (CM) voltages of the VSIs. While due to inductance value mismatch in the ac side line frequency inductors, a low frequency circulating current also flows in the system. This low frequency component needs to be controlled as it could saturate the CM, coupled, or interphase inductors used for limiting the high frequency component of circulating current. In this paper, an analysis is carried out for circulating current during the inductors mismatch condition. A CM offset signal is also proposed to limit the flow of low frequency component of the circulating current. The proposed CM offset is derived in terms of existing CM offset signals, and hence any existing pulse-width modulation (PWM) technique could be implemented using the proposed method. Simulation and experimental results show the improvement in the circulating current using the proposed modified offset.

Index Terms— Circulating Current, Voltage Source Inverter

(VSI), Interleaving, Pulse-width Modulation (PWM).

I. INTRODUCTION Parallel interleaved voltage source inverters (VSIs) are

conventionally used to deliver higher amount of power. Along with high power delivery, modularity, reduced current stress on switches, higher efficiency, better thermal management are the other major advantages of parallel interleaved VSIs [1]-[4]. The parallel interleaved VSIs are modulated using interleaved high frequency carrier signals to reduce the load or grid side harmonics [5]. However, due to interleaving, there

Manuscript received February 14, 2020; revised June 23, 2020; accepted June 28, 2020.

K Shukla is with the Department of Electrical Engineering, MNIT Jaipur, Rajasthan, India (e-mail: kapil.ee@mnit.ac.in).

R. Maheshwari is with Centre for Industrial Electronics, University of South Denmark, Denmark (e-mail: ramkrishan@mci.sdu.dk).

occurs an instantaneous common-mode (CM) voltage difference among the VSIs. This CM voltage difference produces a current to flow between the VSIs, and is termed as circulating current [6]. The circulating current is primarily composed of two components, a high frequency component and a low frequency component [7]. The high frequency component depends on the interleaving angle among the carrier signals and is restricted by using coupled, CM, or interphase inductors [8]-[11]. Along with these inductors, CM minimization based modulation techniques [10]-[11] are also proposed in the literature to minimize the circulating current flow. However, these techniques mainly deal with the high frequency component of the circulating current. The zero-sequence component of the circulating current is also restricted using proportional-integral (PI) controllers [11]-[19]. However, the conventional PI controllers cannot be used for restricting the low frequency circulating current which is generated due to the mismatch in the ac side line frequency inductors [17]-[20], which can occur due to ageing, inter-turn faults [21], tolerances [25], and inductor core properties [26]. This low frequency circulating current could saturate the CM or coupled inductors which are used to limit the high frequency circulating currents. Moreover, the low frequency circulating current introduces additional stress on the switches and reduces the power density of the system.

Vdc/2

A1S11’

S12’S14’

S15’

S16’

S13’

S22’S24’

S25’

S26’

S23’

Vdc/2

O

S21’

N

A

B

C

iA1

iA2

iA

LA2

B1C1

A2B2

C2

RB1

RB2

LB1LC1

LB2

RC2 LC2

RA2

RC1

LA1RA1

iB1iC1

iB2iC2

iB

iC vC

vB

vA

Fig. 1. Parallel interleaved VSIs connected to grid fed from a common dc-link. The parallel interleaved two-level (2L) VSIs having common ac and dc sides are shown in Fig. 1. For this system, the low frequency circulating current caused by the mismatch in the ac side inductors is minimized using a zero-sequence

Circulating Current Suppression in Parallel Interleaved 2L VSIs using Modified CM Offset

based Method during Inductors Mismatch Condition

Kapil Shukla and Ramkrishan Maheshwari, Senior Member, IEEE

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.The final version of record is available at http://dx.doi.org/10.1109/TIA.2020.3006464

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voltage modulation strategy in [17]. A feed-forward term is added to the zero-sequence PI controller, and then depending on the reference signals, duty cycles are generated. Another duty cycle correction based control strategy is proposed in [18]. In both the above methods, the mismatch among the line inductance values of a VSI is not considered. The inductance values of all phases of a single VSI is kept same, which is different from the inductance values of all phases of other VSI. The system with different inductance value for different phases is considered in [19]. A proportional-integral-resonant (PIR) controller along-with a feed-forward term is proposed in [19], to reduce the low frequency circulating current flow. To implement this control strategy, information of every non-zero vector is required in every switching period (Ts) to calculate the dwell times of the zero vectors, which makes it difficult to operate. In addition, the proposed method does not eliminate the low frequency component completely when the individual VSI phase inductors are different. The low frequency circulating current is also minimized in [20] by averaging the CM offsets of individual VSIs. In [20], the unbalance in grid voltages is only considered. The inductors of individual VSIs are kept same. Furthermore, this approach does not suppress the low frequency circulating current completely as same zero-sequence voltage for both the VSIs is considered. Moreover, all the methods proposed in [17] - [20], had not considered the mismatch in internal resistances of the inductors [27]. The online detection of inductance variation is already available in literature [21], [26]. This paper focuses on reduction of low frequency circulating current for the available variation in the inductance and resistance values of line frequency inductors and has following key points:

1. The mismatch in internal resistances of the inductors is considered, and the dynamic equation of the circulating current is derived for inductance and resistance value mismatch of the ac side line frequency inductors.

2. Using the dynamic circulating current equation, a simple modified CM offset based method is proposed for suppressing the low frequency circulating current in parallel interleaved 2L VSIs under line frequency inductors mismatch condition.

3. The modified CM offset is calculated in terms of generated three-phase reference signals of individual VSIs, grid voltages, individual VSI currents, and line frequency inductors. Therefore, correct information of line frequency inductors of each phase of individual VSIs is required to suppress the low frequency circulating current accurately.

4. The proposed CM offset can be used along-with any existing CM offset to implement a particular PWM technique.

The paper is organized as follows. Section II reviews the modelling of parallel interleaved VSIs under inductors mismatch condition. Section III explains the circulating current and its components. Section IV and V focus on the proposed modified CM offset based PWM technique and control scheme, respectively. Simulation results are displayed in section VI. Experimental results are shown in section VII. Conclusions are provided in section VIII.

II. PARALLEL VSIS MODELLING UNDER INDUCTORS MISMATCH CONDITION

The two parallel interleaved 2L VSIs connected to a common dc-link is shown in Fig. 1. The equation that governs the ac side inductor current dynamics is given by

NN xxjxj

xjxjxj vvdt

diLRi −=⋅+⋅ (1)

where x = A,B,C and j = 1,2. ixj represents the line current of phase x, VSI j. vxjN is the generated voltage of phase x, VSI j. Rxj and Lxj are the internal resistance and inductance of line frequency inductor of phase x, VSI j, respectively. vxN is the grid voltage of phase x. As an example, iA1 represents line current of phase A, VSI 1 for x = A and j =1.

The line frequency inductors and their internal resistances of all the phases of both the VSIs are assumed to be different. Considering, R and L, to be the ideal value of internal resistance and inductance of line frequency inductors, respectively. The inductance and internal resistance of each VSI could be written as

LqLRpR xjxjxjxj ⋅=⋅= , (2)

where pxj and qxj are the multiplying factors of the internal resistances and inductances of the line frequency inductors, respectively for phase x, VSI j. Now, the generalized equation (1) could be expanded in six different equations. Adding all these six equations, the potential vNO is calculated, which is used to model the parallel VSIs. The potential vNO is given by

( )L

RRLL

hvvvvvv

v VSI2,1VSI,2VSI,1VSI,CM2CM1NO

33 ∆−∆−∆−∆−⋅+⋅= (3)

where

=

= ∑∑

== CB,A,O22CM

CB,A,O11CM 3

1,31

xx

xx vvvv

(4)

( )N1O

CB,A, 1

11VSI,

1xx

x x

xL vv

qq

v −⋅

−=∆ ∑

= (5)

( )N2O

CB,A, 2

22VSI,

1xx

x x

xL vv

qq

v −⋅

−=∆ ∑

= (6)

( )Ri

qqp

v xx x

xxR ⋅

=∆ ∑

=

−1

CB,A, 1

111VSI,

(7)

( )Ri

qqp

v xx x

xxR ⋅

=∆ ∑

=

−2

CB,A, 2

222VSI,

(8)

∑

==

=

1,2 C,B,A,

1jx xj

L qh (9)

where vx1O and vx2O are the pole voltages of phase x for VSI 1 and 2, respectively. vCM1 and vCM2 are the CM voltages of VSI 1 and 2, respectively. ΔvL,VSI1 and ΔvL,VSI2 are the extra inductive drops due to the mismatch in inductance values. ΔvR,VSI1 and ΔvR,VSI2 are the extra resistive drops due to the unequal mismatch in the internal resistance and inductance values. In case of equal internal resistance and inductance values, pxj = 1, qxj = 1, ΔvL,VSI1 = 0, ΔvL,VSI2 = 0, ΔvR,VSI1= 0, ΔvR,VSI2 = 0, and vNO would be the average of the CM voltages of VSI 1 and VSI 2.

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III. CIRCULATING CURRENT AND ITS COMPONENTS

The parallel interleaved 2L VSIs are generally modulated using various PWM techniques [1], [3], [23]. For carrier-based PWM techniques, the carrier signals of high frequencies are used. These high frequency carrier signals are phase shifted (interleaved) ideally by 180° for two parallel 2L VSIs, for reducing the load or grid side harmonics. However, this interleaving of carrier signals introduces an instantaneous CM voltage difference between the VSIs. Since the VSIs are connected to a common dc-link, a current starts to flow between the VSIs, and is termed as circulating current. The circulating current (iCC) equation for the two parallel interleaved VSIs is given by [6]

−

=⋅+⋅

22CM2CM1CC

CCvv

dtdi

LRi (10)

where

( )C1B1A1CC 31 iiii ++= (11)

The work presented in [6] has only considered the balanced inductors condition. However, under the inductors mismatch condition, an additional low frequency current component along-with the high frequency current component appears in the circulating current. A detailed expression for circulating current under inductors mismatch condition is derived in this paper. Here, a three-phase, three-wire system on the ac side has been considered (Fig. 1) and for this case, the zero-sequence component of the grid side or the load side currents is zero. Therefore, the zero-sequence component of the VSI 1 currents, which is defined as the circulating current (11), will be equal and opposite to the zero-sequence component of VSI 2 currents. Moreover, under balanced inductors condition, the equation (10) would be valid for both balanced and unbalanced grid or load conditions. However, (10) does not hold good during inductors mismatch condition. The circulating current during the inductors mismatch condition is derived using (1) – (9) as given by

( )[ ]

( )[ ]

( )

( ) ( )[ ]12VSI,2VSI,21VSI,1VSI,

1CM22CM1

12VSI,2VSI,CM2

2VSI1,1VSI,CM1CCCC

33

13

33

3

LRLLRL

LLL

L

LRL

L

LRL

hvvhvv

hvhvh

hhvvv

hhvvv

dtdi

LRi

∆+∆−∆+∆−

−⋅⋅

=

⋅

⋅∆−∆−⋅−

⋅

⋅∆−∆−⋅=⋅+⋅

(12)

where ∑∑==

=

=

CB,A, 22

CB,A, 11

1,1x x

Lx x

L qh

qh

The right hand side (RHS) of circulating current expression in (12) has two components. One of the components depends on the CM voltages, and the other component depends on the extra inductive and resistive drops. Therefore, these components in (12) may produce a low frequency circulating current. This low frequency circulating current needs to be suppressed as it could saturate the CM and coupled inductors, which are normally used to limit the high frequency circulating current. Moreover, the low frequency circulating current would increase the losses in the system and hence the power density will be reduced.

IV. SUPPRESSION OF CIRCULATING CURRENT USING MODIFIED CM OFFSET

As discussed in the previous section, the circulating current is composed of two components, a CM voltage dependent component, and an extra inductive and resistive drop dependent component. Conventionally, the CM voltage is dependent on the CM offset voltage, which is added to the three-phase original reference signals in a way that the line-line voltage is not changed to get modified reference signals, which is used to implement various carrier based PWM techniques [6]. The carrier signals, modified reference signals, and corresponding pole voltages using the conventional SVPWM technique are shown in Fig. 2 for both the VSIs. If the carrier signal is varied from +Vdc/2 to –Vdc/2, the pole voltage of a phase averaged over a switching period is equal to the magnitude of the modified reference signal of corresponding phase for that switching period. Therefore, using (4), the CM voltages averaged over a switching period are given by

( )( ) TsTsT

TsTsT

vvv

vvv

off2sum2ref,sCM2

off1sum1ref,sCM1

3

3

+=

+=

(13)

where

∑∑

==

==CB,A,

ref2N,sum2ref,CB,A,

ref1N,sum1ref, ,x

xx

x vvvv (14)

where vx1N,ref and vx2N,ref are the three-phase original reference signals of VSI 1 and 2, respectively. voff1 and voff2 are the CM offset voltages of VSI 1 and 2, respectively. The summation of three-phase reference voltage signals, vref,sum1 and vref,sum2 will be zero for balanced conditions. However, during inductors mismatch condition, the summation of reference voltage signals, vref,sum1 and vref,sum2, may not be zero for balanced inductor currents [24]. Moreover, during the inductors mismatch condition, a low frequency circulating current may flow through the VSIs. To minimize the low frequency circulating current, a PWM technique based on averaging the CM offsets for active-front end rectifiers having unequal terminal voltages is proposed in [20]. The averaging of CM offsets reduces the low frequency circulating current. However, the dynamic equation of the circulating current is not considered in [20], and hence the averaging CM offset based PWM technique does not suppress the low frequency circulating current completely. Moreover, to avoid any low frequency circulating current, the average of circulating current over a switching period must be zero [6], i.e.

0CCCC =⋅+⋅

Tsdtdi

LRi (15)

Therefore, to minimize the low frequency circulating current, the R.H.S of (12) averaged over a switching period must be zero, i.e.

( )

( ) ( )[ ] 0

33

1

12VS,2VSI,21VSI,1VSI,

1CM22CM1

=∆+∆−∆+∆−

−⋅⋅

TsLIRLLRL

LLL

hvvhvv

hvhvh (16)

Using (13) – (16), the modified CM offset voltage signal

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(voff2m) of VSI 2 is calculated and is given by

−+

∆+∆+

∆+∆−=

33sum2ref,sum1ref,

2

2VSI,ref2

1

1VSI,ref1off1off2m

vv

hvv

hvv

vvL

R

L

R

(17)

where

( )Nref1N,CB,A, 1

1ref1

1xx

x x

x vvq

qv −⋅

−=∆ ∑

=

(18)

( )Nref2N,CB,A, x2

2ref2

1xx

x

x vvq

qv −⋅

−=∆ ∑

=

(19)

The modified offset voltage signal (voff2m) of VSI 2 using (17) will suppress the low frequency circulating current. This suppression in low frequency component would reduce the net flux in the CM and coupled inductor cores. These CM and coupled inductors are conventionally designed to restrict the path for high frequency circulating current. The additional flux production due to the low frequency current could saturate these inductors. The proposed method avoids this sort of inductor saturation.

0

0

Carrier 1(VSI 1)

+Vdc/2

vA1N,ref + voff1

vB1N,ref + voff1

vC1N,ref + voff1

Ts

+Vdc/2

+Vdc/2-Vdc/2

-Vdc/2+Vdc/2-Vdc/2

-Vdc/2

vA1O

vB1O

vC1O

+

+ + + +

++

+

+ + + + + +

Ts/2

vCM1

-Vdc/2

+Vdc/2+Vdc/6

-Vdc/6

vA2N,ref + voff2

Carrier 2(VSI 2)

vB2N,ref + voff2

vC2N,ref + voff2

+ +++

+ + + + + +

++vA2O

vB2O

vC2O

vCM2

Fig. 2. Switching pattern of VSI1 and VSI 2.

V. CONTROL SCHEME The control block diagram [22] for generating the three-

phase reference voltage signals of VSI 1 is shown in Fig. 3. The control block of VSI 2 is similar to that of VSI 1 as shown in Fig. 4. However, circulating current PI controller (Kpz & Kiz) for VSI 2 is not needed as same circulating current flows through both the VSIs. Therefore, controlling circulating current of one VSI would automatically control the circulating current of the other VSI. In addition, for VSI 2, the CM offset addition would be different from that of VSI 1 as shown in Fig. 4. In the control block diagrams of VSI 1 and 2, idref1, iqref1, idref2, and iqref2 are the dc reference currents for the d-axis and q-axis PI current controllers (Kp & Ki) of VSI 1 and 2. The PI current controller of zero-axis is used to control the circulating current (iCC). The circulating current is calculated using the ABC to dqz transformation block as the circulating current is nothing but the zero-sequence current [20]. The

theta (ϴ) required for dqz to ABC or ABC to dqz conversion is generated using the synchronous reference frame based phase locked loop (PLL) [22]. Using the PI controllers and the feed-forward dc values of grid voltages (vgd and vgq), the three-phase reference voltage signals of VSI 1 and 2 are generated. These three-phase reference voltage signals are then used to compute the CM offset voltage signals (voff1 and voff2m) which will be added to the generated three-phase reference voltage signals. The CM offset voltage signal (voff1) would vary depending on the PWM technique, and hence the modified CM offset (voff2m) would also vary accordingly.

Lω

Lωd1i

q1i

qref1i

d1i∆

q1i∆

dref1v

qref1v

dref1i

PI

PI

dqz to αβ0

gdv

gqv zvθ

αβ0 to ABC

A1N,refvB1N,refv

C1N,refv

A1N,ref off1v v+B1N,ref off1v v+C1N,ref off1v v+

CM Offset

Addition

Voltage Reference Generation PLL [22]Bv

CvAv

θ

PICCi0

θ

Av ABC to dq [22]

BvCv

gdvgqv

A1i

θ

ABC to dq [22]B1i

C1i

d1iq1i

CCi

Fig. 3. Control block diagram of VSI 1.

d2i

q2i

dref2i

A2N,ref off2mv v+B2N,ref off2mv v+C2N,ref off2mv v+

CM Offset Addition

Using (17)

A2N,refv

B2N,refvC2N,refv

Voltage Reference Generation

(Fig. 3)

qref2ioff1v

(18) (19)

(12) (7)

(8)

ref,sum1 ref,sum2v v(14)gdv gqv 1 2,L Lh h

ref1v∆ ref2v∆,VSI2Rv∆

, 1Rv∆ VSI

Fig. 4. Control block diagram of VSI 2.

VI. SIMULATION RESULTS A MATLAB-Simulink® model of the parallel interleaved

2L VSIs system has been developed. The system parameters and control parameters are shown in Table I and Table II, respectively. The inductors normally have tolerance levels of ±15% [25]. The variation in inductance values could also be due to ageing, inductor core properties [26], and inter-turn faults [21]. To highlight the effectiveness of the proposed method at the worst conditions, the inductance and internal resistance values of line frequency inductor of phase A of VSI 1 is increased by 15%. While for phase C of VSI 1, the inductance and internal resistance values are decreased by 15%. The inductance and internal resistance values of all the other line frequency inductors are kept to their ideal values. Different PWM techniques are compared with each other for equal and unequal sharing of current among the VSIs. The multiplying factors and current reference values for two different cases under consideration are tabulated in Table III.

TABLE I SYSTEM PARAMETERS

Parameter vA, vB, vC R L Vdc Ts Value 150 V 1.4 Ω 27 mH 500 V 200 µs

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TABLE II

CONTROL PARAMETERS Parameter Kp Ki Kpz Kiz

Value 67.5 3500 120 5000

TABLE III

PARAMETER VALUES DURING DIFFERENT CASE STUDIES

Parameter Value

Case 1 Case 2 pA1 1.15 1.15 qA1 1.15 1.15 pC1 0.85 0.85 qC1 0.85 0.85

pB1, pA2, pB2, pC2 1 1 qB1, qA2, qB2, qC2 1 1

idref1 2.5 A 3.5 A idref2 2.5 A 1.5 A

iqref1, iqref2 0 A 0 A

A. Conventional SVPWM The CM offset voltage signals of both the VSIs are

calculated using the conventional SVPWM technique [6]. The CM offset voltage signals of both the VSIs are given by

2

22min2max

off2

1min1maxoff1

vvv

vvv

−−=

−−=

(20)

where vmax1 = max (vA1N,ref, vB1N,ref, vC1N,ref), vmin1 = min (vA1N,ref, vB1N,ref, vC1N,ref), vmax2 = max(vA2N,ref, vB2N,ref, vC2N,ref), and vmin2 = min(vA2N,ref, vB2N,ref, vC2N,ref).

iA1, iA2, iCC, and phase A grid current (iA) for case 1 are displayed in Fig. 5. Due to the mismatch in inductors, a low frequency component appears in the circulating current (Fig. 5 (d)). The current waveforms for case 2 are displayed in Fig. 6. Due to the difference in the VSIs currents, a high value of circulating current flows through the VSIs as displayed in Fig. 6(d). This low frequency circulating current also affects the individual VSIs current profile as displayed in Fig. 6 (b).

B. Reduced CM Voltage Difference PWM Techniques[11] Several PWM techniques are proposed in literature to

reduce the CM voltage difference between the VSIs. These techniques utilize only active vectors to synthesize a given voltage reference vector and hence reduces the CM voltage difference. The reduction in CM voltage difference would also lead to reduction in the circulating current [6]. Among these reduced CM voltage based techniques, Active-Zero State PWM (AZSPWM) [11] is most commonly used, and hence it is implemented in this paper for both the cases as per the procedure provided in [11]. The results for both the cases are shown in Figs 7-8, and from the results, it could be inferred that the high-frequency component of the circulating current is reduced as compared to the conventional SVPWM technique. However, the low-frequency component of the circulating current is still a major concern during the inductors mismatch condition.

(a) (b)

(c) (d)

Fig. 5. Simulated current waveforms for Conventional SVPWM with case 1 (a) VSI 1 phase A current (b) VSI 2 phase A current (c) Phase A grid current (d) Circulating current.

(a) (b)

(c) (d)

Fig. 6. Simulated current waveforms for Conventional SVPWM with case 2 (a) VSI 1 phase A current (b) VSI 2 phase A current (c) Phase A grid current (d) Circulating current.

(a) (b)

(c) (d)

Fig. 7. Simulated current waveforms for AZSPWM with case 1 (a) VSI 1 phase A current (b) VSI 2 phase A current (c) Phase A grid current (d) Circulating current.

(a) (b)

(c) (d)

Fig. 8. Simulated current waveforms for AZSPWM with case 2 (a) VSI 1 phase A current (b) VSI 2 phase A current (c) Phase A grid current (d) Circulating current.

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C. CM Injection PWM [20] The CM injection PWM technique is proposed in [20],

where the average of both the CM offset voltage signals is implemented to modulate the individual VSIs. The average CM offset voltage signal (voffavg) is given by

2off2off1

offavgvv

v+

= (21)

The CM offsets (voff1 and voff2) are calculated using (20). This CM injection PWM is also implemented for both the cases. During the case 1 implementation, the circulating current improves due to implementation of this PWM technique. However, there is still a low frequency harmonic component in the circulating current as shown in Fig. 9 (d).The current waveforms for case 2 are displayed in Fig. 10. The circulating current improves considerably as compared to the conventional SVPWM technique. However, a low frequency component still exists in the circulating current as shown in Fig. 10 (d). The individual phase currents of both the VSIs also improved significantly (Fig. 10 (a) and 10 (b)).

(a) (b)

(c) (d)

Fig. 9. Simulated current waveforms for CM Injected PWM with case 1 (a) VSI 1 phase A current (b) VSI 2 phase A current (c) Phase A grid current (d) Circulating current.

(a) (b)

(c) (d)

Fig. 10. Simulated current waveforms for CM Injected PWM with case 2 (a) VSI 1 phase A current (b) VSI 2 phase A current (c) Phase A grid current (d) Circulating current.

D. Proposed Modified CM offset based Method with Conventional SVPWM and AZSPWM Techniques

To suppress the low frequency component of the circulating current, a modified CM offset voltage signal based method is proposed in this paper and is tested using the conventional SVPWM and AZSPWM techniques. The modified CM offset (voff2m) is derived in terms of voff1 using (17) and is added to

the generated three-phase reference voltage signals (vA2N,ref, vB2N,ref, vC2N,ref) to modulate VSI 2. The voff1 for modulating VSI 1 is calculated using (20). The results using the conventional SVPWM technique for Case 1 and 2 are displayed in Figs. 11 and 12, respectively. While the results using the AZSPWM technique with proposed method for the two cases are shown in Figs. 13 and 14. The low frequency component of the circulating current is totally eliminated using the proposed CM offset addition based method as shown in Figs. 11 -14 (d). Moreover, the high frequency component reduces significantly using AZSPWM as shown in Figs. 13(d) & 14 (d). To highlight the effectiveness of the proposed method, a comparison of peak-peak circulating current using different PWM techniques for both the cases is shown in Table IV.

(a) (b)

(c) (d)

Fig. 11. Simulated current waveforms for proposed modified CM offset based method using SVPWM with case 1 (a) VSI 1 phase A current (b) VSI 2 phase A current (c) Phase A grid current (d) Circulating current.

(a) (b)

(c) (d)

Fig. 12. Simulated current waveforms for proposed modified CM offset based method using SVPWM with case 2 (a) VSI 1 phase A current (b) VSI 2 phase A current (c) Phase A grid current (d) Circulating current.

(a) (b)

(c) (d)

Fig. 13. Simulated current waveforms for proposed modified CM offset based method using AZSPWM with case 1 (a) VSI 1 phase A current (b) VSI 2 phase A current (c) Phase A grid current (d) Circulating current.

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(a) (b)

(c) (d)

Fig. 14. Simulated current waveforms for proposed modified CM offset based method using AZSPWM with case 2 (a) VSI 1 phase A current (b) VSI 2 phase A current (c) Phase A grid current (d) Circulating current.

TABLE IV

SIMULATED COMPARISON OF PEAK-PEAK CIRCULATING CURRENT

Current Sharing

Peak-Peak Circulating current, iCC (A)

SV

PWM

AZS PWM

CM Injection

PWM

SVPWM with

Proposed Method

AZSPWM with

Proposed Method

Equal 0.62 0.28 0.48 0.46 0.17 Unequal 0.88 0.72 0.77 0.47 0.17

The CM offset voltage waveforms comparison using the

conventional SVPWM technique and the proposed modified CM offset based method for both the cases are shown in Fig. 15. A significant improvement in the CM offset voltage waveforms is visible in Fig. 15.

(a) (b)

(c) (d)

Fig. 15. Simulated CM offset voltage waveforms with case 1 (a) Conventional SVPWM, (b) SVPWM using Proposed Method. With case 2 (c) Conventional SVPWM, and (d) SVPWM using Proposed Method.

VII. EXPERIMENTAL RESULTS The experimental implementation of all the different

methods is done with the help of the digital signal controller (DSC) TMS320F28335 from Texas Instruments. The system parameters are kept same as that used for simulation. The experimental setup is displayed in Fig. 16. An extra inductor is connected in series to increase the inductance and resistance values of VSI 1 phase A line frequency inductor. While the inductance and resistance values of VSI 1 phase C inductor is decreased by changing the inductor tapping. Current sensors are used to sense the individual VSI currents. While the voltage sensors are used to sense the grid voltages. The iA1,

iA2, iA, and iCC for balanced inductor condition using conventional SVPWM are displayed in Fig. 17. Since under practical conditions, the inductors could not have same inductance and resistance values. Therefore, a low frequency component could be seen in the circulating current. However, this low frequency component is very low as compared to the component during the inductors mismatch condition as displayed in Fig. 18. The individual VSI phase currents (iA1 and iA2) are shown on the same axis to show the change in magnitude due to the low frequency circulating current and unequal current sharing. A low frequency component appears in the circulating current due to mismatch between the line frequency inductors. The VSIs are also modulated using SVPWM technique for case 2 operating condition and the current waveforms are shown in Fig. 19. A low frequency circulating current appears in the system as shown in Fig. 19.

Fig. 16. Experimental Setup.

A1iA2i

Ai

3 2.72CC A1 B1 C1 Ai i i i⋅ = + + =

Fig. 17. Experimental current waveforms for conventional SVPWM with balanced inductors condition.

A1iA2i

Ai3 4.0CC A1 B1 C1 Ai i i i⋅ = + + =

Fig. 18. Experimental current waveforms for conventional SVPWM with case 1.

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A1i

A2i

Ai

3 6.2CC A1 B1 C1 Ai i i i⋅ = + + =Fig. 19. Experimental current waveforms for conventional SVPWM with case 2.

The parallel interleaved 2L VSIs are also modulated using the CM injection PWM technique for inductor mismatches. The current waveforms for case 1 and case 2 are shown in Figs. 20 and 21, respectively. The CM injection PWM technique improves the circulating current profile as compared to the conventional SVPWM technique. However, the low frequency component is not suppressed completely using the CM injection PWM technique.

A1i

A2i

Ai

3 3.64CC A1 B1 C1 Ai i i i⋅ = + + =

Fig. 20. Experimental current waveforms for CM injection based PWM with case 1.

A1i

A2i

Ai

3 3.7CC A1 B1 C1 Ai i i i⋅ = + + =

Fig. 21. Experimental current waveforms for CM injection based PWM with case 2.

To completely suppress the low frequency component in the circulating current, a modified CM offset based method is proposed in this paper. The current waveforms corresponding to the case 1 and case 2 using the proposed modified CM offset based method with the SVPWM technique are displayed in Figs. 22 and 23, respectively. The CM offset for VSI 1(voff1) is calculated using (20), while the CM offset for VSI 2 is

calculated using (17). The circulating current is suppressed significantly and the low frequency component is eliminated using the proposed modified CM offset based method. The comparison between peak-peak values and root mean square (rms) values of circulating current are shown in Tables V and VI, respectively. The Fast Fourier Transform (FFT) plots for experimental 3.iCC with case 1 and case 2 using all the three methods are also shown in Figs. 24 and 25, respectively. The low frequency component of the circulating current is zoomed in the Figs. 24 and 25. A significant reduction in the low frequency component (50 Hz) using the proposed method could be seen in Figs. 24(c) and 25(c) as compared to the other two methods (Figs. 24(a,b) & 25(a,b)). To quantify the components of circulating current, the low frequency components along-with the dominant high frequency components are also shown in Table VII. The proposed method shows a significant reduction in the low frequency components as compared to the conventional SVPWM and CM injection based PWM techniques.

The transient nature of the proposed CM offset based method using SVPWM technique is also examined and the waveforms are displayed in Fig. 26. The parallel VSIs are first modulated using the conventional SVPWM technique and after some time the modulation method is shifted to the proposed modified CM based method. The suppression in circulating current using the proposed CM offset based method could easily be observed in Fig. 26.

A1i

A2i

Ai

3 2.3CC A1 B1 C1 Ai i i i⋅ = + + =

Fig. 22. Experimental current waveforms for proposed modified CM offset based method using SVPWM with case 1.

TABLE V COMPARISON OF PEAK-PEAK CIRCULATING CURRENT FOR PWM

TECHNIQUES

Current Sharing

Peak-Peak Circulating current, iCC (A)

SVPWM CM

Injection PWM

Proposed Modified CM based Method using

SVPWM Equal (Case 1) 1.33 1.21 0.77

Unequal (Case 2) 2.06 1.23 0.84

TABLE VI COMPARISON OF RMS CIRCULATING CURRENT FOR PWM

TECHNIQUES

Current Sharing

RMS Circulating current, iCC (A)

SVPWM CM

Injection PWM

Proposed Modified CM based Method using

SVPWM Equal (Case 1) 0.311 0.281 0.212

Unequal (Case 2) 0.385 0.286 0.228

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A1i

A2i

Ai

3 2.54CC A1 B1 C1 Ai i i i⋅ = + + =

Fig. 23. Experimental current waveforms for proposed modified CM offset based method using SVPWM with case 2.

(a)

(b)

(c) Fig. 24. FFT plots of circulating current (3.iCC), with case 1. (a) SVPWM (b) CM Injection based PWM (c) Proposed Modified CM based method using SVPWM.

(a)

(b)

(c) Fig. 25. FFT plots of circulating current (3.iCC), with case 2. (a) SVPWM (b) CM Injection based PWM (c) Proposed Modified CM based method using SVPWM.

A1iA2i

Ai

3 CC A1 B1 C1i i i i⋅ = + + Fig. 26. Experimental current waveforms for transition of conventional SVPWM to proposed modified CM based Method with case 1.

VIII. CONCLUSION During the inductors mismatch condition, a low frequency

component of the circulating current usually flows between the parallel connected VSIs. The detailed expression for this

TABLE VII COMPARISON OF HARMONIC COMPONENTS OF CIRCULATING CURRENT (3.iCC)

Current Sharing

PWM Technique

Frequency→

Current Values (A) at Frequency (Hz) 50 100 150 200 250 5000 9850 10150

Equal

SVPWM 0.84 0.02 0.049 0.018 0.035 0.962 0.15 0.13 CM Injection 0.5 0.062 0.018 0.021 0.017 1.027 0.16 0.14

Proposed 0.1 0.053 0.023 0.017 0.006 0.854 0.152 0.133

Unequal

SVPWM 0.96 0.06 0.777 0.03 0.08 0.937 0.145 0.14 CM Injection 0.72 0.067 0.078 0.012 0.01 0.942 0.148 0.14

Proposed 0.11 0.048 0.032 0.02 0.013 0.988 0.142 0.134

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low frequency current which could saturate the CM or coupled inductors is derived in this paper. To avoid this saturation, a modified CM offset based method is also proposed. The proposed modified offset is derived in terms of the CM offset of the VSI 1, and hence any PWM technique could be implemented using the proposed method. The proposed method using the CM offset of SVPWM technique is compared with conventional SVPWM and CM injection PWM technique of [20] to highlight the effectiveness of the proposed method for equal and unequal current sharing conditions among the VSIs. A significant reduction in the low frequency component of the circulating current is achieved using the proposed method.

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Kapil Shukla was born in Dungarpur, India. He received the master of technology (M.Tech.) degree in power systems from the Delhi Technological University (DTU), New Delhi, India in 2012 and the Ph.D degree in Electrical Engineering from the Indian Institute of Technology Delhi, New Delhi, India in 2019.

From 2012 to 2014, he was with the Department of Electrical and Electronics Engineering, Galgotias University, Greater Noida, U.P, India, as an

Assistant Professor. He then joined the Electrical Engineering Department, Manipal University Jaipur, India as an Assistant Professor for a span of one year. He is currently working as an assistant professor with the Department of Electrical Engineering, Malaviya National Institute of Technology Jaipur, Rajasthan, India. His research interests include parallel operation of voltage source inverters, pulse-width modulation techniques, and power quality.

Ramkrishan Maheshwari (S’10 – M’11 – SM’18) was born in Allahabad, India. He received the master of engineering (M.E.) degree in electrical engineering from the Indian Institute of Science (IISc), Bangalore, India in 2005 and the Ph.D. degree in electrical engineering from Aalborg University, Aalborg, Denmark in 2012.

From 2005 to 2008, he was with Honeywell Technology Solution Lab, Bangalore, India. From 2012 to 2014, he was with the Department of Energy

Technology, Aalborg University, Denmark. From 2014 to 2019, he was with the Department of Electrical Engineering, Indian Institute of Technology, New Delhi, India. He is currently working as an Associate Professor with the Center of Industrial Electronics, University of Southern Denmark, Sønderborg, Denmark. His research interests include modeling and control of power converters.

This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.The final version of record is available at http://dx.doi.org/10.1109/TIA.2020.3006464

Copyright (c) 2020 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.