circ-seq
27
Mux-Based Latches Negative latch (transparent when CLK= 0) CLK = 0 1 0 D Q 1 CLK = 1 0 D Q In Clk Q Clk Q ⋅ + ⋅ =
Transcript of circ-seq
Mux-Based LatchesNegative latch(transparent when CLK= 0)
CLK = 0
1
0D
Q 1
CLK = 1
0D
Q
InClkQClkQ ⋅+⋅=
Mux-Based LatchesPositive latch(transparent when CLK= 1)
0
CLK = 0
1D
Q
InClkQClkQ ⋅+⋅=
CLK = 1
0
1D
Q
Mux-Based Latch
CLK
CLK
CLK
D
Q
CLK=1
CLK=0
Mux-Based Latch
CLK
CLK
CLK
CLK
QM
QM
NMOS only Non-overlapping clocks
CLK=1
CLK=0
Master-Slave (Edge-Triggered)Register
1
0D
CLK
QM
Master
0
1
CLK
Q
Slave
QM
Q
D
Two opposite latches trigger on edgeAlso called master-slave latch pair
Master-Slave (Edge-Triggered)Register
1
0D
CLK
QM
Master
0
1
CLK
Q
Slave
QM
Q
D
Two opposite latches trigger on edgeAlso called master-slave latch pair
CLK=0
Master-Slave (Edge-Triggered)Register
1
0D
CLK
QM
Master
0
1
CLK
Q
Slave
QM
Q
D
Two opposite latches trigger on edgeAlso called master-slave latch pair
CLK=1
Master-Slave RegisterMultiplexer-based latch pair
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6
CLK = 0 ⇒⇒⇒⇒ T1, T4 accesi, T2, T3 spenti
CLK = 1 ⇒⇒⇒⇒ T2, T3 accesi, T1, T4 spenti
Master-Slave RegisterMultiplexer-based latch pair
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6
CLK = 0 ⇒⇒⇒⇒ T1, T4 accesi, T2, T3 spenti
CLK = 1 ⇒⇒⇒⇒ T2, T3 accesi, T1, T4 spenti
Master-Slave RegisterMultiplexer-based latch pair
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6
CLK = 0 ⇒⇒⇒⇒ T1, T4 accesi, T2, T3 spenti
CLK = 1 ⇒⇒⇒⇒ T2, T3 accesi, T1, T4 spenti
Master-Slave RegisterMultiplexer-based latch pair
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6
CLK = 0 ⇒⇒⇒⇒ T1, T4 accesi, T2, T3 spenti
CLK = 1 ⇒⇒⇒⇒ T2, T3 accesi, T1, T4 spenti
tcq
Clk-Q Delay
D
Q
CLK
2 0.5
0.5
1.5
2.5
tc 2 q(lh)
0.5 1 1.5 2 2.50time, nsec
Volts tc 2 q(hl)
-
CLK
Master-Slave Register: setupSetup time
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6
il dato D deve avere il tempo di attraversare I1, T1, I3e I2 prima che CLK passi da 0 a 1
⇒⇒⇒⇒ D deve arrivare tsu=tpI1+tpT1+tpI3+tpI2 prima dellatransizione 0 - 1 del clock
Master-Slave Register: setupSetup time
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6
il dato D deve avere il tempo di attraversare I1, T1, I3e I2 prima che CLK passi da 0 a 1
⇒⇒⇒⇒ D deve arrivare tsu=tpI1+tpT1+tpI3+tpI2 prima dellatransizione 0 - 1 del clock
Master-Slave Register: setupSetup time
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6
il dato D deve avere il tempo di attraversare I1, T1, I3e I2 prima che CLK passi da 0 a 1
⇒⇒⇒⇒ D deve arrivare tsu=tpI1+tpT1+tpI3+tpI2 prima dellatransizione 0 - 1 del clock
tsu
Setup Time
D
Q
QM
CLK
I2 2 T2
2 0.5
Volts
0.0
0.2 0.4time (nsec)
(a) T setup 5 0.21 nsec
0.6 0.8 10
0.5
1.0
1.5
2.0
2.5
3.0
DQ
QM
CLK
I2 2 T2
2 0.5
Volts
0.0
0.2 0.4time (nsec)
(b) T setup 5 0.20 nsec
0.6 0.8 10
0.5
1.0
1.5
2.0
2.5
3.0
tsu=0.21 ns tsu=0.20 ns
Cross-Coupled NAND
S
QR
Q
Cross-coupled NANDs set-reset
S
R
Q
Q
S R Q Q
0 0 1 1
0 1 1 0
1 0 0 1
1 1 Q Q
forbidden state
Other Latches/Registers: C2MOS
M1
D Q
M3CLK
M4
M2
CLK
VDD
CL1
X
CL2
Master Stage
M5
M7CLK
CLK M8
M6
VDD
Other Latches/Registers: C2MOS
M1
D Q
M3CLK
M4
M2
CLK
VDD
CL1
X
CL2
Master Stage
M5
M7CLK
CLK M8
M6
VDD
CLK=0
Other Latches/Registers: C2MOS
M1
D Q
M3CLK
M4
M2
CLK
VDD
CL1
X
CL2
Master Stage
M5
M7CLK
CLK M8
M6
VDD
CLK=1
TSPC Register
CLK
CLK
D
VDD
M3
M2
M1
CLK
Y
VDD
Q
Q
M9
M8
M7
CLK
X
VDD
M6
M5
M4
TSPC Register
CLK
CLK
D
VDD
M3
M2
M1
CLK
Y
VDD
Q
Q
M9
M8
M7
CLK
X
VDD
M6
M5
M4
1/2 N-latch
TSPC Register
CLK
CLK
D
VDD
M3
M2
M1
CLK
Y
VDD
Q
Q
M9
M8
M7
CLK
X
VDD
M6
M5
M4
1/2 N-latch 1/2 P-latch
TSPC Register
CLK
CLK
D
VDD
M3
M2
M1
CLK
Y
VDD
Q
Q
M9
M8
M7
CLK
X
VDD
M6
M5
M4
1/2 N-latch 1/2 P-latch
precharge inverter
TSPC Register: funzionamento
CLK
CLK
D
VDD
M3
M2
M1
CLK
Y
VDD
Q
Q
M9
M8
M7
CLK
X
VDD
M6
M5
M4
TSPC Register: funzionamento
CLK
CLK
D
VDD
M3
M2
M1
CLK
Y
VDD
Q
Q
M9
M8
M7
CLK
X
VDD
M6
M5
M4
CLK=0
precarica
mantiene il dato precedente
TSPC Register: funzionamento
CLK
CLK
D
VDD
M3
M2
M1
CLK
Y
VDD
Q
Q
M9
M8
M7
CLK
X
VDD
M6
M5
M4
CLK=1
valutazione
