CellCell--based IC Design, based IC Design, Implementation and VerificationImplementation and Verification ( (cmhuang@cic.org.tw cmhuang@cic.org.tw) ) Jun. 2004 Jun. 2004C. M. Huang / CIC-CBDC / 07.2004 2DayDay--11 Design Flow Overview Verilog at a Glance RTL Simulation Lab: Using Verilog-XL Code Coverage Analysis RTL Synthesis Logic Synthesis Lab: Using VN Cover Lab: Using HDL and Design CompilerC. M. Huang / CIC-CBDC / 07.2004 3DayDay--22 Gate-level Delay Calculation Static Timing Analysis Power Analysis & Optimization DFT & ATPG Lab: Gate-level Simulation Lab: Using Power Compiler Lab: Using DFT Compiler Automatic Physical Design Physical Verification Formal Equivalence Checking Lab: Using Apollo Lab: Using Conformal LECDesign Flow OverviewDesign Flow OverviewC. M. Huang / CIC-CBDC / 07.2004 Overview - 2Algorithm, Architecture, and ChipAlgorithm, Architecture, and ChipWe are here...C. M. Huang / CIC-CBDC / 07.2004 Overview - 3How to Realize an Architecture?How to Realize an Architecture?C. M. Huang / CIC-CBDC / 07.2004 Overview - 4General Design ProcessGeneral Design ProcessDesignSpecify and capture the ideal into some formal representationsImplementationRefine the design through all phasesVerificationVerify the correctness of design and implementationC. M. Huang / CIC-CBDC / 07.2004 Overview - 5General Design ProcessGeneral Design ProcessIdeal IdealDesign DesignVerification VerificationImplementation ImplementationVerification VerificationImplementation ImplementationVerification VerificationImplementation ImplementationVerification Verification Verified Chip Layout Verified Chip LayoutC. M. Huang / CIC-CBDC / 07.2004 Overview - 6Typical Design ConsiderationsTypical Design ConsiderationsFunctionalityAreaTimingPowerTestabilityReliabilityDesignDesignC. M. Huang / CIC-CBDC / 07.2004 Overview - 8Possible Design DomainsPossible Design Domains if A = 0 then Z = 1; else Z = 0;Z AAZBehavioral Domain Structural Domain Physical DomainC. M. Huang / CIC-CBDC / 07.2004 Overview - 9Possible Design LevelsPossible Design LevelsLayoutModulesFloorplanClustersPhysical partitionsTransfer functionsLogicRegister transfersAlgorithmsSystemsTransistorsGates, FFsALUs, MUXs, REGsHardware modulesProcessor, memory, switchBehavioralDomainPhysicalDomainStructuralDomainRevised from: Silicon CompilationRegister Transfer LevelLogic LevelCircuit LevelAlgorithm LevelArchitecture LevelC. M. Huang / CIC-CBDC / 07.2004 Overview - 10Productivity v.s. PredictabilityProductivity v.s. PredictabilityTR TR Gate Gate RTL RTL Behavioral BehavioralProductivity ProductivityPredictability PredictabilityC. M. Huang / CIC-CBDC / 07.2004 Overview - 11Current Practice: HDLCurrent Practice: HDL@@RTLRTLmodule TEST(CLK, A, B, C, E); inputCLK, A, B, C;output E;reg E, D;always @(posedge CLK)E >Relational > < >= < >= > shift right