CIS 501 Computer Architecture What is Computer Architecture ...
CHW 362 : Computer Architecture & Organizationbu.edu.eg/portal/uploads/Computers and...
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CHW 362 : Computer
Architecture & Organization
Instructors:Dr Ahmed ShalabyDr Mona Ali
http://bu.edu.eg/staff/ahmedshalaby14#
http://www.bu.edu.eg/staff/mona.abdelbaset
2
Study: CHW 362 : Computer
Architecture & Organization
Why?
How?
What?
What ? Computer Architecture
• computer architecture defines how tocommand a processor.
• computer architecture is a set of rules andmethods that describe the functionality,organization, and implementation ofcomputer system.
How ? Course Book
How ? Course ContentLec # Subject Week #
Lec1 Chapter 1: From Zero to One Week #1
Lec2 Chapter 2: Combinational Logic Design Week #2
Lec 3 Chapter 3: Sequential Logic Design Week #3
Lec 4 Chapter 3 : continue Week #4
Lec 5 Chapter 4: Hardware Description Language Week #5
Lec 6 Chapter 4 : continue Week #6
Midterm Exam Week #7
Lec 7 Chapter 5: Digital Building Blocks Week #8
Lec 8 Chapter 5 continue Week #9
Lec 9 Chapter 6: Computer Architecture Week #10
Lec 10 Chapter 6 : continue Week #11
Lec 11 Chapter 7: Microarchitecture Week #12
Lec 12 Chapter 7 continue Week #13
Why ? Computer Architecture
Synthesis
Basics
8
Digital System
Implementation Spectrum
9
trade-offflexibility efficiency
ASIC
Reconfigurable Architectures
• µProcessor• µController• DSP
• CPLD• FPGA• Customized Processors• Coarse Grain- Reconfigurable Array
Software
Hardware
Reconfigurable Architectures
• Filed Programmable Devices
Simple
Programmable logic Devices ( PLD )
Complex
Complex Programmable Logic Devices ( CPLD )
Field Programmable Gate Array ( FPGA )
10
Programmable logic Devices
11
Logic Functions
Relatively small FPD that contains one or two levels
of programmable logic—an AND plane and/or an
OR plane.
Complex PLD
12
• Arrangement of multiple SPLD-like blocks on a single chip.
• Programmable PLD Blocks, Programmable Interconnects
FPGA
13
16-bit SR
flip-flop
clock
mux
y
qe
a
b
c
d
16x1 RAM
4-input
LUT
clock enable
set/reset
• Logic Functions implemented in Look Up Table.
• Flip-Flops (Register).
• Multiplexers
FPGA - LUT
14
• LUT contains Memory Cells to implement small logic functions
• Each cell holds ‘0’ or ‘1’ .
• Programmed with outputs of Truth Table
• Inputs select content of one of the cells as output
• Configured by re-programmable SRAM memory cells
FPGA – Design Flow
• Reading Specs and Define the full definition of the problem
• Detailed Specs and architecture of the project.
• Behavioral design – High level Description of Logic Design.
– Schematic.
– State machine.
– Flow chart.
– Block diagram.
• Function Verification ( Pre-Synthesis Simulation ).
• Synthesis - Target FPGA Device.
– Place
– Route
• Timing Verification ( Post-Synthesis Simulation ).
• Device Programing.
15
Synthesis
• Synthesis is an automatic method of converting a higher level of abstraction (RTL) to a lower level of abstraction (gate level Netlists).
• Synthesis produces technology-specific implementation from technology-independent HDL description.
• Not all HDL can be used for synthesis. There are the HDL subset for synthesis and synthesis style description.
• Synthesis is very sensitive to how the HDL is written
o Good design is still the responsibility of the designer.
o Junk in - junk out
16
System Level Synthesis
17
System Level
Model
TaskAnalysis
HW/SWPartitioning
ASIC
ProcessorCore
Memory
FPGA
I/O
HardwareBehavioralDescription
SoftwareBehavioralDescription
SoftwareCompiler
HighLevel
Synthesis
Chapter 1 <18>
Digital Design and Computer Architecture, 2nd Edition
Chapter 5
David Money Harris and Sarah L. Harris
Chapter 1 <19>
Chapter 5 :: Topics
• Introduction
• Arithmetic Circuits
• Number Systems
• Sequential Building Blocks
• Memory Arrays
• Logic Arrays
Chapter 1 <20>
• Digital building blocks:– Gates, multiplexers, decoders, registers,
arithmetic circuits, counters, memory arrays, logic arrays
• Building blocks demonstrate hierarchy, modularity, and regularity:– Hierarchy of simpler components
– Well-defined interfaces and functions
– Regular structure easily extends to different sizes
• Will use these building blocks in Chapter 7 to build microprocessor
Introduction
Chapter 1 <21>
A B
0 0
0 1
1 0
1 1
SCout
S =
Cout
=
Half
Adder
A B
S
Cout +
A B
0 0
0 1
1 0
1 1
SCout
S =
Cout
=
Full
Adder
Cin
0 0
0 1
1 0
1 1
0
0
0
0
1
1
1
1
A B
S
Cout
Cin+
1-Bit Adders
Chapter 1 <22>
A B
0 0
0 1
1 0
1 1
0
1
1
0
SCout
0
0
0
1
S =
Cout
=
Half
Adder
A B
S
Cout +
A B
0 0
0 1
1 0
1 1
0
1
1
0
SCout
0
0
0
1
S =
Cout
=
Full
Adder
Cin
0 0
0 1
1 0
1 1
0
0
0
0
1
1
1
1
1
0
0
1
0
1
1
1
A B
S
Cout
Cin+
1-Bit Adders
Chapter 1 <23>
A B
0 0
0 1
1 0
1 1
0
1
1
0
SCout
0
0
0
1
S = A B
Cout
= AB
Half
Adder
A B
S
Cout +
A B
0 0
0 1
1 0
1 1
0
1
1
0
SCout
0
0
0
1
S = A B Cin
Cout
= AB + ACin
+ BCin
Full
Adder
Cin
0 0
0 1
1 0
1 1
0
0
0
0
1
1
1
1
1
0
0
1
0
1
1
1
A B
S
Cout
Cin+
1-Bit Adders
Chapter 1 <24>
A B
S
Cout
Cin+
N
NN
• Types of carry propagate adders (CPAs):
– Ripple-carry (slow)
– Carry-lookahead (fast)
– Prefix (faster)
• Carry-lookahead and prefix adders faster for large adders
but require more hardware
Symbol
Multibit Adders (CPAs)
Chapter 1 <25>
S31
A30
B30
S30
A1
B1
S1
A0
B0
S0
C30
C29
C1
C0
Cout ++++
A31
B31
Cin
• Chain 1-bit adders together
• Carry ripples through entire chain
• Disadvantage: slow
Ripple-Carry Adder
Chapter 1 <26>
tripple = NtFA
where tFA is the delay of a 1-bit full adder
Ripple-Carry Adder Delay
Chapter 1 <27>
• Compute carry out (Cout) for k-bit blocks using generate and
propagate signals
• Some definitions:
– Column i produces a carry out by either generating a carry out or
propagating a carry in to the carry out
– Generate (Gi) and propagate (Pi) signals for each column:
• Column i will generate a carry out if Ai AND Bi are both 1.
Gi = Ai Bi• Column i will propagate a carry in to the carry out if Ai OR Bi is 1.
Pi = Ai + Bi• The carry out of column i (Ci) is:
Ci = Ai Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1
Carry-Lookahead Adder
Chapter 1 <28>
• Step 1: Compute Gi and Pi for all columns
• Step 2: Compute G and P for k-bit blocks
• Step 3: Cin propagates through each k-bit
propagate/generate block
Carry-Lookahead Addition
Chapter 1 <29>
• Example: 4-bit blocks (G3:0 and P3:0) :
G3:0 = G3 + P3 (G2 + P2 (G1 + P1G0 )
P3:0 = P3P2 P1P0
• Generally,
Gi:j = Gi + Pi (Gi-1 + Pi-1 (Gi-2 + Pi-2Gj )
Pi:j = PiPi-1 Pi-2Pj
Ci = Gi:j + Pi:j Cj-1
Carry-Lookahead Adder
Chapter 1 <30>
B0
++++
P3:0
G3
P3
G2
P2
G1
P1
G0
P3
P2
P1
P0
G3:0
Cin
Cout
A0
S0
C0
B1
A1
S1
C1
B2
A2
S2
C2
B3
A3
S3
Cin
A3:0
B3:0
S3:0
4-bit CLA
BlockC
in
A7:4
B7:4
S7:4
4-bit CLA
Block
C3
C7
A27:24
B27:24
S27:24
4-bit CLA
Block
C23
A31:28
B31:28
S31:28
4-bit CLA
Block
C27
Cout
32-bit CLA with 4-bit Blocks
Chapter 1 <31>
For N-bit CLA with k-bit blocks:
tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA
– tpg : delay to generate all Pi, Gi
– tpg_block : delay to generate all Pi:j, Gi:j
– tAND_OR : delay from Cin to Cout of final AND/OR gate in k-bit CLA
block
An N-bit carry-lookahead adder is generally much faster than a
ripple-carry adder for N > 16
Carry-Lookahead Adder Delay
Chapter 1 <32>
• Computes carry in (Ci-1) for each column, then
computes sum:
Si = (Ai Bi) Ci
• Computes G and P for 1-, 2-, 4-, 8-bit blocks, etc.
until all Gi (carry in) known
• log2N stages
Prefix Adder
Chapter 1 <33>
• Carry in either generated in a column or propagated from a
previous column.
• Column -1 holds Cin, so
G-1 = Cin, P-1 = 0
• Carry in to column i = carry out of column i-1:
Ci-1 = Gi-1:-1
Gi-1:-1: generate signal spanning columns i-1 to -1
• Sum equation:
Si = (Ai Bi) Gi-1:-1
• Goal: Quickly compute G0:-1, G1:-1, G2:-1, G3:-1, G4:-1, G5:-1,
… (called prefixes)
Prefix Adder
Chapter 1 <34>
• Generate and propagate signals for a block spanning bits i:j:
Gi:j = Gi:k + Pi:k Gk-1:j
Pi:j = Pi:kPk-1:j
• In words:
– Generate: block i:j will generate a carry if:
• upper part (i:k) generates a carry or
• upper part propagates a carry generated in lower part
(k-1:j)
– Propagate: block i:j will propagate a carry if both the
upper and lower parts propagate the carry
Prefix Adder
Chapter 1 <35>
0:-1
-1
2:1
1:-12:-1
012
4:3
3
6:5
5:36:3
456
5:-16:-1 3:-14:-1
8:7
7
10:9
9:710:7
8910
12:11
11
14:13
13:1114:11
121314
13:714:7 11:712:7
9:-110:-1 7:-18:-113:-114:-1 11:-112:-1
15
0123456789101112131415
Bi
Ai
Gi:i
Pi:i
Gk-1:j
Pk-1:j
Gi:k
Pi:k
Gi:j
Pi:j
ii:j
Bi
Ai
Gi-1:-1
Si
iLegend
Prefix Adder Schematic
Chapter 1 <36>
tPA = tpg + log2N(tpg_prefix ) + tXOR
– tpg: delay to produce Pi Gi (AND or OR gate)
– tpg_prefix: delay of black prefix cell (AND-OR gate)
Prefix Adder Delay
Chapter 1 <37>
Compare delay of: 32-bit ripple-carry, carry-lookahead, and
prefix adders
• CLA has 4-bit blocks
• 2-input gate delay = 100 ps; full adder delay = 300 ps
Adder Delay Comparisons
Chapter 1 <38>
Compare delay of: 32-bit ripple-carry, carry-lookahead, and
prefix adders
• CLA has 4-bit blocks
• 2-input gate delay = 100 ps; full adder delay = 300 ps
tripple = NtFA = 32(300 ps)
= 9.6 ns
tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA
= [100 + 600 + (7)200 + 4(300)] ps
= 3.3 ns
tPA = tpg + log2N(tpg_prefix ) + tXOR
= [100 + log232(200) + 100] ps
= 1.2 ns
Adder Delay Comparisons
Chapter 1 <39>
Symbol Implementation
+
A B
-
YY
A B
NN
N
N N
N
N
Subtracter
Chapter 1 <40>
Symbol Implementation
A3
B3
A2
B2
A1
B1
A0
B0
Equal=
A B
Equal
44
Comparator: Equality
Chapter 1 <41> Copyright © 2007 Elsevier
5-<41>
A < B
-
BA
[N-1]
N
N N
Comparator: Less Than
Chapter 1 <42> Copyright © 2007 Elsevier
5-<42>
ALU
N N
N
3
A B
Y
F
F2:0 Function
000 A & B
001 A | B
010 A + B
011 not used
100 A & ~B
101 A | ~B
110 A - B
111 SLT
Arithmetic Logic Unit (ALU)
Chapter 1 <43> Copyright © 2007 Elsevier
5-<43>
+
2 01
A B
Cout
Y
3
01
F2
F1:0
[N-1] S
NN
N
N
N NNN
N
2
Ze
ro
Exte
nd
F2:0 Function
000 A & B
001 A | B
010 A + B
011 not used
100 A & ~B
101 A | ~B
110 A - B
111 SLT
ALU Design
Chapter 1 <44>
Compare delay of: 32-bit ripple-carry, carry-lookahead, and
prefix adders
• CLA has 4-bit blocks
• 2-input gate delay = 100 ps; full adder delay = 300 ps
tripple = NtFA = 32(300 ps)
= 9.6 ns
tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA
= [100 + 600 + (7)200 + 4(300)] ps
= 3.3 ns
tPA = tpg + log2N(tpg_prefix ) + tXOR
= [100 + log232(200) + 100] ps
= 1.2 ns
Adder Delay Comparisons
Chapter 1 <45> Copyright © 2007 Elsevier
5-<45>
+
2 01
A B
Cout
Y
3
01
F2
F1:0
[N-1] S
NN
N
N
N NNN
N
2
Ze
ro
Exte
nd
• Configure 32-bit ALU for SLT
operation: A = 25 and B = 32
Set Less Than (SLT) Example
Chapter 1 <46> Copyright © 2007 Elsevier
5-<46>
+
2 01
A B
Cout
Y
3
01
F2
F1:0
[N-1] S
NN
N
N
N NNN
N
2
Ze
ro
Exte
nd
• Configure 32-bit ALU for SLT
operation: A = 25 and B = 32
– A < B, so Y should be 32-bit
representation of 1 (0x00000001)
– F2:0 = 111
– F2 = 1 (adder acts as
subtracter), so 25 - 32 = -7
– -7 has 1 in the most
significant bit (S31 = 1)
– F1:0 = 11 multiplexer selects
Y = S31 (zero extended) =
0x00000001.
Set Less Than (SLT) Example
Chapter 1 <47> Copyright © 2007 Elsevier
5-<47>
• Logical shifter: shifts value to left or right and fills empty spaces with 0’s
– Ex: 11001 >> 2 =
– Ex: 11001 << 2 =
• Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit (msb).
– Ex: 11001 >>> 2 =
– Ex: 11001 <<< 2 =
• Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end
– Ex: 11001 ROR 2 =
– Ex: 11001 ROL 2 =
Shifters
Chapter 1 <48>
• Logical shifter:
– Ex: 11001 >> 2 = 00110
– Ex: 11001 << 2 = 00100
• Arithmetic shifter:
– Ex: 11001 >>> 2 = 11110
– Ex: 11001 <<< 2 = 00100
• Rotator:
– Ex: 11001 ROR 2 = 01110
– Ex: 11001 ROL 2 = 00111
Shifters
Chapter 1 <49>
A3:0
Y3:0
shamt1:0
>>
2
4 4
A3
A2
A1
A0
Y3
Y2
Y1
Y0
shamt1:0
00
01
10
11
S1:0
S1:0
S1:0
S1:0
00
01
10
11
00
01
10
11
00
01
10
11
2
Shifter Design
Chapter 1 <50>
• A << N = A × 2N
– Example: 00001 << 2 = 00100 (1 × 22 = 4)
– Example: 11101 << 2 = 10100 (-3 × 22 = -12)
• A >>> N = A ÷ 2N
– Example: 01000 >>> 2 = 00010 (8 ÷ 22 = 2)
– Example: 10000 >>> 2 = 11100 (-16 ÷ 22 = -4)
Shifters as Multipliers, Dividers
Chapter 1 <51>
• Partial products formed by multiplying a single digit of the multiplier with multiplicand
• Shifted partial products summed to form result
Decimal Binary
23042x
01010111
5 x 7 = 35
460920+
9660
01010101
01010000
x
+
0100011
230 x 42 = 9660
multiplier
multiplicand
partial
products
result
Multipliers
Chapter 1 <52>
4 x 4 Multiplier
x B3
B2
B1
B0
A3B
0 A
2B
0 A
1B
0 A
0B
0
A3
A2
A1
A0
A3B
1 A
2B
1 A
1B
1 A
0B
1
A3B
2 A
2B
2 A
1B
2 A
0B
2
A3B
3 A
2B
3 A
1B
3 A
0B
3+
P7
P6
P5
P4
P3
P2
P1
P0
0
P2
0
0
0
P1
P0
P5
P4
P3
P7
P6
A3
A2
A1
A0
B0
B1
B2
B3
x
A B
P
44
8
Chapter 1 <53>
4 x 4 Divider
1
A3
000
Q3
1
Q2
B0
B1
B2
B3
R0
R1
R2
R3
A2
1
Q1
A1
1
Q0
A0
+
R B
D
R'
N
Cin
Cout
1 0
R B
DR'N
Cout
Cin
Legend
A/B = Q + R/B
Algorithm:
R’ = 0
for i = N-1 to 0
R = {R’ << 1. Ai}
D = R - B
if D < 0, Qi=0, R’=R
else Qi=1, R’=D
R’=R
Chapter 1 <54>
• Numbers we can represent using binary
representations
– Positive numbers
• Unsigned binary
– Negative numbers
• Two’s complement
• Sign/magnitude numbers
• What about fractions?
Number Systems
Chapter 1 <55>
• Two common notations:
– Fixed-point: binary point fixed
– Floating-point: binary point floats to the right of the
most significant 1
Numbers with Fractions
Chapter 1 <56>
01101100
0110.1100
22 + 21 + 2-1 + 2-2 = 6.75
• 6.75 using 4 integer bits and 4 fraction bits:
• Binary point is implied
• The number of integer and fraction bits must be
agreed upon beforehand
Fixed-Point Numbers
Chapter 1 <57>
• Represent 7.510 using 4 integer bits and 4
fraction bits.
Fixed-Point Number Example
Chapter 1 <58>
• Represent 7.510 using 4 integer bits and 4
fraction bits.
01111000
Fixed-Point Number Example
Chapter 1 <59>
• Representations:
– Sign/magnitude
– Two’s complement
• Example: Represent -7.510 using 4 integer and 4 fraction
bits
– Sign/magnitude:
– Two’s complement:
Signed Fixed-Point Numbers
Chapter 1 <60>
• Representations:
– Sign/magnitude
– Two’s complement
• Example: Represent -7.510 using 4 integer and 4 fraction
bits
– Sign/magnitude:
11111000
– Two’s complement:
1. +7.5: 01111000
2. Invert bits: 10000111
3. Add 1 to lsb: + 1
10001000
Signed Fixed-Point Numbers
Chapter 1 <61>
• Binary point floats to the right of the most significant 1
• Similar to decimal scientific notation
• For example, write 27310 in scientific notation:
273 = 2.73 × 102
• In general, a number is written in scientific notation as:
± M × BE
– M = mantissa
– B = base
– E = exponent
– In the example, M = 2.73, B = 10, and E = 2
Floating-Point Numbers
Chapter 1 <62>
Sign Exponent Mantissa
1 bit 8 bits 23 bits
• Example: represent the value 22810 using a 32-bit floating
point representation
We show three versions –final version is called the IEEE 754
floating-point standard
Floating-Point Numbers
Chapter 1 <63>
0 00000111 11 1001 0000 0000 0000 0000
Sign Exponent Mantissa
1 bit 8 bits 23 bits
1. Convert decimal to binary (don’t reverse steps 1 & 2!):
22810 = 111001002
2. Write the number in “binary scientific notation”:
111001002 = 1.110012 × 27
3. Fill in each field of the 32-bit floating point number:
– The sign bit is positive (0)
– The 8 exponent bits represent the value 7
– The remaining 23 bits are the mantissa
Floating-Point Representation 1
Chapter 1 <64>
0 00000111 110 0100 0000 0000 0000 0000
Sign Exponent Fraction
1 bit 8 bits 23 bits
• First bit of the mantissa is always 1:
– 22810 = 111001002 = 1.11001 × 27
• So, no need to store it: implicit leading 1
• Store just fraction bits in 23-bit field
Floating-Point Representation 2
Chapter 1 <65>
0 10000110
Sign Biased
ExponentFraction
1 bit 8 bits 23 bits
110 0100 0000 0000 0000 0000
• Biased exponent: bias = 127 (011111112)
– Biased exponent = bias + exponent
– Exponent of 7 is stored as:
127 + 7 = 134 = 0x100001102
• The IEEE 754 32-bit floating-point representation of 22810
in hexadecimal: 0x43640000
Floating-Point Representation 3
Chapter 1 <66>
Write -58.2510 in floating point (IEEE 754)
Floating-Point Example
Chapter 1 <67>
1 100 0010 0 110 1001 0000 0000 0000 0000
Sign Exponent Fraction
1 bit 8 bits 23 bits
Write -58.2510 in floating point (IEEE 754)
1. Convert decimal to binary:
58.2510 = 111010.012
2. Write in binary scientific notation:
1.1101001 × 25
3. Fill in fields:Sign bit: 1 (negative)
8 exponent bits: (127 + 5) = 132 = 100001002
23 fraction bits: 110 1001 0000 0000 0000 0000
in hexadecimal: 0xC2690000
Floating-Point Example
Chapter 1 <68>
Number Sign Exponent Fraction
0 X 00000000 00000000000000000000000
∞ 0 11111111 00000000000000000000000
- ∞ 1 11111111 00000000000000000000000
NaN X 11111111 non-zero
Floating-Point: Special Cases
Chapter 1 <69>
• Single-Precision:
– 32-bit
– 1 sign bit, 8 exponent bits, 23 fraction bits
– bias = 127
• Double-Precision:
– 64-bit
– 1 sign bit, 11 exponent bits, 52 fraction bits
– bias = 1023
Floating-Point Precision
Chapter 1 <70>
• Overflow: number too large to be represented
• Underflow: number too small to be represented
• Rounding modes:
– Down
– Up
– Toward zero
– To nearest
• Example: round 1.100101 (1.578125) to only 3 fraction bits
– Down: 1.100
– Up: 1.101
– Toward zero: 1.100
– To nearest: 1.101 (1.625 is closer to 1.578125 than 1.5 is)
Floating-Point: Rounding
Chapter 1 <71>
1. Extract exponent and fraction bits
2. Prepend leading 1 to form mantissa
3. Compare exponents
4. Shift smaller mantissa if necessary
5. Add mantissas
6. Normalize mantissa and adjust exponent if necessary
7. Round result
8. Assemble exponent and fraction back into floating-point
format
Floating-Point Addition
Chapter 1 <72>
Add the following floating-point numbers:
0x3FC00000
0x40500000
Floating-Point Addition Example
Chapter 1 <73>
0 01111111 100 0000 0000 0000 0000 0000
Sign Exponent Fraction
1 bit 8 bits 23 bits
0 10000000 101 0000 0000 0000 0000 0000
1 bit 8 bits 23 bits
Sign Exponent Fraction
1. Extract exponent and fraction bits
For first number (N1): S = 0, E = 127, F = .1
For second number (N2): S = 0, E = 128, F = .101
2. Prepend leading 1 to form mantissa
N1: 1.1
N2: 1.101
Floating-Point Addition Example
Chapter 1 <74>
3. Compare exponents
127 – 128 = -1, so shift N1 right by 1 bit
4. Shift smaller mantissa if necessary
shift N1’s mantissa: 1.1 >> 1 = 0.11 (× 21)
5. Add mantissas
0.11 × 21
+ 1.101 × 21
10.011 × 21
Floating-Point Addition Example
Chapter 1 <75>
0 10000001 001 1000 0000 0000 0000 0000
Sign Exponent Fraction
1 bit 8 bits 23 bits
6. Normalize mantissa and adjust exponent if necessary
10.011 × 21 = 1.0011 × 22
7. Round result
No need (fits in 23 bits)
8. Assemble exponent and fraction back into floating-point
format
S = 0, E = 2 + 127 = 129 = 100000012, F = 001100..
in hexadecimal: 0x40980000
Floating Point Addition Example
Chapter 1 <76>
Q
CLK
Reset
N
+N
1
CLK
Reset
N
N
QN
r
Symbol Implementation
• Increments on each clock edge
• Used to cycle through numbers. For example,
– 000, 001, 010, 011, 100, 101, 110, 111, 000, 001…
• Example uses:
– Digital clock displays
– Program counter: keeps track of current instruction executing
Counters
Chapter 1 <77>
NQ
Sin
Sout
CLK
Sin
Sout
Q0
Q1
QN-1
Q2
Implementation:
• Shift a new bit in on each clock edge
• Shift a bit out on each clock edge
• Serial-to-parallel converter: converts serial input (Sin) to
parallel output (Q0:N-1)
Shift Registers
Symbol:
Chapter 1 <78>
Clk0
1
0
1
0
1
0
1
D0
D1
DN-1
D2
Q0
Q1
QN-1
Q2
Sin
Sout
Load
• When Load = 1, acts as a normal N-bit register
• When Load = 0, acts as a shift register
• Now can act as a serial-to-parallel converter (Sin to Q0:N-1) or
a parallel-to-serial converter (D0:N-1 to Sout)
Shift Register with Parallel Load
Chapter 1 <79>
Address
Data
ArrayN
M
• Efficiently store large amounts of data
• 3 common types:
– Dynamic random access memory (DRAM)
– Static random access memory (SRAM)
– Read only memory (ROM)
• M-bit data value read/ written at each unique N-bit address
Memory Arrays
Chapter 1 <80>
Address
Data
ArrayN
M
Address Data
11
10
01
00
depth
0 1 0
1 0 0
1 1 0
0 1 1
width
Address
Data
Array2
3
• 2-dimensional array of bit cells
• Each bit cell stores one bit
• N address bits and M data bits:
– 2N rows and M columns
– Depth: number of rows (number of words)
– Width: number of columns (size of word)
– Array size: depth × width = 2N × M
Memory Arrays
Chapter 1 <81>
Address Data
11
10
01
00
depth
0 1 0
1 0 0
1 1 0
0 1 1
width
Address
Data
Array2
3
• 22 × 3-bit array
• Number of words: 4
• Word size: 3-bits
• For example, the 3-bit word stored at address 10 is 100
Memory Array Example
Chapter 1 <82>
Address
Data
1024-word x
32-bit
Array
10
32
Memory Arrays
Chapter 1 <83>
stored
bit
wordline
bitline
stored
bit = 0
wordline = 1
stored
bit = 1
stored
bit = 0
stored
bit = 1
bitline =
(a) (b)
wordline = 1
wordline = 0
wordline = 0
bitline =
bitline =
bitline =
Memory Array Bit Cells
Chapter 1 <84>
stored
bit
wordline
bitline
stored
bit = 0
wordline = 1
stored
bit = 1
stored
bit = 0
stored
bit = 1
bitline =
(a) (b)
wordline = 1
wordline = 0
wordline = 0
bitline =
bitline =
bitline = 0
1
Z
Z
Memory Array Bit Cells
Chapter 1 <85>
wordline311
10
2:4
Decoder
Address
01
00
stored
bit = 0wordline
2
wordline1
wordline0
stored
bit = 1
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
bitline2
bitline1
bitline0
Data2
Data1
Data0
2
• Wordline: – like an enable
– single row in memory array read/written
– corresponds to unique address
– only one wordline HIGH at once
Memory Array
Chapter 1 <86>
• Random access memory (RAM): volatile
• Read only memory (ROM): nonvolatile
Types of Memory
Chapter 1 <87>
• Volatile: loses its data when power off
• Read and written quickly
• Main memory in your computer is RAM
(DRAM)
Historically called random access memory because any data
word accessed as easily as any other (in contrast to sequential
access memories such as a tape recorder)
RAM: Random Access Memory
Chapter 1 <88>
• Nonvolatile: retains data when power off
• Read quickly, but writing is impossible or
slow
• Flash memory in cameras, thumb drives, and
digital cameras are all ROMs
Historically called read only memory because ROMs
were written at manufacturing time or by burning fuses.
Once ROM was configured, it could not be written again.
This is no longer the case for Flash memory and other
types of ROMs.
ROM: Read Only Memory
Chapter 1 <89>
• DRAM (Dynamic random access memory)
• SRAM (Static random access memory)
• Differ in how they store data:
– DRAM uses a capacitor
– SRAM uses cross-coupled inverters
Types of RAM
Chapter 1 <90>
• Invented DRAM in
1966 at IBM
• Others were skeptical
that the idea would
work
• By the mid-1970’s
DRAM in virtually all
computers
Robert Dennard, 1932 -
Chapter 1 <91>
stored
bit
wordline
bitline
wordline
bitline
stored
bit
• Data bits stored on capacitor
• Dynamic because the value needs to be refreshed
(rewritten) periodically and after read:
– Charge leakage from the capacitor degrades the value
– Reading destroys the stored value
DRAM
Chapter 1 <92>
wordline
bitline
wordline
bitline
+ +stored
bit = 1
stored
bit = 0
DRAM
Chapter 1 <93>
stored
bit
wordline
bitline
wordline
bitline bitline
SRAM
Chapter 1 <94>
wordline311
10
2:4
Decoder
Address
01
00
stored
bit = 0wordline
2
wordline1
wordline0
stored
bit = 1
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
bitline2
bitline1
bitline0
Data2
Data1
Data0
2
wordline
bitline bitline
wordline
bitline
DRAM bit cell: SRAM bit cell:
Memory Arrays Review
Chapter 1 <95>
11
10
2:4
Decoder
Address
Data0Data1Data2
01
00
2
wordline
bitline
wordline
bitline
bit cell
containing 0
bit cell
containing 1
ROM: Dot Notation
Chapter 1 <96>
• Developed memories and high speed circuits at Toshiba, 1971-1994
• Invented Flash memory as an unauthorized project pursued during nights and weekends in the late 1970’s
• The process of erasing the memory reminded him of the flash of a camera
• Toshiba slow to commercialize the idea; Intel was first to market in 1988
• Flash has grown into a $25 billion per year market
Fujio Masuoka, 1944 -
Chapter 1 <97>
11
10
2:4
Decoder
Address
Data0Data1Data2
01
00
2
Address Data
11
10
01
00
depth
0 1 0
1 0 0
1 1 0
0 1 1
width
ROM Storage
Chapter 1 <98>
11
10
2:4
Decoder
Address
Data0Data1Data2
01
00
2 Data2 = A1 A0
Data1 = A1 + A0
Data0 = A1A0
ROM Logic
Chapter 1 <99>
11
10
2:4
Decoder
A, B
ZYX
01
00
2
Implement the following logic functions using a 22 × 3-bit
ROM:
– X = AB
– Y = A + B
– Z = A B
Example: Logic with ROMs
Chapter 1 <100>
11
10
2:4
Decoder
A, B
ZYX
01
00
2
Implement the following logic functions using a 22 × 3-bit
ROM:
– X = AB
– Y = A + B
– Z = A B
Example: Logic with ROMs
Chapter 1 <101>
wordline311
10
2:4
Decoder
Address
01
00
stored
bit = 0wordline
2
wordline1
wordline0
stored
bit = 1
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
bitline2
bitline1
bitline0
Data2
Data1
Data0
2
Data2 = A1 A0
Data1 = A1 + A0
Data0 = A1A0
Logic with Any Memory Array
Chapter 1 <102>
Implement the following logic functions using a 22 × 3-bit
memory array:
– X = AB
– Y = A + B
– Z = A B
Logic with Memory Arrays
Chapter 1 <103>
wordline311
10
2:4
Decoder
A, B
01
00
stored
bit = 1wordline
2
wordline1
wordline0
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 0
stored
bit = 0
bitline2
bitline1
bitline0
X Y Z
2
Implement the following logic functions using a 22 × 3-bit
memory array:
– X = AB
– Y = A + B
– Z = A B
Logic with Memory Arrays
Chapter 1 <104>
stored
bit = 1
stored
bit = 0
00
01
2:4
Decoder
A
stored
bit = 0
bitline
stored
bit = 0
Y
B
10
11
4-word x 1-bit Array
A B Y
0 0
0 1
1 0
1 1
0
0
0
1
Truth
Table
A1
A0
Called lookup tables (LUTs): look up output at each input
combination (address)
Logic with Memory Arrays
Chapter 1 <105>
A1
A3
WD3
WE3
A2
CLK
Array
RD2
RD1M
M
N
N
N
M
• Port: address/data pair
• 3-ported memory
– 2 read ports (A1/RD1, A2/RD2)
– 1 write port (A3/WD3, WE3 enables writing)
• Register file: small multi-ported memory
Multi-ported Memories
Chapter 1 <106>
// 256 x 3 memory module with one read/write port
module dmem( input logic clk, we,
input logic [7:0] a,
input logic [2:0] wd,
output logic [2:0] rd);
logic [2:0] RAM[255:0];
assign rd = RAM[a];
always @(posedge clk)
if (we)
RAM[a] <= wd;
endmodule
SystemVerilog Memory Arrays
Chapter 1 <107>
• PLAs (Programmable logic arrays)
– AND array followed by OR array
– Combinational logic only
– Fixed internal connections
• FPGAs (Field programmable gate arrays)
– Array of Logic Elements (LEs)
– Combinational and sequential logic
– Programmable internal connections
Logic Arrays
Chapter 1 <108>
X Y
A B C
AND ARRAY
OR ARRAY
ABC
AB
ABC
AND
ARRAY
OR
ARRAY
Inputs
Outputs
Implicants
N
M
P
• X = ABC + ABC
• Y = AB
PLAs
Chapter 1 <109>
AND
ARRAY
OR
ARRAY
Inputs
Outputs
Implicants
N
M
P
X Y
ABC
AB
ABC
A B C
AND ARRAY
OR ARRAY
PLAs: Dot Notation
Chapter 1 <110>
• Composed of:
– LEs (Logic elements): perform logic
– IOEs (Input/output elements): interface with outside
world
– Programmable interconnection: connect LEs and
IOEs
– Some FPGAs include other building blocks such as
multipliers and RAMs
FPGA: Field Programmable Gate Array
Chapter 1 <111>
General FPGA Layout
Chapter 1 <112>
• Composed of:
– LUTs (lookup tables): perform combinational logic
– Flip-flops: perform sequential logic
– Multiplexers: connect LUTs and flip-flops
LE: Logic Element
Chapter 1 <113>
Altera Cyclone IV LE
Chapter 1 <114>
• The Altera Cyclone IV LE has:
– 1 four-input LUT
– 1 registered output
– 1 combinational output
Altera Cyclone IV LE
Chapter 1 <115>
Show how to configure a Cyclone IV LE to perform the
following functions:
– X = ABC + ABC
– Y = AB
LE Configuration Example
Chapter 1 <116>
Show how to configure a Cyclone IV LE to perform the
following functions:
– X = ABC + ABC
– Y = AB
LE Configuration Example
LUT output0 0
0 1
1 0
1 1
0
1
0
0
data 20
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
1
0
X
X
X
X
X
X
X
X
data 1
(A) (B) (C) (X)
data 1
0
AB0 Y
data 4data 3
data 2data 3data 4
LUT
data 1
0
AB
CX
data 2data 3data 4
LUT
LUT output0
1
0
1
0
0
1
0
data 20
0
1
1
X
X
X
X
data 1
(A) (B) (Y)
data 4data 3X
X
X
X
LE 1
LE 2
Chapter 1 <117>
Using a CAD tool (such as Altera’s Quartus II)
• Enter the design using schematic entry or an HDL
• Simulate the design
• Synthesize design and map it onto FPGA
• Download the configuration onto the FPGA
• Test the design
FPGA Design Flow