Christie Marrian, Spansion 10/24/07switching for advanced memory applications," Electron Devices...
Transcript of Christie Marrian, Spansion 10/24/07switching for advanced memory applications," Electron Devices...
Spansion Confidential
Engineering Document
Resistive switching for next generation Flash technology
Christie Marrian, Spansion
10/24/07
2004-06-28 2SPANSION Confidential
Cautionary Statement
This presentation and comments made pursuant thereto may containforward-looking statements that are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995, including statements regarding future deployment of MirrorBit™technology, the company's ability to capitalize on its product and technology leadership and its operational efficiency. Investors are cautioned that the forward-looking statements in this presentation involve risks and uncertainties that could cause actual results to differ materially from the company's current expectations, including the possibility that demand for the company's Flash memory products will be lower than currently expected; that customer acceptance of MirrorBit technology will not continue to increase; that OEMs will increasingly choose NAND-based Flash memory products over NOR- and MirrorBit ORNAND architecture-based Flash memory products for their applications; that there will be a lack of customer acceptance of MirrorBit ORNAND architecture-based Flash memory products; that the company will not achieve its current product and technology introduction or implementation schedules; that the company will not be able to meet customer demand during cyclical industry or economic downturns; that competitors will introduce new memory technologies that render the company's Flash memory products uncompetitive or obsolete. The company urges investors to review in detail the risks and uncertainties in the company's Securities and Exchange Commission filings, including but not limited to the company's Annual Report on Form 10-K for the year ended December 25, 2005.
3
Introduction
• NAND market – Almost 100% data storage. – Memories are mostly for memory cards or memory products.
• NOR market – Mainly for code storage.– Memories are embedded in systems.
• NOR flash memory technology – Only for NOR market? No.
5,572
2,195
7,237
4,503
9,143
6,4677,971
10,598
0
2,000
4,000
6,000
8,000
10,000
12,000
2002 2003 2004 2005
NAND/NOR Sales ($M)Source : WSTS
NOR NAND
NAND
NOR
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Cellular Requirements
Source: Spansion estimates for 2006
64Mb
256Mb
128Mb
512Mb
1Gb+
Camera
64-Channel Sound
Search Engine
Navigation
16Mb
32Mb
Voice
Color LCD
High-end Multimedia
12%
8%
23%
13%
14%
20%10%
5
Floating Gate Cell Basic Operations
• Initial cell VT is low (Data 1).
5V
-9V
Open
Erase4V
GND 1V
Read
GND
9V
5V
Program
Most erased Soft program Least erased Program
0 1 2 3 4 5 6
10
8
6
4
2
0
VG (V)
ID (µA) Read
6
Floating Gate Scaling Barrier
• Floating gate electro-static interaction– Narrow floating-gate spacing– Tall floating gate
Floating gate
Silicon body
Control gate
FG-FG coupling effect
(animation)
Tunnel oxide
7
Nitride Storage
• The favorite NVM technology– Charge does not move around the storage electrode– Less floating gate electro-static interaction results in denser memories.
Nitride
Silicon body
Control gate
Tunnel oxide
8
MirrorBit Basic Operations
• Channel hot electron (CHE) programming
• Transpose source and drain for reading the data
• Band to band (BTBT) hot hole injection erasing
-6V
GND 5.5V
Erase
1.2V
4.5V
Read9V
GND
Program SourceDrain
GND4V
Local VT shift
EC
EV
BTBT hot hole injection
EC
EV
CHE injection
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Cell Operation
W/L B/L CommonRead 5V 0.5V 0VProgram 18V 0/10V 0VErase 0V 18V Float
W/L B/Ln B/L n+1Read 5V 1.5V 0VProgram 10V 5/0V 0VErase -6V 5V Float
W/L B/L CommonRead 5V 0.5V 0VProgram 10V 5/0V 0VErase -18V 0V Float
Cell Size: ~4.5λ2 Cell Size: ~(6λ2)/2 Cell Size: ~9.5λ2
Floating-GateNAND
Floating-GateNOR
MirrorBit™ technology
9/28/06 10
MirrorBit® Quad:Technology of the Future—Today
Eff
ecti
ve C
ell S
ize
(µm
2)
Node (nm)
90 65 45 320.001
0.01
0.1
Source: Spansion Estimates September 2006
Production
2008200720062005
45nm
65nm
90nm
110nm
Scaling to 32nm and Beyond Goal – One Node Per Year
MirrorBit® QuadMirrorBitNAND SLCNAND MLC
10/26/2007 11
Emerging Memory Technologies
Write time per bitRead access time
Scalability
Fast
Fast
Good
FRAM
NOR flash
NAND flash
RRAM,PRAM, MRAM
DRAM
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SourceDrain
Gate
Bottom electrodeMemory element
Top electrode
Memory Cell Structure
Cu
TE
Cu2O
! MIM memory element built on a via! Memory element connected with a select transistor! Fully compatible with standard CMOS process
50 nm
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Background – Trapping Model*
• OFF state mainly by space-charge-limited-conduction (SCLC)and Frenkel-Poole (FP)
• OFF"ON switch at trap-filled-limit voltage (VTFL)
*Chen et. al "Non-volatile resistive switching for advanced memory applications," Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International , vol., no.pp. 746- 749, 5-7 Dec. 2005
Cu2O MIM Memory Cell
OFF state VPGM
VER
Ilimit
-2 0 2 4-20µ
-10µ
0
10µ
20µ
30µ
40µ
50µ
Cur
rent
(A)
Voltage (V)
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Electrode Effect
OFF-state current leakage increases with reactivity between top electrode and Cu2O (Ni / Co<Ti<Ta).
Free energy of formation
-457Ta2O5
-212TiO2
-51.7NiO
-51CoO
∆Go (kcal/mole)Mox
Voltage (V)
1E-14
1E-13
1E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
0.0001
0 0.5 1 1.5 2 2.5 3
|Cur
rent
(A)|
TaTiNiCo
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Switching Characteristics: Ni vs. Ti TE
Cells with Ni top electrode• Erase with both polarity• Higher erase current
Cells with Ti top electrode• Reverse polarity field• Low erase current
V
I
Vg
Cu
TE+
-
Cu2O
Voltage (V)-2 -1 0 1 2 3
|Cur
rent
(A)|
2.E-05
4.E-05
6.E-05
8.E-05
1.E-04
0.E+00
Program
Erase
Erase
Ilimit
TE= NiTE= Ti
10/26/2007 16
ON/OFF Window
! Model predicts high ON/OFF ratio with deep-trap materials
! ON/OFF ratio of 105 – 106 observed
0.0 0.2 0.4 0.6 0.8 1.0100f
1p10p
100p1n
10n100n
1µ10µ
Cur
rent
(A)
Voltage (V)
ON state
OFF state
Current (uA)0.005 0.... 0.05 0.1 0.5 1 5 10
-2
-1
0
1
2
0.005 0.01 0.05 0.1 0.5 1 5 10Current (uA)
Cum
ulat
ive
Prob
abili
ty2%
16%
50%
84%
9
8%
OFF ON
Current read at 0.5V
Tester resolution
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Retention
101 102 103 104 10510-7
10-6
10-5
Cur
rent
(A)
Time (min)
90°C 30 hrs retention
25°C 50 hrs retention! Long retention predicted with deep-trap materials
! Retention related to program current
0 0.2 0.4 0.6 0.8 1 1.2
-2
-1
0
1
2
0 0.2 0.4 0.6 0.8 1 1.2Current(50hr) / Current(0hr)
Cum
ulat
ive
Prob
abili
ty2%
16%
50%
84%
9
8%
M.A. Lampert et al, “Current injection in solids”, Academic Press, 1970.
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Cycling
0 100 200 300 400 500 6000.01
0.050.1
0.51
5
10
Cycle
Rea
d cu
rren
t (uA
)
10:1 operation window
! Program with 100 ns pulses
! 0.5uA – 5uA window for cycling
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Electrical Characteristics Summary
Zero up to 25 hours at V < 0.5VRead disturb
0.18 umCell size
> 600 cycles testedCycling
30 hours at 90°C testedRetention
≤ 100 nsSpeed
1-2 VVErasing
≤ 100 nsSpeed
(2-5 V) / (~ 50 uA)V/IProgramming
ValuesCharacteristics
A. Chen et. Al, IEDM 2005
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BEOL Thin Film Challenges for RCM
• Thin ~100A metal oxide films• Hard to etch (process) metal films
– Interfaces in metal-oxide-metal cell
• Highly planar CMP– Maintain electric field uniformity across cell
• Phase Change RCM– Ternary materials plus dopant– Encapsulation
Erase Mechanism for Copper Oxide Resistive Switching Memory Cells with Nickel Electrode
Advanced Memory GroupSpansion Inc
T-N Fang, S. Kaza, S. Haddad, A. Chen, Y-C Wu, Z. Lan, S. Avanzino, D. Liao, C. Gopalan, S. Choi, S. Mahdavi, M. Buynoski, Y. Lin, C. Marrian, C. Bill, M. VanBuskirk, and M. Taguchi
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Spansion Confidential
Engineering Document
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Spansion Confidential
Engineering Document
Trademark Attribution
Spansion, the Spansion Logo and combinations thereof are trademarks of Spansion LLC. Other product names used in this presentation are for identification purposes only and may be trademarks of their respective companies.