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TM
CA3098
Programmable Schmitt Trigger withMemory, Dual Input Precision LevelDetector
The CA3098 Programmable Schmitt Trigger is a monolithic
silicon integrated circuit designed to control high operating
current loads such as thyristors, lamps, relays, etc. The
CA3098 can be operated with either a single power supply
with maximum operating voltage of 16V, or a dual power
supply with maximum operating voltage of 8V. It can
directly control currents up to 150mA and operates with
microwatt standby power dissipation when the current to be
controlled is less than 30mA. The CA3098 contains the
following major circuit function features (see Block Diagram):
1. Differential amplifiers and summer: the circuit uses two
differential amplifiers, one to compare the input voltage
with the high reference, and the other to compare the
input with the low reference. The resultant output of the
differential amplifiers actuates a summer circuit which
delivers a trigger that initiates a change in state of a flip-
flop.
2. Flip-flop: the flip-flop functions as a bistable memory
element that changes state in response to each triggercommand.
3. Driver and output stages: these stages permit the circuit
to sink maximum peak load currents up to 150mA at
terminal 3.
4. Programmable operating current: the circuit incorporates
access at terminal 2 to permit programming the desired
quiescent operating current and performance parameters.
PinoutCA3098
(PDIP)
TOP VIEW
Features
Programmable Operating Current
Micropower Standby Dissipation
Direct Control of Currents Up to. . . . . . . . . . . . . . . 150mA
Low Input On/Off Current of Less Than 1nA for
Programmable Bias Current of 1A
Built-in Hysteresis . . . . . . . . . . . . . . . . . . . . . 20mV (Max)
Applications
Control of Relays, Heaters, LEDs, Lamps, Photosensitive
Devices, Thyristors, Solenoids, etc.
Signal Reconditioning
Phase and Frequency Modulators On/Off Motor Switching
Schmitt Triggers, Level Detectors
Time Delays
Overvoltage, Overcurrent, Overtemperature Protection
Battery-Operated Equipment
Square and Triangular-Wave Generators
LOW REF.
IBIAS
OUT
V-
1
2
3
4
8
7
6
5
+IN
HIGH REF.
V+
CURRENTCONTROL
Part Number Information
PART
NUMBER
TEMP
RANGE (oC) PACKAGE PKG. NO.
CA3098E -55 to 125 8 Ld PDIP E8.3
January 1999 File Number 896.5
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OBSOLE
TEPROD
UCT
NOREC
OMMEND
EDREPL
ACEMEN
T
Call1-88
8-INTER
SILor3
21-724-7
143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143
|Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001. All Rights Reserved
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Block Diagram
Schematic Diagram
DIFF.
AMP
DIFF.AMP
7
1
8 SUMMER
HIGHREF. (HR)
SIGNALINPUT
LOWREF. (LR)
FLIP-FLOP(MEMORY)
2PROGRAMMABLEBIAS CURRENTINPUT (IBIAS)
DRIVER OUTPUT 3
5
4 V-
SINKOUTPUT
OUTPUTCURRENTCONTROL
SUBSTRATE
6 V+
COMPARATOR
8
7
LOWREF. (LR)
1
4
SIGNALINPUT
5
6
3
2
V-
Q1
HIGHREF. (HR)
Q2
Q6 Q7
Q3
Q4
Q5
Q9
Q8
Q10
Q11
Q20
Q26
Q16
Q14
Q15Q12
Q17 Q18
Q19
Q31
Q30
Q27 Q28
Q22 Q23
Q32Q33
Q29
Q34
Q35Q36 Q38
Q37
Q25
Q24
Q39
Q40
Q41
Q42
Q46
Q45Q44Q43
R350K
R14500
SINK
PROGRAMMABLE
V+
BIAS CURRENTINPUT (IBIAS)
OUTPUTCURRENTCONTROL
OUTPUT
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Absolute Maximum Ratings Thermal Information
Supply Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . .16V
Voltage Between High Reference or Sink Output and V-. . . . . . .16V
Differential Input Voltage Between Terminals 8 and 1 . . . . . . . . . 10V
and Terminals 7 and 8
Load Current (Terminal 3) (Duty Cycle 25%). . . . . . . . . . . . 150mA
Input Current to Voltage Regulator (Terminal 5) . . . . . . . . . . . 25mA
Programmable Bias Current (Terminal 2) . . . . . . . . . . . . . . . . . 1mA
Output Current Control (Terminal 5). . . . . . . . . . . . . . . . . . . . . 15mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Voltage Range
+IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+
HIGH REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V- +2.0V) to V+
LOW REF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) to (V+ -2.0V)
Thermal Resistance (Typical, Note 3) JAPDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125oC/W
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . .175 oC
Maximum Junction Temperature (Plastic Package). . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
CA3098
UNITSMIN TYP MAX
Input Offset Voltage
Low Reference (Figures 2, 5) VIO(LR) VLR = GND, VHR = V+ to (V- +2V),
IBIAS = 100A
-15 -3 6 mV
High Reference (Figures 2, 6) VIO(HR) VHR = GND, VLR = V- to (V+ -2V),
IBIAS = 100A
-10 -1 10 mV
Temperature Coefficient
Low Reference (Figure 7) -55oC to 125oC - 4.5 - V/oC
High Reference (Figure 8) -55oC to 125oC - 8.2 - V/oC
Minimum Hysteresis
Voltage (Figure 9) VIO(HR-
LR)
VREG = 0V (Note 1), V+ = 4V, V- = -4V,
IBIAS = 1A
- 3 20 mV
Temperature Coefficient (Figure 10) -55oC to 125oC - 6.7 - V/oC
Output Saturation Voltage(Figures 11, 12)
VCE(SAT) VI = 5V, VREG = 6V (Note 1), V+ = 12V,IBIAS = 100A
- 0.72 1.2 V
Total Supply Current ITOTALON (Figures 3, 13, 14) VI = 6V, VREG > 6V (Note 1), V+ = 16V,
IBIAS = 100A
500 710 800 A
OFF (Figures 3, 13, 14) VI = 10V, VREG < 10V (Note 1),
V+ = 16V, IBIAS = 100A
400 560 750 A
Input Bias Current (Figures 3, 15) IIBIB(PNP) VI = 16V, VREG < 16V (Note 1),
V+ = 16V, IBIAS = 100A
- 42 100 nA
IB(NPN) VI = 6V, VREG > 6V (Note 1), V+ = 16V,
IBIAS = 100A
- 28 100 nA
Output Leakage Current ICE(OFF) Current from Terminal 3 when Q46 is OFF - - 10 A
Switching Times (Figures 4, 16-27) IBIAS = 100A, V+ = 5V, VREG = 2.5V(Note 1)Delay Time tD - 900 - ns
Fall Time tF - 30 - ns
Rise Time tR - 2000 - ns
Storage Time tS - 6.5 - s
Output Current (Note 2) IO 100 - - mA
NOTES:
1. For definition of VREG see Figure 3.
2. Continuous (DC) output current must be limited to 40mA. For 100mA output current, the duty cycle must be 40%.
3. JA is measured with the component mounted on an evaluation PC board in free air.
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General Description of Circuit Operation
When the signal input voltage of the CA3098 is equal to or
less than the low reference voltage (LR), current flows from
an external power supply through a load connected to
Terminal 3 (sink output). This condition is maintained until
the signal input voltage rises to or exceeds the high
reference voltage (HR), thereby effecting a change in the
state of the flip-flop (memory) such that the output stageinterrupts current flow in the external load. This condition, in
turn, is maintained until such time as the signal again
becomes equal to or less than the low reference voltage.
The CA3098 comparator is unique in that it contains circuit
provisions to permit programmability. This feature provides
flexibility to the designer to optimize quiescent power
consumption, input circuit characteristics, hysteresis, and
additionally permits independent control of the comparator,
namely, pulsing, strobing, keying, squelching, etc.
Programmability is accomplished by means of the bias
current (IBIAS) supplied to Terminal 2.
An auxiliary means of controlling the magnitude of load
current flow at Terminal 3 is provided by sinking current into
Terminal 5. Figure 1 highlights the operation of the CA3098
when connected as a simple hysteresis switch (Schmitt
trigger).
26
5
CA3098
IO
RL
EO
V+ = 12VDC
7
8
1
LOW REF. = 4V
HIGH REF. = 8V
4
INPUTSIGNAL
EIN
120k
RB
SEQUENCE
INPUT SIGNAL
LEVEL
OUTPUT VOLTAGE (V)
(TERMINAL 3)
1 4 EIN > 0 0
2 8 EIN > 4 0
3 EIN > 8 12
2 8 EIN > 4 12
1 4 EIN > 0 0
3
FIGURE 1. BASIC HYSTERESIS SWITCH (SCHMITT
TRIGGER) AND RESULTANT OUTPUT STATES
Metallization Mask Layout
Dimensions in parentheses are in millimeters and are derived
from the basic inch dimensions as indicated. Grid graduations
are in mils (10-3 inch).
The layout represents a chip when it is part of the wafer. When
the wafer is cut into chips, the cleavage angles are 57o instead
of 90o with respect to the face of the chip. Therefore, the
isolated chip is actually 7mils (0.17mm) larger in both
dimensions.
60
50
40
30
20
10
0
61
0 10 20 30 40 50 58
63 (1.600)
66 (1.676)
CA3098
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Test Circuits
FIGURE 2. INPUT OFFSET VOLTAGE TEST CIRCUIT FIGURE 3. TOTAL SUPPLY CURRENT, AND INPUT BIAS
CURRENT TEST CIRCUIT
FIGURE 4. SWITCHING TIME TEST CIRCUIT
2
6
5
CA3098 3 VO
8
7
1
4
1.5k
-6V
VLRVHRVI
IBIAS
150
+6V
2
6
5
CA3098 3
8
7
1
4
1.1k
VREGVI
IBIAS
110
V+
mA
mA
IIB
ITOTAL
26
5
CA3098
8
7
1
4
450
VREG
IBIAS
45
V+
VI
3 VOtD
tF tR
tS
VI
VO
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Typical Performance Curves
FIGURE 5. INPUT OFFSET VOLTAGE (LOW REFERENCE)
vs PROGRAMMING BIAS CURRENT
FIGURE 6. INPUT OFFSET VOLTAGE (HIGH REFERENCE)
vs PROGRAMMING BIAS CURRENT
FIGURE 7. INPUT OFFSET VOLTAGE (LOW REFERENCE)
vs AMBIENT TEMPERATURE
FIGURE 8. INPUT OFFFSET VOLTAGE (HIGH
REFERENCE) vs AMBIENT TEMPERATURE
FIGURE 9. MINIMUM HYSTERESIS VOLTAGE vs
PROGRAMMING BIAS CURRENTFIGURE 10. MINIMUM HYSTERESIS VOLTAGE vs AMBIENT
TEMPERATURE
VHR = 6V, VLR = 6V
TA = 25oC, V+ = +12V,
VIO (LR) = VI - VLR
10
PROGRAMMING BIAS CURRENT (A)
10 100 1000
-1
-2
-3
-4
-5
LOWR
EF.INPUTOFFSETVOLTAGE(mV)
VHR = 6V, VLR = 0V
TA = 25oC, V+ = +12V,
VIO (HR) = VI - VHR
10
PROGRAMMING BIAS CURRENT (A)
10 100 1000
1
2
3
4
HIGHREF.INPUTOFF
SETVOLTAGE(mV)
VIO (LR) = VI - VLR
-75-1.5
TEMPERATURE (oC)
-50 -25 0
-2.0
-2.5
-3.0
-3.5
LOW
REF.INPUTOFFSETVOLTAGE(m
V)
25 50 75 100 125
IBIAS = 100A
-750
TEMPERATURE (oC)
-50 -25 0
1
2
3
HIGHREF.INPUTOFFSETVOLTAGE(m
V)
25 50 75 100 125
VIO (HR) = VI - VHR
VHR = 6V, VLR = 6V
TA = 25oC, V+ = +12V,
10
PROGRAMMING BIAS CURRENT (A)
10 100 1000
1
2
3
4
MIN.HYSTERESISVOLTAGE(mV)
-25
TEMPERATURE (oC)
0 100 1251
2
3
4
MIN.HYS
TERESISVOLTAGE(mV)
25 50 75-50-75-100
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FIGURE 11. OUTPUT SATURATION VOLTAGE vs OUTPUT
SINK CURRENT
FIGURE 12. OUTPUT SATURATION VOLTAGE vs AMBIENT
TEMPERATURE
FIGURE 13. TOTAL SUPPLY CURRENT vs PROGRAMMING
BIAS CURRENT
FIGURE 14. TOTAL SUPPLY CURRENT vs AMBIENT
TEMPERATURE
FIGURE 15. INPUT BIAS CURRENT vs PROGRAMMING BIAS
CURRENT
FIGURE 16. DELAY TIME vs SUPPLY VOLTAGE
Typical Performance Curves (Continued)
V+ = 12V
TA = 25oC, IBIAS = 100A
100
OUTPUT SINK CURRENT (mA)
100 1000
0.8
1.0
1.2
1.4
OUTPUTSATURATIONVOLTAGE(V)
0.6
0.4
0.2
V+ = 10V
IBIAS = 100A
-1000.5
TEMPERATURE (oC)
-75 125
0.9
1.0
OUTPUTSATURAT
IONVOLTAGE(V)
0.8
0.7
0.6
-50 -25 0 25 50 75 100
VREG = 6V (NOTE)TA = 25oC, V+ = 12V
10.1
PROGRAMMING BIAS CURRENT (A)
100 1000
10
100
1,000
10,000
TOTALSUPPLYCURRENT(A)
1
10
NOTE: See Figure 3 for definition of VREG
IBIAS = 100A
500
600
700
800
TOTALSUPPLYCURRENT(A)
400
300
200
-75 125-50 -25 0 25 50 75 100TEMPERATURE (oC)
VREG = 6V (NOTE)TA = 25
oC, V+ = 12V
PROGRAMMING BIAS CURRENT (A)
100 10001010.1
10
100
INPUTBIASCURRENT(nA)
1
IIB (p-n-p)
IIB (n-p-n)
NOTE: See Figure 3 for definition of VREG
1000
950
900
850
1050
5 10 15
POSITIVE SUPPLY VOLTAGE (V)
DELAYTIME(ns)
TA = 25oC
IBIAS = 100A
VLR = VHR = VREG = V+/2
800
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FIGURE 17. STORAGE TIME vs SUPPLY VOLTAGE FIGURE 18. OUTPUT FALL TIME vs SUPPLY VOLTAGE
FIGURE 19. OUTPUT RISE TIME vs SUPPLY VOLTAGE FIGURE 20. OUTPUT RISE TIME vs AMBIENT TEMPERATURE
FIGURE 21. OUTPUT FALL TIME vs AMBIENT TEMPERATURE FIGURE 22. STORAGE TIME vs AMBIENT TEMPERATURE
Typical Performance Curves (Continued)
TA = 25oC
IBIAS = 100A
VLR = VHR = VREG = V+/2
5 10 15
POSITIVE SUPPLY VOLTAGE (V)
7000
6500
STORAGETIM
E(ns)
TA = 25oC
IBIAS = 100A
VLR = VHR = VREG = V+/2
5 10 15
POSITIVE SUPPLY VOLTAGE (V)
40
35
30OUTPUTFALL
TIME(ns)
TA = 25oC
IBIAS = 100A
VLR = VHR = VREG = V+/24000
3000
2000OUTPUTRISETIME(ns)
5 10 15POSITIVE SUPPLY VOLTAGE (V)
2500
2400
2300
2200
2600
SUPPLY VOLTAGE = 5V
IBIAS = 100A
VLR = VHR = VREG = 2.5V
2100
2000
1900
1800
1700
OUTPUTRISETIME(ns)
-40 -20 0 20 40 60 80
TEMPERATURE (oC)
-40 -20 0 20 40 60 80
TEMPERATURE (oC)
SUPPLY VOLTAGE = 5V
IBIAS = 100A
VLR = VHR = VREG = 2.5V40
35
30
45
OUTPUTFA
LLTIME(ns)
25
SUPPLY VOLTAGE = 5V
IBIAS = 100A
VLR = VHR = VREG = 2.5V
-40 -20 0 20 40 60 80
TEMPERATURE (oC)
100
9000
8000
7000
6000
5000
4000
STORAGE
TIME(ns)
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FIGURE 23. DELAY TIME vs AMBIENT TEMPERATURE FIGURE 24. DELAY TIME vs PROGRAMMING BIAS CURRENT
FIGURE 25. STORAGE TIME vs PROGRAMMING BIAS
CURRENT
FIGURE 26. OUTPUT FALL TIME vs PROGRAMMING BIAS
CURRENT
FIGURE 27. OUTPUT RISE TIME vs PROGRAMMING BIAS CURRENT
Typical Performance Curves (Continued)
1000
800
700
600
900
-40 -20 0 20 40 60 80
TEMPERATURE (oC)
DELAYTIME(ns)
SUPPLY VOLTAGE = 5V
IBIAS = 100A
VLR = VHR = VREG = 2.5V
100
1100
1000
900
800
700
600
500
0 500 1000
DELAYTIM
E(ns)
PROGRAMMING BIAS CURRENT (A)
400
TA = 25oC, VLR = VHR = VREG = 2.5V
SUPPLY VOLTAGE = 5V1100
10000
9000
8000
7000
6000
5000
4000
0 500 1000
STORAGETIME(ns)
PROGRAMMING BIAS CURRENT (A)
SUPPLY VOLTAGE = 5V
TA = 25oC
VLR = VHR = VREG = 2.5V
11000
12000
3000
40
30
20
10
50
0 500 10000
OUTPUTFALLTIME(ns)
PROGRAMMING BIAS CURRENT (A)
SUPPLY VOLTAGE = 5VTA = 25
oC
VLR = VHR = VREG = 2.5V
60
2500
2000
1500
1000
3000
0 500 1000
OUTPTUT
RISETIME(ns)
PROGRAMMING BIAS CURRENT (A)
SUPPLY VOLTAGE = 5V
TA = 25oC, VLR = VHR = VREG = 2.5V
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FIGURE 32. OFF/ON CONTROL OF TRIAC WITH
PROGRAMMABLE HYSTERESIS
FIGURE 33. ONE SHOT MULTIVIBRATOR
Typical Applications (Continued)
2
6
5
CA3098 3
8
7
1
4
1k
V-
R4
MT2
MT1
G
LOAD
100k
TRIACR1100k
R2100k
R3100k
SENSOR
120VAC60Hz
(e.g., 100k)
2
6
5
CA3098
8
1
7
4
1k
+6V
3
60k
C1
1k
-6V
1M
LAMP
1.1M
TRIGGERINPUT
2.5V
0V
DESIRED tON
(ms)
VALUE OF C1
(F)
15 0.01
150 0.1
300 0.2
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All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Sales Office HeadquartersNORTH AMERICAIntersil Corporation7585 Irvine Center DriveSuite 100Irvine, CA 92618TEL: (949) 341-7000FAX: (949) 341-7123
Intersil Corporation2401 Palm Bay Rd.Palm Bay, FL 32905TEL: (321) 724-7000FAX: (321) 724-7946
EUROPEIntersil Europe SarlAve. William Graisse, 31006 LausanneSwitzerlandTEL: +41 21 6140560FAX: +41 21 6140579
ASIAIntersil CorporationUnit 1804 18/F Guangdong Water Building83 Austin RoadTST, Kowloon Hong KongTEL: +852 2723 6339FAX: +852 2730 1433
CA3098
Dual-In-Line Plastic Packages (PDIP)
CL
E
eA
C
eB
eC
-B-
E1INDEX
1 2 3 N/2
N
AREA
SEATING
BASEPLANE
PLANE
-C-
D1
B1
B
e
D
D1
AA2
L
A1
-A-
0.010 (0.25) C AM B S
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the MO Series Symbol List in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or
protrusions. Mold flash or protrusions shall not exceed 0.010
inch (0.25mm).
6. E and are measured with the leads constrained to be
perpendicular to datum .
7. eB and eC are measured at the lead tips with the leads
unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
eA-C-
E8.3 (JEDEC MS-001-BA ISSUE D)8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.355 0.400 9.01 10.16 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC 6
eB - 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N 8 8 9
Rev. 0 12/93