Chess Panel Project

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    Team Members ::

    Mahmoud Fathi El-tabey Nahla Hesham El-Askary

    Mohamed Saied El-sayed Ghada Sa'd Ragab

    Mohamed Hassan Akl Hagar Adel Mohamed

    Basma Salah El-din Abdl-munim Mariem Ali Ismail

    Basma Ali Mohamed

    Presented to

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    Chess panel

     Project Overview ::Chess Game is one of the most intelligent games over the world , wedecide to develop this game using Altera DE0 kit and VHDL

    programming language ..

    Basic operation ; depending on the motion in two axes X and Y , using

    2D array with 2 stepper motors ,, and by detecting piece before moving

    it using a magnetic field between chess piece and a permanent magnet

    ,, and Displaying operation on 7-segment display with inputs of Places

    of chess piece wanted to move and the place wanted to move to ..there is a LED of error detection upon the fault movement of chess

    piece ..

    Our project consists of two main parts (( Mechanical and Electrical

    Parts ))

    Due to the Electrical Part as a software and hardware ::

    We Use VHDL applicable on Cyclon III FPGA Altera ..

    it consists of main blocks :-

    1- Input & Display .

    2- FSM .

    3- Motors ( Stepper & Servo ) .

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    Input & Display(1)

    Input Block

    -Usage :

    This block is used to move the chess piece from a specific place to the

    destination the player want .

    -Component :Its

    The input of chess panel consists of three push buttons ,, up , down &. which represent thethey are active low ):note(itset taken from the k

    input block ,, its component are :- 1- Two DemuX.

    2- Counter mod 5 .

     3- Four counter mod 8 .

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    1- DeMuX :-The First DeMux use up switch as input ,, two selector from counter 5

    mod. & four output which control the horizontal motion ( X-axis ) .

    The second DeMux use down switch as input ,, two selector from

    counter 5 mod. & four output which control the vertical motion ( Y-axis )

    .

    -Its code is :-

    library IEEE ;

    use IEEE.std_logic_1164.all ;

    ENTITY DeMux4 IS

    PORT ( st_m :IN std_logic_vector (2 downto 0 ) ;

    d_m : IN std_logic ;

    ss1, ss2 ,ss3, ss4: OUT std_logic );

    END DeMux4 ;

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    ARCHITECTURE selecter OF DeMux4 IS

    signal s1,s2,s3,s4 : std_logic :='0' ;

    begin

    process(st_m, d_m)

    begin

    if (st_m = "000") then s1

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    -Its code is :-

    library IEEE ;

    use IEEE.std_logic_1164.ALL ;

    Entity cnt_st5 is

    port ( set1 : IN std_logic ;s_m : OUT std_logic_vector (2 downto 0 ) ) ;

    END cnt_st5 ;

    Architecture behaviour of cnt_st5 is

    BEGIN

    process (set1 )

    Variable cnt : std_logic_vector (2 downto 0 ) := "000";

    BEGIN

    if set1 ='0' then

    case cnt is

    -- present Next

    When "000" => cnt := "001" ;

    When "001" => cnt := "010" ;

    When "010" => cnt := "011" ;

    When "011" => cnt := "100" ;

    when "100" => cnt := "000" ;

    When others => cnt := "000" ;End case ;

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    END if ;

    s_m

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    Variable count : std_logic_VECTOR ( 2 downto 0 ) :="000" ;

    BEGIN

    if (clk1='1' AND clk1'event) then

    if up ='0' then

    case count is

    -- present Next

    When "000" => count := "001" ;

    When "001" => count := "010" ;

    When "010" => count := "011" ;

    When "011" => count := "100" ;

    When "100" => count := "101" ;

    When "101" => count := "110" ;

    When "110" => count := "111" ;When "111" => count := "000" ;

    When others => count := "000" ;

    End case ;

    elsif down ='0' then

    case count is

    -- present Next

    When "000" => count := "111" ;

    When "001" => count := "000" ;

    When "010" => count := "001" ;

    When "011" => count := "010" ;

    When "100" => count := "011" ;

    When "101" => count := "100" ;

    When "110" => count := "101" ;

    When "111" => count := "110" ;

    When others => count := "000" ;

    END Case ;

    END if ;

    END if ;

    q

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    -Technique :The•

    The technique which happen when the player want to play is :-

    - initially the counter 5 mod is at state 000 , so the first counter 8 mod

    will be operated , its input are ( sso1 and sso5 ) depend on up or down .

    - when the player finish putting the input of place on the X-axis ,, he

    must press the set switch so it will count and it will be at state 001 .

    - so the second counter 8 mod will operate ,, its input are ( sso2 and

    sso6) depend on up or down .

    - after inputting the second value and pressing set switch so we have

    entered the place of chess piece which the player want to move .

    - by repeating the previous steps we can obtain the destination the

    player want , so after entering the place and destination the first turn

    will be finished and the another player will do the same previous steps .

     

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     Seven-Segment Display

    Role description:

    -  The two 7-segments display are used to show each play of the two

    players.

    -  They receive the place where the player want to move its piece, then

    decode the binary numbers inputs into letters and decimal numbers,

    and display the new place.

    -  The horizontal squares are numbered from 1 to 8

    -  The eight vertical squares are from A to H.

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    Horizontal inputs decoding :

    - HINT : output is active low

    Vertical inputs decoding :

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    - HINT : output is active low

    Vertical inputs Seven segmentsdecoding code:

    LIBRARY IEEE;

    USE IEEE.STD_LOGIC_1164.All;

    entityseven_segment_horz is

    port( no_input : in std_logic_vector(0 to 2);

    a,b,c,d,e,f,g : out std_logic ) ;

    endseven_segment_horz;

    architectureno_decoder of seven_segment_horz is

    begin

    process(no_input( 

    variablesegs : std_logic_vector (0 TO 6);

    begin

    caseno_input is

    when "000" =>segs := "1001111";

    when "001" =>segs := "0010010";

    when "010" =>segs := "0000110";when "011" =>segs := "1001100";

    when "100" =>segs := "0100100";

    when "101" =>segs := "0100000";

    when "110" =>segs := "0001111";

    when "111" =>segs := "0000000";

    when others =>segs := "1111111";

    end case;

    a

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    Horizontal inputs Seven segments

    decoding code: 

    LIBRARY IEEE;

    USE IEEE.STD_LOGIC_1164.ALL;

    Entity seven_segment_horz is

    port(no_input : in std_logic_vector(0 to 2);

    a,b,c,d,e,f,g : out std_logic);

    end seven_segment_horz;

    architecture no_decoder of seven_segment_horz is

    begin

    process(no_input)

    variable segs : std_logic_vector (0 TO 6);begin

    case no_input is

    when "000" =>segs := "1001111";

    when "001" =>segs := "0010010";

    when "010" =>segs := "0000110";

    when "011" =>segs := "1001100";

    when "100" =>segs := "0100100";

    when "101" =>segs := "0100000";

    when "110" =>segs := "0001111";

    when "111" =>segs := "0000000";

    when others =>segs := "1111111";

    end case;

    a

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    - So the code of the input with the display after connection between

    them is :- 

    library IEEE ;

    use IEEE.std_logic_1164.all ;

    entity top_level1 is

    port ( clkt : std_logic ;

    upt,downt,sett : IN std_logic ;

    a1,b1,c1,d1,e1,f1,g1 ,a2,b2,c2,d2,e2,f2,g2 ,

    a3,b3,c3,d3,e3,f3,g3 ,a4,b4,c4,d4,e4,f4,g4 :OUT

    std_logic );

    end top_level1 ;

    ARCHITECTURE ckt of top_level1 is

    Signal s_mo : std_logic_VECTOR (2 downto 0 ) ;

    Signal sso1,sso2,sso3,sso4 , sso5, sso6 , sso7 , sso8 :

    std_logic ;

    Signal Qy1,Qx1,Qy2,Qx2 : std_logic_vector (2 downto 0) ;

    -- signal clk_t : std_logic ;

    component DeMux4 IS

    PORT ( st_m :IN std_logic_vector (2 downto 0 ) ;

    d_m :IN std_logic ;

    ss1, ss2 ,ss3, ss4: OUT std_logic );

    END component ;

    component mod_8 is

    port ( clock : IN std_logic ;

    up , down : IN std_logic ;

    q : OUT std_logic_VECTOR (2 downto 0) ) ;

    END component ;

    component cnt_st5 is

    port ( set1 : IN std_logic ;

    s_m : OUT std_logic_vector (2 downto 0 ) ) ;

    END component ;

    component seven_segment_vert is

    port( ch_input : in std_logic_vector(2 downto 0);

    A,B,C,D,E,F,G : out std_logic );

    end component;

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    component seven_segment_horz is

    port( no_input : in std_logic_vector(2 downto 0);

    a,b,c,d,e,f,g : out std_logic );

    end component;

    BEGIN

    selector : cnt_st5 port map (sett ,s_mo);

    dem1 : DeMux4 port map (s_mo ,upt, sso1,sso2,sso3,sso4) ;

    dem2 : DeMux4 port map (s_mo ,downt, sso5,sso6,sso7,sso8)

    ;

    count1 : mod_8 port map ( clkt,sso1,sso5,Qy1);

    count2 : mod_8 port map ( clkt,sso2,sso6,Qx1);

    count3 : mod_8 port map ( clkt,sso3,sso7,Qy2);

    count4 : mod_8 port map ( clkt,sso4,sso8,Qx2);sv_sgv1 : seven_segment_vert port map ( Qy1

    ,a1,b1,c1,d1,e1,f1,g1);

    sv_sgvh1 : seven_segment_horz port map ( Qx1

    ,a2,b2,c2,d2,e2,f2,g2);

    sv_sgv2 : seven_segment_vert port map (

    Qy2,a3,b3,c3,d3,e3,f3,g3);

    sv_sgh2 : seven_segment_horz port map ( Qx2

    ,a4,b4,c4,d4,e4,f4,g4);

    end ckt ;

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    Finite state machine)(2

    - In the ordinary combinational logic , we use the vhdl concurrent code

    , and this leads to operate the whole of the code in the same time ,,but there is a problem we face .

    So we are recommended to use the sequential logic ( code in vhdl)

    which depends on the arrangement of the steps of our program .

    And this refers to the FSM (Finite State Machine) .

    The FSM is a sequential circuit which arrange the steps of any device

    operation required .

    In our (Chess Panel) Project , we use the FSM as a detection and

    Location code of the positions of the chess piece , when the chess piece

    is located in a certain place , it's registered in the Memory of FSM , as

    an old value . Then when the user (player) entered the piece place

    he/she wants changing position , the values of it's place would be

    registered in the New1,New2 … After checking entering the place ,

    set_cnt which function is to count how many times the user push setbutton two times , and the 7-segment is displaying the piece place

    position , the Device would start the movement of the motor ,, which

    is explained in the motor part of the report …. (()) ,,,

    Due to the techniques explained in the abstract of the Game , we have

    6 movements of both motors (horizontal X , Vertical Y) , in order to

    arrange this steps we use (case…when statement in code of FSM)

    which contained current and next states of the motor and the gameposition ,,

    The inputs of FSM are (set_count, Q0,Q1,Q2,Q3, donex,doney,clk)

    The Outputs of FSM are (enx , eny, x_stps, y_stps, dircx,dircy )

    And we use (n_stpx,n_stpy) as signals in order to execute the function

    of subtraction to determine the no. of steps required for motors ..

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    1-initial state :- in this state we initialize the place that we start from asthe motor is at the 000 on x-axis & 000 on y-axis ( the old_X & old_y

    values ) . after the player enter the place of the piece that he/she want

    to move so he/she will have pressed two set counts ,, so to move from

    this state to the next state (Rcvp) set_count must equal 010 .

    2- Rcvp :- in this state new_x & new_y will save the values the player

    have entered .. after saving these values so we could move to the next

    state ( cx1) .

    3- c1x :- in this state the motor move a constant motion in order to

    move from the place which the motor stopped in ,, to go to the place of

    the chess piece which he want to go ,, the motor x move the distance of

    half square (n) in which n=3.2 cm ,, in this state motor y must equal 0 .

    then to move to the next state ( c1y ) the done of motor x must equal 1

    as this means that the motor have finished its motion .

    4- c1y :- in this state the motor move a constant motion in order to

    continue moving from the place which the motor stopped in ,, to go to

    the place of the chess piece which he want to go ,, the motor y move

    the distance of half square (n) in which n=3.2 cm ,, in this state motor x

    must equal 0 . then to move to the next state ( mvx ) the done of motor

    y must equal 1 as this means that the motor have finished its motion .

    5- mvx :- in this state the motor will move the number of steps which

    are the difference between new_x and old _x ,, this operation will be

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    done by the subtractor component ,, the output of this component the

    number of steps and the direction of motion ,, in this state motor y must

    equal 0 … then to move to the next state ( mvy ) the done of motor x

    must equal 1 as this means that the motor have finished its motion .

    6- mvy :- in this state the motor will move the number of steps which

    are the difference between new_y and old _y ,, this operation will be

    done by the subtractor component ,, the output of this component the

    number of steps and the direction of motion ,, in this state motor x must

    equal 0 … then to move to the next state ( c2x ) the done of motor y

    must equal 1 as this means that the motor have finished its motion .

    7- c2x :- ( fixed state) in this state the motor move a constant motion inorder to go to the place the player want ,, the motor x move the

    distance of half square (n) in which n=3.2 cm ,, in this state enable of

    motor y must equal 0 . then to move to the next state ( c2y ) the done

    of motor x must equal 1 as this means that the motor have finished its

    motion . 

    8- c2y :- (fixed state ) in this state the motor move a constant motion in

    order to continue going to the place the player want ,, the motor ymove the distance of half square (n) in which n=3.2 cm ,, in this state

    enable of motor x must equal 0 . then to move to the next state ( Rgst )

    the done of motor y must equal 1 as this means that the motor have

    finished its motion . 

    9- Rgst :- in this state the input block receive the destination or new

    place ( newx => oldx & newy => oldy ) which is depend on the value of

    set_count ,, as when the set_count = 100 then the next state will be(RcvD ) but when the set_count = 010 then the next state will be (RcvP )

    10-RcvD :- in this state ( newx

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    This figure shows the state transition diagram of FSM

     

    • its code is :-library IEEE ;

    use IEEE.std_logic_1164.all;

    USE IEEE.STD_LOGIC_UNSIGNED.ALL;

    use IEEE.numeric_std.all;

    use IEEE.math_real.all;

    entity fsm is

    generic (constant m: integer := 2;

    constant k: integer := 34 );

    port (set_count : IN std_logic_vector(2 downto 0) ;

    Q0,Q1,Q2,Q3: IN std_logic_vector (2 downto 0);

    donex,doney,clk : IN std_logic ;

    enx , eny : out std_logic ;

    x_stps : OUT integer range 0 to 574 ; ---------modification try

    y_stps : OUT integer range 0 to 574 ; ---------modification try

    dircx,dircy:out std_logic ;

    srvv : OUT std_LOGIC ); 

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    end fsm ;

    architecture mealy of fsm is

    component clk_fsm IS

    PORT (clk :IN std_LOGIC;lowspeedclock :OUT std_LOGIC);

    END component;

    component subt IS

    port ( P1,P2 : IN std_logic_vector (2 downto 0);

    -- clk : IN std_LOGIC ;

    Qout : OUT std_logic_vector(2 downto 0) ;

    Dirc : OUT std_LOGIC );

    End component ;

    signal clk_sig : std_LOGIC ;

    signal DirX,DirY : std_logic ;

    signal n_stpx,n_stpy : std_logic_vector(2 downto 0) ; ---- modification try (stable)

    --signal nu_stpx,nu_stpy : unsigned(2 downto 0) ;

    signal old1,old2: std_logic_vector (2 downto 0):="000" ;

    signal NEW1 ,NEW2 : std_logic_vector (2 downto 0);

    signal stp_xx,stp_yy : Integer range 0 to 7 ; --- modified try

    type state_type is

    (INIT , RCVP,RCVD , C1X ,C1Y , MVX ,MVY ,C2X,C2Y , RGST );

    signal current_state : state_type := INIT ;

    signal next_state : state_type ;

    begin

    stp_xx

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    case current_state is

    when INIT =>

    enx

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    end if ;

    when Mvy =>

    dircy

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    New2

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    Stepper Motor Control(3)

    Essentially the movement of pieces of chess that is controlled by a

    motor is very important issue in this project ,, according to chess game

    rules , pieces are directed by the player in different directions , so we

    need a movement in both x-axis and y-axis ,, the characteristics of

    stepper motor is suitable for these conditions so we decided to use it as

    responsable of main movement in the project's pieces ..

    stepper motor is an electromechanical device, it converts electrical

    power into mechanical power. Also it is a brushless, synchronous electric

    motor that can divide a full rotation into an expansive number of steps.

    The motor’s position can be controlled accurately without any feedback

    mechanism, as long as the motor is carefully sized to the application,,

    with the stepper we can get accurately controlled number of steps ,

    rotation and speed..

     How to control the stepper in vhdl?

    The first thoughts was about how to control a stepper in vhdl ,, it can be

    achieved by a simple Mod-8 syncronous counter that counts from 0 to 7

    and a decoder that decodes each count to a determined state of 0s and

    1s that is sent to the coils of the stepper and caused it to rotate with

    determined angle in one direction..

    The sequence of states used in this code is called the fullstep sequence..

    The full-step sequence always has two coils of the stepper motorenergized in any state of the sequence and typically causes 15° of shaft

    rotation per step. If you look at the full-step sequence, you will

    notice that each state transition involves turning off one coil and

    simultaneously turning on another coil. The half-step sequence is

    created by inserting a state with only one coil energized between full

    steps. In this sequence, one coil is de-energized before the other is

    energized..this causes the stepper shaft to rotate half as far as it would

    in the full-step sequence but we will use the fullstep sequence only as it

    satisfies the required rotation in this project ..

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     The code :- (First Component )

    library IEEE  ;  Use IEEE.std_logic_1164.all ;Entity steep ISPORT ( ck :IN std_logic;

    Enable : in std_logic ;qm :OUT std_logic_vector (3 DOWNTO 0);

    direction :in std_logic );

    END steep ;ARCHITECTURE vhdl OF steep ISBEGIN

    PROCESS (ck,Enable)Variable maincount : integer range 0 to 7 ; Beginif (Enable='1') then 

    IF (ck'Event and ck='1 ' )THEN

    CASE direction ISWhen '0' => maincount := maincount + 1; WHEN '1' => maincount := maincount - 1; 

    end case  ;  END IF; 

    CASE maincount ISWhen 0 => qm qm qm qm qm qm qm qm

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    In this code ,, "ck" is the clock input of the counter , " maincount " is

    a signal of type integer that represents the output of the counter and

    the input for the decoder , "qm" represents the out of the counter

    and the states that moves the coil by using "direction" input to the

    counter we can control the stepper to move forward or backward for

    the stepper in y-axis , right or left for the x-axis stepper ,, the

    following diagram shows the codes blocks ,, 

    Block Diagram of first component

    but how to make the motor rotates only number of times that is

    required to move the piece to a determined state ? how to recieve

    the input from the player that determine the place of the pieces and

    their destination and translate it into a desired number of states

    that's only cause the motor to go to the right place each time ?

     Main Code of Stepper control :-

    we shall use the block shown to illustrate how the work of the stepper

    is controlled ,,

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    Block Diagram of stepper control

    after receiving the number of steps that required only in a

    determined movement from the input block of this project , it entersa down counter as an input with a clock , by using a signal " flag " and

    at each active transition of the clock the counter counts down from

    the number of steps to 0 and output a wave that remains high during

    the down counting of the counter and becomes low when the

    counter reaches 0 ,,, this wave then is ANDing with an clock to

    output the clock in the high state of the wave and 0 in case of low

    state ..

     The code :- (second component )

    LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_ARITH.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity pwm is 

    port ( Enab : in std_LOGIC ;clck : in STD_LOGIC ;count : in integer range 0 to 15 ;mainclock : out STD_LOGIC ;----done : out std_LOGIC ) ;END pwm  ;

    architecture ckt of pwm isSigNAL mclk : std_LOGIC  ;SIGNAL  qstate : integer range 0 to 15 ;SIGNAL  Flag : STD_LOGIC := '1' ;---signal cckk : std_LOGIC ;

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    --component trafficclock IS--PORT (clk :IN std_logic ;

    --lowspeedclock :OUT std_logic ) ;---END component ;

    begin ---pp: trafficclock port map (clck,cckk) ;

    process (clck , count,Enab) Begin If (Enab='1') then if (clck'Event and clck='1' and Flag ='1') then qstate

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    ENTITY steper_control IS

    PORT ( clok:IN std_LOGIC; 

    En : in std_LOGIC;

    do : out std_LOGIC;

    dir :in std_LOGIC; 

    counter : in integer range 0 to 15;

    qout :OUT std_logic_vector (3 DOWNTO 0  ( 

    ( ; 

    END steper_control;

    ARCHITECTURE vhdl OF steper_control IS

    component pwm is 

    port ( Enab : in std_LOGIC;

    clck : in STD_LOGIC;

    count : in integer range 0 to 15;mainclock : out STD_LOGIC;

    done : out std_LOGIC;)

    END component;

    component steep IS

    PORT ( ck :IN std_logic; 

    Enable : in std_logic;

    qm :OUT std_logic_vector (3 DOWNTO 0);

    direction :in std_logic ;)

    END component;

    SIGNAL mainclck: std_LOGIC ; 

    BEGIN

    downcounter : pwm port map

    (En,clok,counter,mainclck,do);

    motorsteps : steep port map(mainclck,En,qout,dir);

    END vhdl;

    By Using the components discussed above we can control the stepper motion

    ,, repeating the same concept for another motor we can get a control in x-axis

    and in y-axis.

     

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     Stepper External Circuit :-

    The output current of DE0 board is too small to operate the stepper motor

    ,, and in case of connecting the DE0 board directly to the stepper , there is

    a possibility of damaging the board due to too much high current ,, so thecircuit below is used to raise the output current and protecting the DE0

    board ..

    Schematic of stepper circuit

     

    The operation of the circuit is that when the FPGA signal is high no current

    passes through the optocoupler and to the base of Q1 so Q1 is off and no

    signal is applied to the motor ,, In case of low FPGA signal , current passes

    through the optocoupler to the transistor Q1 so Q1 is on and Q1 collector

    current operates the stepper ,, the insulation of DE0 board from the stepper

    and external circuit is achieved by using the optocoupler and thus we reached

    our goal.

  • 8/20/2019 Chess Panel Project

    31/31

     

    Due to the Mechanical Part of our Project ::