Chapters 1-3, 5b1morris/cpe100/slides/2020_slides... · 2020. 12. 2. · Alyssa 1 Alyssa 1 Ben 2...
Transcript of Chapters 1-3, 5b1morris/cpe100/slides/2020_slides... · 2020. 12. 2. · Alyssa 1 Alyssa 1 Ben 2...
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Professor Brendan Morris, SEB 3216, [email protected]
http://www.ee.unlv.edu/~b1morris/cpe100
CPE100: Digital Logic Design I
Final Review
Chapters 1-3, 5
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Logistics
• Wednesday Dec 9• 15:10-17:10 (3:10-5:10pm) - 2 hour exam
• Will be available between Dec 9-12• 2 Parts – Part 1 online (45 mins), Part 2 handwritten (75 mins)
• Chapters 1-3, 5.1-5.2.3, 5.4• Responsible for all material covered in class
• Exclude 3.5.3-3.5.6, 5.3, 5.5-5.7
• Closed book, closed notes
• No calculators
• Must show work and be legible for credit
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Preparation
• Read the book (2nd Edition)
• Then, read it again
• Do example problems
• Use both Harris and Roth books, class participation quizzes
• Be sure you understand homework solutions
• Exam Advice: Be sure to attempt all problems.
• Partial credit can only be given for something written on the page
• Don’t spend too much time thinking (don’t get stuck)
• Be sure to read questions completely
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Main New Material
• Synchronous timing
• How can you ensure dynamic discipline is respected
• Parallelism
• How can you increase operational speed
• Synchronous building blocks
• Full-adder, counter
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Ch 3.5.2 Synchronous Timing
• Data input must be stabled when sampled at rising clock edge
• Setup time: 𝑡𝑠𝑒𝑡𝑢𝑝 = time before clock edge data must be stable (i.e. not changing)
• Hold time: 𝑡ℎ𝑜𝑙𝑑 = time after clock edge data must be stable
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CLK
tsetup
D
thold
ta
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Timing Constraints6
• Setup Timing
• 𝐷2 cannot change 𝑡𝑠𝑒𝑡𝑢𝑝 before next clock cycle
• 𝑇𝑐 ≥ 𝑡𝑝𝑐𝑞 + 𝑡𝑝𝑑 + 𝑡𝑠𝑒𝑡𝑢𝑝
• Hold Timing• 𝐷2 cannot change until after 𝑡ℎ𝑜𝑙𝑑 of the current clock cycle
• 𝑡ℎ𝑜𝑙𝑑 < 𝑡𝑐𝑐𝑞 + 𝑡𝑐𝑑
CLK
Q1
D2
Tc
tpcq
tpd
tsetup
CL
CLKCLK
Q1 D2
R1 R2
CLK
Q1
D2
tccq
tcd
thold
CL
CLKCLK
Q1 D2
R1 R2
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Ch 3.6 Parallelism
• Goal is to increase throughput of circuit
• Two types:• Spatial – duplicate hardware to do same task at once
• Temporal – break task into smaller stages for pipelining (assembly line)• Note: this requires no dependencies between stages
• Token – group of inputs processed to produce group of outputs
• Latency – time for a single token to complete
• Throughput – # tokens produced per unit time
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Parallelism Timeline8
Sp
ati
al
Para
lleli
sm Roll
Bake
Ben 1 Ben 1
Alyssa 1 Alyssa 1
Ben 2 Ben 2
Alyssa 2 Alyssa 2
Time
0 5 10 15 20 25 30 35 40 45 50
Tray 1
Tray 2
Tray 3
Tray 4
Latency:
time to
first tray
Legend
Te
mp
ora
l
Para
lleli
sm Ben 1 Ben 1
Ben 2 Ben 2
Ben 3 Ben 3
Time
0 5 10 15 20 25 30 35 40 45 50
Latency:
time to
first tray
Tray 1
Tray 2
Tray 3
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Pipeline Example
• 𝑡𝑝𝑐𝑞 = 0.3, 𝑡𝑠𝑒𝑡𝑢𝑝 = 0.2 ns
• Identify critical path
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Pipeline Example II
• Two-stage pipeline
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Pipeline Example III
• Three-stage pipeline
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Ch 5 Digital Building Blocks
• Emphasis on full adder (FA) and counter
• Understand ripple adder
• 𝑡𝑟𝑖𝑝𝑝𝑙𝑒 = 𝑁𝑡𝐹𝐴
• Counter increments stored value each clock cycle
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Q
CLK
Reset
N
+
N
1
CLK
Reset
N
N
QN
r
Symbol Implementation
A B
S
Cout
Cin+
N
NN
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Chapter 3.4 Finite State Machine
• Technique for representing synchronous sequential circuit
• Consists of combinational logic and state register
• Moore machine – output only dependent on state (not inputs)
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Chapter 3.4 FSM Design Steps
1. Identify inputs and outputs
2. Sketch state transition diagram
3. Write state transition table
4. Select state encodings
5. Rewrite state transition table with state encodings
6. Write output table
7. Write Boolean equations for next state and output logic
8. Sketch the circuit schematic
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Chapter 3.4 FSM Examples
• Given problem description, give state transition diagram
• Given state transition diagram, encode state and provide next state/output equations
• Given FSM circuit, describe what system does and give state transition/output tables
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Chapter 3.4 FSM Examples
• Design and edge detector circuit. The output should go HIGH for one cycle after the input makes a 0 → 1 transition.
• Single input: A
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FSM Example17
• State transition diagram • State/Output Tables
• Use binary state encoding
𝑺𝟏𝑺𝟎 𝑨 𝑺𝟏′ 𝑺𝟎
′ 𝑸
00 0 00 0
00 1 01 0
01 0 00 1
01 1 10 1
10 0 00 0
10 1 10 0
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FSM Example18
• Equations
• 𝑆1′ = 𝐴𝑆1 + 𝐴𝑆0
• 𝑆0′ = 𝐴 ഥ𝑆1𝑆0
• 𝑄 = 𝑆1
• Circuit diagram
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Ch 1.4 Number Systems
• General number representation
• N-digit number {𝑎𝑁−1𝑎𝑁−2…𝑎1𝑎0} of base 𝑅 in decimal
• 𝑎𝑁−1𝑅𝑁−1 + 𝑎𝑁−2𝑅
𝑁−2 +⋯+ 𝑎1𝑅1 + 𝑎0𝑅
0
• = σ𝑖=0𝑁−1 𝑎𝑖𝑅
𝑖
• What is range of values?
• Should be very familiar with common bases such as 2, 10, 16
• Be able to convert between bases
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Number Example
• What is 101102 in (unsigned) decimal?
• Convert 101102 to base 6
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Binary Addition
• Understand signed number representation (unsigned, two’s complement, sign-mag)
• Addition• Potential for overflow – know how and when occurs
• Subtraction• Find negative of number and do addition
• Zero/sign extension – when should you use which?
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Binary Addition Example
• Assume 4-bit 2’s complement and indicate if overflow occurs
• Add −8 + 4
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Ch 1.5 Logic Gates
• Know circuit symbols and associated truth tables
• NOT/BUF, AND/OR, NAND/NOR, XOR, XNOR
• Be able to determine output from gate level circuit schematic
• Both give truth table and provide Boolean equation
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Ch 2.3-2.4 Boolean Equations
• Sum-of-product (SOP) minterm form
• Product-of-sum (POS) maxterm form
• Simplify using axioms/theorems
• Example
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A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
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Ch 2.7 Kmap
• Convert truth table to Kmap and draw bubbles to maximally cover ones
• Be sure to know how to include don’t cares
• Know up to 5-input function
• Example
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A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
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Ch 2.8 Mux/Decoder
• Know how to do logic with mux or decoder
• Mux
• Decoder
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Ch 2.9 Combinational Timing
• Delay for input to cause a change in output
• Propagation delay 𝑡𝑝𝑑 is longest time to see output change
• Contamination delay 𝑡𝑐𝑑 is shortest time to see output change
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Ch 3.2 Sequential Elements
• Sequential elements store “state” – have memory
• Need to know the operation of different devices
• SR latch, D latch, D flip-flop
• Should also understand the internal circuitry for these elements
• Given a sequential circuit design you can explain operation including timing
• Given a description of operation, build a circuit using sequential building blocks.
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Sequential Element Example
• How does the following work?
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