Chapter5 Ckts B

8/17/2019 Chapter5 Ckts B

1/41

Sequential CMOS and NMOS Logic Circuits

• Sequential logic circuits contain one or more combinational logic

blocks along with memory in a feedback loop with the logic

– he ne!t state of the machine depends on the present state and the inputs

– he output depends on the present state of the machine and perhaps also

on the inputs

• Mealy machine" output depends only on the state of the machine

• Moore machine" the output depends on both the present state and the inputs

• opics to be studied in this section"

– #asic memory cell operation

– S$ Latch

– %& Latch

– ' Latch

– (lip)(lops

– Clocked CMOS Logic

– Cascode *oltage Switch Logic

– Clock 'istribution


2/41

Logic Circuit Classification" Sequential Circuit ypes

• Sequential circuits +also called regenerati,e

circuits- fall into three types"

– Bistable – Monostable

– Astable

• #istable circuits ha,e two stable operating

points and will remain in either state unless

perturbed to the opposite state

– Memory cells. latches. flip)flops. and

registers

• Monostable circuits ha,e only one stable

operating point. and e,en if they are

temporarily perturbed to the opposite state.

they will return in time to their stableoperating point

• /stable circuits ha,e no stable operating

point and oscillate between se,eral states

– $ing oscillator


3/41

Memory Cell" wo)0n,erter #asic #istable 1lement

• / memory cell is comprised of two in,erters

connected back)to)back. i2e2 output of one to

input of the other and ,ice),ersa2• he memory cell +or latch- has two stable

states where the dc ,oltage transfer cur,es

cross at the *O3 and *OL points. but also

e!hibits an unstable state where the *C4s

cross near their *th switching points2

– 0n actual physical circuits the memory cell

will ne,er stay at the unstable point. since

any small electrical noise in the circuit will

trigger it to one side or the other

– 0n numerical simulation +Cadence Spectre-

the circuit may actually remain in the

unstable state +assuming no noise source-

• he CMOS S$/M cell at the left will either

be in state 567 with *68 at 9N' and *6: at

*'' or in state 587 with *68 at *'' and *6:

at 9N'2


4/41

CMOS S$ Latch" NO$ 9ate *ersion• he NO$)based S$ Latch contains the basic

memory cell +back)to)back in,erters- built

into two NO$ gates to allow setting the state

of the latch2

– 0f Set goes high. M8 is turned on forcing ;4

low which. in turn. pulls ; high

• S


5/41

'epletion Load NMOS S$ Latch" NO$ *ersion• / depletion load ,ersion of the NO$)based

S$ latch is shown at left2

– (unctionally same as CMOS ,ersion• he latch is a ratio circuit

– Low side conducts dc current. causing higher

standby power than CMOS ,ersion


6/41

CMOS S$ Latch" N/N' 9ate *ersion

• / CMOS S$ latch built with two :)input

N/N' gates is shown at left

– he basic memory cell comprised of two back)to)back CMOS in,erters is seen

• he circuit responds to acti,e low S and $

inputs

– 0f S goes to 6 +while $ < 8-. ; goes high.

pulling ;4 low and the latch enters Set state

• S


7/41

Clocked S$ Latch" NO$ *ersion

• Shown at left is the NO$)based S$ latch with

a clock added2

– he latch is responsi,e to inputs S and $ only

when CL& is high

– ?hen CL& is low. the latch retains its current

state

• iming diagram shows the le,el)sensiti,e

nature of the clocked S$ latch2

– Note four times where ; changes state"

• ?hen S goes high during positi,e CL&

• On leading CL& edge after changes in S @ $

during CL& low time

• / positi,e glitch in S while CL& is high

• ?hen $ goes high during positi,e CL&


8/41

Clocked CMOS S$ Latch" /O0 0mplementation

• CMOS /O0 implementation of clocked

NO$)based S$ latch shown at left with

logic symbol circuit below – Only 8: transistors required

– ?hen CL& is low. two series legs in N

tree are open and two parallel transistors

in A tree are ON. thus retaining state in the

memory cell

– ?hen CL& is high. the circuit becomes

simply a NO$)based CMOS latch which

will respond to inputs S and $


9/41

Clocked CMOS %& Latch" N/N' *ersion

• he S$ latch has a problem in that when both S

and $ are high. its state becomes indeterminate

• he %& latch shown at left eliminates this problem by using feedback from output to

input. such all states in the truth table are

allowable

– 0f % < & < 6. the latch will hold its present state

– 0f % < 8 and & < 6. the latch will set on the ne!t

positi,e)going clock edge. i2e2 ; < 8. ;4 < 6

– 0f % < 6 and & < 8. the latch will reset on the ne!t

positi,e)going clock edge. i2e2 ;4 < 8 and ; < 6

– 0f % < & < 8. the latch will toggle on the ne!t

positi,e)going clock edge

• Note that in order to pre,ent the %& Latch abo,e

from oscillating continuously during the clock

acti,e time. the clock width must be kept smaller

than the switching delay time of the latch2

Otherwise. se,eral oscillations may occur before

the clock goes low again2 0n practice this may be

difficult to achie,e2


10/41

%& Master)Sla,e (lip)(lop

• / (lip)(lop is defined as two latches connected serially and acti,ated with opposite

phase clocks

– (irst latch is the MasterB Second latch is the Sla,e – 1liminates transparency. i2e2 a change occurring in the primary inputs is ne,er reflected directly

to the outputs. since opposite phase clocks are used to acti,ate the M and S latches2

• / %& master)sla,e flip)flop +NO$)based ,ersion- is shown below"

– he feedback paths occur from ; and ;4 sla,e outputs to the master inputs /O0 gates

– does not e!hibit any tendency to oscillate when % < & < 8 no matter how long the clock period.

since opposite clock phases acti,ate the master and sla,e latches separately2

– he NO$)based ,ersion can be done with four /O0 CMOS gates. requiring : transistors

– Can be susceptible to 5ones catching7. i2e2 a positi,e glitch in either the % or & input while the

CL& is high. which can change the state of the master latch +and the sla,e latch on ne!t edge-


11/41

CMOS ')Latch 0mplementation

• / ')latch is implemented. at the gate le,el. by

simply utiliDing a NO$)based S)$ latch.

connecting ' to input S. and connecting '4 toinput $ with an in,erter2

– ?hen CL& goes high. ' is transmitted to output

; +and '4 to ;4-

– ?hen CL& goes low. the latch retains its

pre,ious state

• he ' latch is normally implemented withtransmission gate +9- switches. as shown at

the left

– he input 9 is acti,ated with CL& while the

latch feedback loop 9 is acti,ated with CL&4

– 0nput ' is accepted when CL& is high

– ?hen CL& goes low. the input is open)circuited

and the latch is set with the prior data '


12/41

CMOS ')Latch Schematic *iew and iming

• / schematic ,iew of the ')Latch can be obtained

using simple switches in place of the 94s

– ?hen CL& < 8. the input switch is closed allowing

new input data into the latch

– ?hen CL& < 6. the input switch is opened and the

feedback loop switch is closed. setting the latch

• iming diagram"

– 0n order to guarantee adequate time to get correct

data at the first in,erter input before the input

switch opens. the data must be ,alid for a gi,en

time +setup- prior to the CL& going low2

– 0n order to guarantee adequate time to set the latch

with correct data. the data must remain ,alid for a

time +hold- after the CL& goes low2

– *iolations of setup and hold can cause metastability

problems and chaotic transient beha,ior2


13/41

/lternate CMOS ')Latch 0mplementation

• /n alternate +preferred- ,ersion of the CMOS

')Latch +shown at left- is implemented with

two tri)state in,erters and a normal CMOSin,erter2

• (unctionally it is similar to the pre,ious chart

')Latch

– ?hen CL& is high. the first tri)state in,erter

sends the in,erted input through to the second

in,erter. while the second tri)state is in its highE state2

• Output ; is following input '

– ?hen CL& is low. the first tri)state goes into

its high E state. while the second tri)state

in,erter closes the feedback loop. holding the

data ; and ;4 in the latch2


14/41

CMOS Static Latches with Single Ahase Clock

• *arious types of ' latch circuit with

single phase clocks

– +a- shows the use of a weak in,erter with

long L +low ?FL- de,ices to allow

remo,al of feedback loop G)gate but

retain static latch function

– +b- ' latch ckt with input in,erter buffer

– +c- implementation of +b- utiliDing tri)

state bufferFin,erter circuits with clocks

at center of tri)state

– /lternate schematic of +c- indicating

layout con,enience due to common tie

point at output of tri)state buffers

• Clock skew problems can be sol,ed on)

chip by using buffering in clock nets

– 0n,erter buffers to generate neg clk

– ransmission gate buffers for true clk


15/41

Construction of ' $egister +(lip)(lop- in CMOS

• wo le,el)sensiti,e latches arecombined to form a positi,e edge)

triggered register. as is used to build a' register

– +a- shows negati,e le,el sensiti,e latch+,alid when clock is negati,e-

– +b- shows positi,e le,el sensiti,e latch+,alid when clock is positi,e-

– +c- shows positi,e edge)triggered 'register +also called a (lip)(lop-comprised of a negati,e latch feeding a positi,e latch

• (irst latch is the Master

• Second latch is the Sla,e

• ' register timing"

– Output ; ,alid at q +clock)to);- delayafter clock edge

– 'ata must be ,alid s +setup time- priorto clock edge and h +hold time- afterclock edge


16/41

CMOS ' (lip)(lop" (alling 1dge)riggered

• Shown below is a ' (lip)(lop. constructed by cascading two ')Latch circuits from the

pre,ious chart

– Master latch is positi,e le,el sensiti,e +recei,es data when CL& is high-

– Sla,e latch is negati,e le,el sensiti,e +recei,es data ;m when CL& is low-

• he circuit is negative-edge triggered

– he master latch recei,es input ' until the CL& falls from high to low. at which point it sets

that data in the master latch and sends it through to the output ;s

$2 ?2 &nepper

SCHI8. page H)=:


17/41

Clocked CMOS Logic +C:MOS-

• Clocked CMOS logic has been used for ,ery

low power CMOS andFor for minimiDing hot

electron effect problems in N)(1 de,ices• Clocking transistors allow ,alid logic output

only when clk is high

• Clocking transistors may be at output end of

logic trees +ma!imum performance- or at

power supply end of logic trees +ma!imum

protection from hot electrons-


18/41

Cascade *oltage Switch Logic +C*SL-• C*SL is a differential type of logic circuit whereby both true and complement inputs are

required

– (or e!ample. true inputs are applied to left pull)down leg below and complement inputs areapplied to right leg

• N pull)down trees are the dual of each other

• A pull)up de,ices are cross)coupled to latch output

• #oth true and complement outputs are obtained

• 0nput pull)down trees may be intermi!ed. depending on the logic to be implemented


19/41

Clocked C*SL +Cascade *oltage Switch Logic-

• Clocked C*SL circuit type shown at left

• 1!ample in +b- is an implementation of ; <

a GO$ b GO$ c GO$ d

– Some similarity to a current steering circuit

in bipolar

– ?hen clock is low. nodes are prechargedB

?hen clock goes high. one leg pulls the

internal output to ground. while opposite leg

is non)conducting

– Complement outputs ; and –; are obtained


20/41

Sample)Set 'ifferential Logic +SS'L-"

'ynamic C*SL with a Latching Sense /mp• SS'L utiliDes a latching sense amplifier

to latch output when clock goes high.

much like a '$/M sense amplifier

• ?hen clock is low A8 @ A: precharge

while N8 pulls down the N tree logic

causing a differential ,oltage on the

internal output nodes• ?hen clock goes high. NJ)NH cause the

sense amplifier to set and latch


21/41

CMOS Schmitt rigger Circuit• he Schmitt rigger circuit.

shown at left. has a dc transfer

characteristic like an in,erter. but

with different switching thresholds

depending on whether *in is

increasing or decreasing

– 3ysteresis effect

• 0f *in is increasing. high * th

• 0f *in is decreasing. low *th

• SA0C1 simulated *C wa,eforms

with increasing and decreasinginput ,oltage are shown at right2

• increasing *in *th < J2H *

• decreasing *in *th < 82= *


22/41

Clocking Strategies for (inite State Machine @

Aipelined Systems• *LS0 systems uni,ersally make use of storage elements and states. with clock+s- to

control the sequencing

• +a- shows a (inite State Machine

– at positi,e clock edge. the ne!t state bits get stored as the current state bits and the current state bits combined with inputs generate new ne!t state bits

• +b- shows a pipelined system indicati,e of today4s microprocessors and logic systems


23/41

iming a Aipelined System

• Aipelined system typically has registers separated by combinational logic

•Minimum cycle time c obtainable gi,en by

Tc = Tq + Td + Ts

– q is the clock)to); output delay of $egister /

– d is the total worst case delay through the combinational logic

– s is the set)up delay time of $egister #

• 0n order to increase frequency in superpipelined and superscalar machines. long

combinational logic blocks can be split into smaller combinational blocks and latches

used to separate the blocks +rather than full registers-

– 0mpro,es o,erall frequency of processor. but adds some delay penalty due to added latches


24/41

he 1ffect of Clock Skew on a Aipeline

• 'esign of a pipelined machine assumes

that clock edges will appear at each

register at a precise time to

• 0f delay occurs in clock distribution due to

$C wire delays. LC ringing on the clock

nets. or buffer delay. the pipeline timing

will be skewed2

– Can cause a latch or register to be set withincorrect data +as shown at right-

• 1!ample"

– $egister M8 is set by the clock at c8.

pro,iding data inputs to the combinational

logic and then to register M:

– $egister M: is supposed to latch in old dataat the same clock edge

– #ut. if the delay to c: K c8 > q8 > logic

delay. M: will incorrectly store the new

data rather than the pre,ious data2


25/41

Clock SynchroniDation sing Ahase Locked Loops

• Ahase Locked Loop

+ALL- is used tosynchroniDe an on)chip

generated clock with a

system clock at some

point on the chip

– $educes clock skew to

Dero at the sensing point

• +a- no ALL – clock skew

• +b- with ALL on chip

• +c- using ALL with

di,ide by = scheme to

achie,e =G freq on)chip

• +d- use of ALL approach

to synchroniDe data

across se,eral chips


26/41

Charge Aump Ahase Locked Loop

• One implementation of a ALL using a

phase detector and charge pump ckt

with a freq multiplier of n times – / phase difference is measured between

the reference clock and the on)chip

clock

– Charge pump pumps a ref ,oltage up or

down depending on phase difference

– Loop filter to clean up ,oltage – *ariable Controller Oscillator +*CO- is

used to obtain e!act frequency clock

• +b- *CO frequency is a function of

control ,oltage applied to N pull)downs

and current mirror

• +c- another approach to control

frequency by using a ,ariable delay line

– MOS capacitance load on each stage is

,aried by N(1 gate ,oltage


27/41

Latch Metastability

• Consider the problem of setting a latch when the data is late andFor has a ,ery longriseFfall time and is still changing during the clock transition

– if data change is delayed and o,erlaps clock edge +below-. latch may set with new datarather than ,alid prior data

• 'ata delay < :2: ns latch sets correctly at ;


28/41

Clock ree 'istribution

• o pre,ent clock skew problems on a

chip. clock distribution networks are

designed ,ery carefully• 1!ample shown" linear +1)?- clock

tree distribution network

– Clock is buffered se,eral times before

dri,ing (O


29/41

%& MS (lip)(lop Aroblem" One4s Catching

• /lthough the %& Master)Sla,e (lip)

(lop can be considered edge)triggered

in regards to a change in ;s at thenegati,e CL& edge. it is actually le,el

sensiti,e in regards to noise on % +or &-

during the CL& high inter,al2

– Note positi,e glitch in % which

erroneously Sets the Master latch at ;m

< 8 during the CL& high inter,al andthen also reflects itself in ;s < 8 at the

negati,e)going CL& edge2

• Called 5One4s Catching7

– Same problem can occur with a glitch

in & during CL& high. causing a $eset

operation

– Since the master latch actually sets and

latches on the noise glitch. the error is

then transmitted to the sla,e latch

during CL&4


30/41

/ Aositi,e)1dge riggered ' (lip)(lop

• ?hy is the N/N')based ' (lip)(lop shown at left edge)triggered and not le,el

sensiti,e

– here is no master latch – he two N/N' gate pairs are clocked with opposite phase clocks. and therefore act similar to

the transmission gates in the 9)based ' flip)flop

• he 8st N/N' pair is clocked with CL&4

• he :nd N/N' pair is clocked with CL&44 < CL&

• $esult"

– ; changes on the positi,e)going CL& edge

– N/N' 8 pair locks in the ,alid data at the negati,e CL& edge

– he master latch is essentially dynamic. holding the state as charge at the inputs of the two

in,erters


31/41

Monostable Multi,ibrator Circuit with 'epletion Loads

• he monostable multivibrator circuit at left

has only one stable state +*out low-

• Operation +$eset-"

– Aull *in high momentarily to reset to *out

high. pulling left node down to some *OL

– Capacitor immediately pulls gate of right

NMOS down turing it O((

– *out immediately charges high to *dd• Operation +imed return to Set-"

– Capacitor slowly charges to roughly *dd

through NMOS depletion transistor

– /fter capacitor charges sufficiently towards

*dd. right)most NMOS transistor turns ON

and switches the latch back to *out low


32/41

/n NMOS Schmitt rigger Circuit

• ransistor SiDes"

– ?FL-M8 < 8

– ?FL-M: < 62H – ?FL-MJ < 86

– ?FL-M= < 8

• 3ow does the circuit work


33/41

Clocked S$ Latch" N/N' *ersion

• N/N' ,ersion of clocked S$ latch with

acti,e high clock is shown

– Circuit is implemented with four N/N' gates.not with an /O0 or O/0

• 8P transistors required

– he latch is responsi,e to S or $ only if CL& is

high

– ?hen CL& is low. the latch retains its present

state


34/41

%& $egister 0mplemented in CMOS

• %& register is implemented by adding

logic to front of a ' register

• Operation" – 0f %& < 68. ; goes to 6 on rising clock

edge

– 0f %& < 86. ; goes to 8 on clock edge

– 0f %& < 66. ; retains prior state

– 0f %& < 88. ; toggles on clock edge

– ?hen clock is down. ; and ;N hold

prior state


35/41

$egister CMOS 0mplementation

• +oggle- $egister is shown below +note error in ?este @ 1shraghian te!t-

– Output ; toggles +changes state- on each positi,e clock edge

– sed as a di,ide by two counter – Comprised of ' register with –; connected to the input

– Clear function is added to the reg below by replacing 8st in,erter in sla,e latch with a N/N'

• Operation"

– ?hen clk goes up. output ; is complemented +and master latch is set-

– ?hen clk goes down. sla,e latch is set2 No change occurs to ;

– ?hen clear goes high. ;M is set to a 587 +; to a 567-


36/41

' $egister 0mplementation in CMOS• CMOS implementation of the popular positi,e edge)triggered ' register is shown

– Comprised of four transmission gates and fi,e in,erters

• Operation – Clock < 6"

• Master latch is connected to input to recei,e new ' data

• Sla,e latch is holding pre,ious data on output and is isolated from input

– Clock < 8"

• Master latch stops sampling input. latches up the ' data at the positi,e clock edge. and sends it

through to the output ;


37/41

CMOS Latch Symbolic Layouts

• ypical layouts of ' latch circuits

– +a- layout of tri)state buffer ' latch

shown on pre,ious slide

– +b- @ +c - two alternate layouts of

con,entional ')latch circuit


38/41

Static $egisters #ased on C*SL and S$/M Structures

• +a- shows a static ' register designed

around C*SL circuits

– Latch 8 is formed with A(14s cross

coupled and is clocked with N(14s

pulling down to cause latch to set

– Latch : is formed with N(14s cross

coupled and uses A(1 transistors to

pull the output nodes toward *dd to set

the latch when Clk is low

• +b- is a ' latch based on an S$/M cell

with N(1 pull)downs to set latch when

Clk goes high

'iff ti l S lit L l C*SL


39/41

'ifferential Split)Le,el C*SL

• *ref is applied to gates of cascode N(14s to

isolate the logic signal inputs from the high

speed output nodes

– *ref is designed to be appro!imately equal to

+*ddF:- > *tn

– #y using *ref. the signal swing on the N logic

trees connected to nodes d and –d is reduced to a

small ,oltage of roughly *ddF:

•A pull)up de,ices are wired as a cross)coupledlatch designed with a full *dd signal

– 9ates of A pull)up transistors are connected

below the N cascode transistors for ma!imum

speed

• +a- shows a simple in,erter

• +b- shows open drain pull)down complementaryoutputs

– N logic trees connect to d and )d


40/41

$egisters with /synchronous Set and $eset

• /synchronous Set and $eset are

added to the ' $egister by replacing

in,erter gates with :)input N/N'

gates in forward or feedback latch

legs +as shown at left-

– +a- /synchronous $eset only

– +b- /synchronous Set and $eset

– #oth registers ha,e an input bufferadded

' i L h i h Si l Cl k


41/41

'ynamic Latches with a Single Clock • 'ynamic latches eliminate dc feedback leg by storing data on gate capacitance of

in,erter +or logic gate- and switching charge in or out with a transmission gate

– Minimum frequency of operation is typically of the order of H6)866 &3D so as not to lose data

due to Qunction or gate leakage from the node – Can be clocked at high frequency since ,ery little delay in latch elements

• 1!amples"

– +a- or +b- show simple transmission gate latch concept

– +c - tri)state in,erter dynamic latch holds data on gate when clk is high

– +d- and +e- dynamic ' register

Chapter5 Ckts B

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Transcript of Chapter5 Ckts B