Chapter2 assemblers

System Programming Mrs. Sunita M Dol, CSE Dept

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Chapter 2. Assemblers

Multiple Choice Questions

1) Series of statements explaining how data is to be processed is called _______

a) Assembler b) machine

c) Pascal d) program

2) Which of the following is true about pseudo code?

a) A machine language

b) Assembly language

c) High level language

d) None of these

3) In two pass assembler the object code generation is done during the ______

a) Second pass

b) First pass

c) Zero pass

d) None of these

4) Which of the following program converts assembly language program to object

programs?

a) Assembler b) compiler

c) Macro processor d) linker

5) Pass-II of assembler _______

a) Assembles instruction and generates code

b) Perform processing of assembler directives not done during Pass-I

c) Write the object program and assembly listing

d) All of these


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6) Symbol table can be used for _______

a) Checking type compatibility

b) Suppressing duplication of error massages

c) Storage allocation

d) All of these

7) Symbolic references in source statement are not processed at all during Pass-I in

_______

a) Variant-I

b) Variant-II

c) Variant-III

d) All above

8) Which directive sets the LC with the address specified by address specification?

a) START b) END

c) ORIGIN d) Both (a) and (c)

9) Which registers are used as base registers in Intel 8088?

a) BP and SP

b) BP and SI

c) BP and BX

d) BX and AX

10) A/An ______ instructs the assembler to perform certain actions during the assembly

of program.

a) Statement format

b) Symbolic operands

c) Assembler directive

d) Data declaration


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11) Which of the following is/are assembler directive(s)?

a) STOP b) READ

c) EQU d) (a) and (b) both

12) All errors are reported against the erroneous statement itself, if error reports are

produced in________

a)Pass-I b)Pass-II

c)(a) and (b) both d)Not possible in both

13) Which of the following is a 8-bit data register in Intel 8088 processor?

a)AX b)BL

c)DS d)SH

14) A/An ________ statement indicates an action to be performed during the execution

of the assembled program.

a) Declarative

b) Imperative

c) Assembler directives

d) All of above

15) Which of the following is not a assembler directive?

a) END b) PRINT

c) ORIGIN d) None of above

16) Intermediate code for "ORIGIN" is

a)(IS,03)

b)(DL,02)

c)(AD,03)

d)(AD,04)


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17)To implement the memory allocation, a data structure called ______ is used in

analysis phase of assembly language.

a) Instruction counter

b) Location counter

c) DS

d) DC

18) _______ translation of an assembly language program can handle forward

references easily.

a) 1-pass

b)2-pass

c)3-pass

d)(a) and (b) both

19) Which is the opcode for MOVER, READ, and MOVEM?

(a) 04, 09, 05

(b) 06, 05, 09

(c) 05, 00, 10

(d) 02, 10, 04


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20) START 101

READ N

PRINT N

N DS 01

What is equivalent machine code?

(a) 101) + 09 0, 103

102 ) + 10 0, 103

103)

(b) 101) + 08 0, 103

102 ) + 10 0, 103

103)

(c) 101) + 09 0, 104

102 ) + 11 0,103

103)

(d) 101) + 07 0, 103

102 ) + 10 0,103

103)


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21) START 101

READ N

PRINT N

N DS 1

What is equivalent variant I for this assembly code?

(a) (AD, 02) (C, 101)

(IS, 09) (S, 01)

(IS, 09) (S, 01)

(DL, 01) (C, 1)

(b)(AD, 01) (C, 101)

(IS, 09) (S, 01)

(IS, 10) (S, 01)

(DL, 02) (C, 1)

(c)(AD, 01) (C, 101)

(IS, 09) (S, 01)

(IS, 02) (S, 01)

(DL, 09) (C, 1)

(d)(AD, 01) (C, 101)

(IS, 09) (S, 01)

(IS, 08) (S, 01)

(DL, 02) (C, 1)

22) Which of the following are features of language programming

(a) Mnemonic operation codes

(b) Symbolic operands

(c) Data declarations

(d) All of the above


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23) Assembly program contains which kind of statement from below

(a) Control structure statement

(b) Loop statement

(c) Declaration statement

(d) None of above

24) What is syntax of declaration statement 'DS'

(a)[Label] DS '<value>'

(b)[Label] DS <constant>

(c)[Label] DS <operand specification>

(d)both (a) and (b)

25) A _____ is an operand with the syntax='<value>'

(a) Constant (b) Variable

(c) Literal (d) Either (a) or (c)

26) Which of the following are assembler directives?

(a)MOVER, MOVEM

(b)READ, PRINT

(c)STOP

(d)START, END

27) Arrange following steps of design specification for assembler

i. Determine the processing necessary to obtain and maintain the

information

ii. Design suitable data structure to record the information

iii. Determine processing necessary to perform task

iv. Identify the information necessary to perform task

(a) i-iii-iv-ii

(b) iv-ii-i-iii

(c) i-ii-iv-iii

(d) iii-iv-ii-I


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28) START 101

READ N

PRINT N

N DS 01

What is equivalent variant I for this.?

(a)(AD, 02) (C, 101)

(IS, 09) N

(IS, 10) N

(DL, 02) (C, 1)

(b)(AD, 01) (C, 101)

(IS, 09) N

(IS, 09) N

(DL, 02) (C, 1)

(c)(AD, 01) (C, 101)

(IS, 09) N

(IS, 10) N

(DL, 09) (C, 1)

(d)(AD, 01) (C, 101)

(IS, 09) N

(IS, 10) N

(DL, 02) (C, 1)

29) A literal differs from constant because

a) Its location can’t be specified

b) Its location can be specified

c) Its value is changed

d) None of above


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30) Pass-I of two pass assembler perform

a) Synthesis

b) Analysis phase

c) Synthesis & analysis

d) None of above

31) Pass-II of two pass assembler perform

a) Synthesis

b) Analysis phase

c) Synthesis & analysis

d) None of above

32) In which case it is not necessary to have a representation of DS statement

a) IC contains address field

b) IC does not contains address field

c) There is no DS statement

d) None of the above

33) By default all the literals are stored

a) At the end of program

b) Start of program

c) After LTORG

d) Middle of the program

34) Literal pool contains all the literals used in program since

a) Start of program

b) Last LTORG statement

c) Both a) & b)

d) None of above


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35) Which of the table(s) is/are used by both pass

a) SYMTAB b) LITTAB

c) OPTAB d) POOLTAB

36) Listing & error reporting should be done in

a) Pass-I b) Pass-II

c) Pass-I & Pass-II d) None of the above

37) For efficiency reason, which table should remain in main memory?

a) SYMTAB

b) LITTAB

c) OPTAB

d) POOLTAB

38. To implement memory allocation a data structure called --------------- is introduced.

(a) Linked List

(b) Record Base Pointer

(c) Location Counter

(d) Address Counter

39. The LC processing is performed in ---------------------.

(a) Synthesis Phase (b) Analysis Phase

(c) Both (a) & (b) (d) None of These

40. The problem of forward references is tackled using a process called ------------ in

single phase assembler.

(a) Backtracking

(b) Synchronization

(c) Aging

(d) Back patching


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41. The address of forward referenced symbol is put into ---------when its definition is

encountered in Single Pass Assembler.

(a) OPTAB (b)SYMTAB

(c) TII Table of incomplete Information (d) Mnemonic Table

42. Which of the following is wrong statement in task performed by two pass

assembler?

(a) Perform LC processing

(b) Construct intermediate representation

(c) Separate the symbol, mnemonic opcode & operand field

(d) Build mnemonic table

43. Which of the following is advanced assembler directives?

(a) START (b) EQU

(c) STOP (d) Both (a) & (c)

44. Syntax of ORIGIN is

(a) ORIGIN <constant>

(b) ORIGIN <operand_spec>

(c) <symbol> ORIGIN <operand_spec>

(d) None of above

45. Variant I &variant II of intermediate code differ in

(a) Address Fields

(b) Information contained in operand fields

(c) Information contained in address specification

(d) Information contained in operand specification


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46. In a 2 pass assembler, the pseudo code EQU is to be evaluated during:

(a) Pass-I

(b) Pass-II

(c) Not evaluated by assembler

(d) None of the above

47. Efficient use of addressing modes

(a) Speeds up execution

(b) Reduces number of instructions

(c) Reduces size of instruction


48. Which of the following addressing mode supports indexing?

(a)Relative

(b)Direct

(c) Immediate

(d)Both (a) and (b)

49. Which of the following is an analytic operator?

(a)SIZE

(b)PTR

(c)THIS


50. A________statement indicates that segment register contains the base address of

segment

(a)START

(b)ASSUME

(c)ORG

(d)Both (a) and (c)


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51. Forward references Table contains following entries:

(a)Address of the instruction whose operand field contains the FR

(b)Symbol to which FR is made

(c)Number of the SRTAB to be used for assembling the reference


52.A___________is created while processing ‘assume’ statement

(a)OPTAB

(b)FRT

(c)SRTAB

(d)CRT

53._______ and _______ delimit the body of procedure.

(a)NEAR and FAR

(b)PROC and ENDP

(c)START and END


54. Which addressing mode the following instruction represents

MOV sum 56H[SI][BX]

(a)Based & Indexed

(b) Immediate

(c)Based

(d)Indexed


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55. Following activities are performed during which pass:

i) Isolate the label, mnemonic opcode and operand fields of statement

ii) Obtain the machine opcode corresponding to mnemonic from the mnemonic

table

iii) Check validity of mnemonic opcode through lookup in mnemonics table

iv) Obtain address of memory operand from symbol table

(a) Pass-I, Pass-II, Pass-I, Pass-II

(b) Pass-II, Pass-II, Pass-I, Pass-I

(c) Pass-I, Pass-I, Pass-II, Pass-II


56. Consider the following assembly code

START 100

MOVER AREG, A

ADD AREG, B

MOVEM AREG, C

STOP

A DC ‘5’

B DC ‘8’

C DS 1

END

The content of symbol table for above code will be

(a)

Symbol Address Length

A 103 1

B 104 1

C 105 1


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(b)


A 104 1

B 105 1

C 106 1

(c)


A 105 1

B 106 1

C 107 1

(d)


A 104 1

B 106 1

C 105 1


START 100

MOVER AREG, =’5’

ADD AREG, B

MOVEM AREG, C

STOP

B DC ‘8’

C DS 1

END


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The content of symbol table for above code will be

(a)

Literal_Table_Pointer Literal Address

1 =‘5’ 106

2

(b)


1 =‘5’ 105

2

(c)


1 =‘5’ 104

2

(e) None of above


START 100


ADD AREG, B

MOVEM AREG, C

STOP

B DC ‘8’

C DS 1

END


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What will be the variant-II intermediate code for above code?

(a)

(AD, 01) (C, 100)

(IS, 04) AREG, (L,01)

(IS, 01) AREG, B

(IS, 05) AREG, C

(IS, 00)

(DL, 02) (C, 8)

(DL, 01) (C, 1)

(b)

(AD, 01) (C, 100)

(IS, 03) AREG, (L,01)

(IS, 02) AREG, B

(IS, 05) AREG, C

(IS, 00)

(DL, 01) (C, 8)

(DL, 02) (C, 1)

(c)

(AD, 01) (C, 100)

(IS, 04) AREG, (L,01)

(IS, 01) AREG, B

(IS, 05) AREG, C

(IS, 00)

(DL, 01) (C, 8)

(DL, 02) (C, 1)

(d)

(AD, 01) (C, 100)

(IS, 04) AREG, (L,01)


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(IS, 01) AREG, B

(IS, 05) AREG, C

(IS, 01)

(DL, 01) (C, 8)

(DL, 02) (C, 1)


START 100

MOVER AREG, A

ADD AREG, B

MOVEM AREG, C

STOP

A DC ‘5’

B DC ‘8’

C DS 1

END

What will be the variant-II intermediate code for above code?

(a)

(AD, 01) (C, 100)

(IS, 04) AREG, A

(IS, 01) AREG, B

(IS, 05) AREG, C

(IS, 00)

(DL, 01) (C, 5)

(DL, 01) (C, 8)

(DL, 02) (C, 1)

(b)

(AD, 01) (C, 100)

(IS, 04) AREG, A

(IS, 01) AREG, B

(IS, 05) AREG, C


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(IS, 00)

(DL, 02) (C, 5)

(DL, 03) (C, 8)

(DL, 02) (C, 1)

(c)

(AD, 01) (C, 100)

(IS, 04) AREG, A

(IS, 01) AREG, B

(IS, 05) AREG, C

(IS, 00)

(DL, 01) (C, 5)

(DL, 01) (C, 8)

(DL, 03) (C, 1)

(d)

(AD, 01) (C, 100)

(IS, 04) AREG, A

(IS, 01) AREG, B

(IS, 05) AREG, C

(IS, 00)

(DL, 02) (C, 5)

(DL, 02) (C, 8)

(DL, 01) (C, 1)


START 100

MOVER AREG, A

ADD AREG, B

MOVEM AREG, C


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STOP

A DC ‘5’

B DC ‘8’

C DS 1

END

What will be the target code for above code?

(a)

101) + 04 1 104

102) + 01 1 105

104) + 05 1 106

105) + 00 0 000

106) + 00 0 005

107) + 00 0 008

108)

(b)

100) + 04 1 104

101) + 01 1 105

102) + 05 1 106

103) + 00 0 000

104) + 00 0 005

105) + 00 0 008

106)

(c)

100) + 02 1 104

101) + 01 1 105

102) + 05 1 106

103) + 00 0 000

104) + 00 0 005

105) + 00 0 008


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106)

(d)

100) + 04 1 104

101) + 01 1 105

102) + 04 1 106

103) + 00 0 000

104) + 00 0 005

105) + 00 0 008

106)


START 100


ADD AREG, B

MOVEM AREG, C

STOP

B DC ‘8’

C DS 1

END

What will be the target code for above code?

(a)

100) + 04 1 106

101) + 01 1 104

102) + 05 1 105

103) + 00 0 000

104) + 00 0 008

105)

106) + 00 0 005


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(b)

100) + 04 1 106

101) + 01 1 104

102) + 04 1 105

103) + 00 0 000

104) + 00 0 008

105)

106) + 00 0 005

(c)

100) + 04 1 106

101) + 02 1 104

102) + 05 1 105

103) + 00 0 000

104) + 00 0 008

105)

106) + 00 0 005

(d)

100) + 04 1 106

101) + 01 1 104

102) + 05 1 105

103) + 00 0 001

104) + 00 0 008

105)

106) + 00 0 005

Chapter2 assemblers

Engineering

Transcript of Chapter2 assemblers