Chapter2 Chapter2 Subject Matter of an International Sales Contract.
chapter2-1 comb logic.pptdigital.lecture.ub.ac.id/.../03/chapter2-1-comb-logic.pdf · 2011. 10....
Transcript of chapter2-1 comb logic.pptdigital.lecture.ub.ac.id/.../03/chapter2-1-comb-logic.pdf · 2011. 10....
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 1
Combinational Combinational Logic CircuitsLogic Circuits(Sections 2.1 (Sections 2.1 –– 2.5)2.5)
19-Mar-10 2Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
OverviewOverviewnn Binary logic and GatesBinary logic and Gatesnn Boolean AlgebraBoolean Algebra
nn Basic PropertiesBasic Propertiesnn Algebraic ManipulationAlgebraic Manipulation
nn Standard and Canonical FormsStandard and Canonical Formsnn Minterms and Maxterms (Canonical forms)Minterms and Maxterms (Canonical forms)nn SOP and POS (Standard forms)SOP and POS (Standard forms)
nn Karnaugh Maps (KKarnaugh Maps (K--Maps)Maps)nn 2, 3, 4, and 5 variable maps2, 3, 4, and 5 variable mapsnn Simplification using KSimplification using K--MapsMaps
nn KK--Map ManipulationMap Manipulationnn Implicants: Prime, EssentialImplicants: Prime, Essentialnn Don’t CaresDon’t Cares
19-Mar-10 3Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Binary LogicBinary Logic
nn Deals with binary variables that take 2 Deals with binary variables that take 2 discrete values (0 and 1), and with logic discrete values (0 and 1), and with logic operationsoperations
nn Three basic logic operations: Three basic logic operations: nn AND, OR, NOTAND, OR, NOT
nn Binary/logic variables are typically Binary/logic variables are typically represented as letters: A,B,C,…,X,Y,Zrepresented as letters: A,B,C,…,X,Y,Z
19-Mar-10 4Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Binary Logic FunctionBinary Logic FunctionF(vars) = F(vars) = expressionexpression
Example: F(a,b) = a’Example: F(a,b) = a’•b + b’•b + b’G(x,y,z) = x•(y+z’)G(x,y,z) = x•(y+z’)
set of binaryset of binaryvariablesvariables
nnOperators ( +, Operators ( +, •, ‘ )•, ‘ )nnVariablesVariablesnnConstants ( 0, 1 )Constants ( 0, 1 )nnGroupings (parenthesis)Groupings (parenthesis)
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 2
19-Mar-10 5Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Basic Logic OperatorsBasic Logic Operators
nn 11--bit logic AND resembles binary bit logic AND resembles binary multiplication:multiplication:
0 0 • 0 = 0,• 0 = 0, 0 • 1 = 0,0 • 1 = 0,1 • 0 = 0,1 • 0 = 0, 1 • 1 = 11 • 1 = 1
nn 11--bit logic OR resembles binary bit logic OR resembles binary addition, except for one operation:addition, except for one operation:
0 +0 + 0 = 0,0 = 0, 0 + 1 = 1,0 + 1 = 1,1 + 0 = 1,1 + 0 = 1, 1 + 1 = 11 + 1 = 1 (≠ 10(≠ 1022))
19-Mar-10 6Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Truth Tables for logic operatorsTruth Tables for logic operatorsTruth tableTruth table:: tabular form that tabular form that uniquelyuniquely represents the represents the relationship between the input variables of a function and relationship between the input variables of a function and its outputits output
AA BB F=AF=A••BB00 00 0000 11 0011 00 0011 11 11
2-Input ANDAA BB F=AF=A++BB00 00 0000 11 1111 00 1111 11 11
2-Input OR
AA F=AF=A’’00 1111 00
NOT
19-Mar-10 7Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Truth Tables (cont.)Truth Tables (cont.)
nn Q: Let a function F() depend on Q: Let a function F() depend on nnvariables. How many rows are there in variables. How many rows are there in the truth table of F() ?the truth table of F() ?
A: 2n rows, since there are 2n possible binary patterns/combinations for the n variables
19-Mar-10 8Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Logic GatesLogic Gatesnn Logic gates are abstractions of electronic Logic gates are abstractions of electronic
circuit components that operate on one or circuit components that operate on one or more input signals to produce an output signal.more input signals to produce an output signal.
2-Input AND 2-Input OR NOT (Inverter)
A A AB BF G H
F = AF = A••BB G = A+BG = A+B H = A’H = A’
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 3
19-Mar-10 9Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Timing DiagramTiming Diagram
A
B
F=A••B
G=A++B
H=A’
1
1
1
1
10
0
0
0
0
t0 t1 t2 t3 t4 t5 t6
Inputsignals
GateOutputSignals
Basic Assumption:Zero time forsignals topropagate Through gates
Transitions
19-Mar-10 10Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Combinational Logic CircuitCombinational Logic Circuitfrom Logic Functionfrom Logic Function
nn Consider function F = A’ + BConsider function F = A’ + B•C’ + A’••C’ + A’•BB’ ’ nn A combinational logic circuit can be constructed to implement F, A combinational logic circuit can be constructed to implement F,
by appropriately connecting input signals and logic gates:by appropriately connecting input signals and logic gates:nn Circuit input signals Circuit input signals àà from function variables (A, B, C)from function variables (A, B, C)nn Circuit output signal Circuit output signal àà function output (F)function output (F)nn Logic gates Logic gates àà from logic operationsfrom logic operations
A
B
C
F
19-Mar-10 11Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Combinational Logic CircuitCombinational Logic Circuitfrom Logic Function (cont.)from Logic Function (cont.)
nn In order to design a costIn order to design a cost--effective and efficient circuit, effective and efficient circuit, we must minimize the circuit’s we must minimize the circuit’s size (area) and propagation size (area) and propagation delay (time required for an input delay (time required for an input signal change to be observed at signal change to be observed at the output line)the output line)
nn Observe the truth table of F=A’ Observe the truth table of F=A’ + B+ B•C’ + A’••C’ + A’•BB’ and G’ and G=A’ + B=A’ + B•C’ •C’
nn Truth tables for F and G are Truth tables for F and G are identical identical àà same functionsame function
nn Use G to implement the logic Use G to implement the logic circuit (less components)circuit (less components)
AA BB CC FF GG00 00 00 11 1100 00 11 11 1100 11 00 11 1100 11 11 11 1111 0 0 00 00 0011 00 11 00 0011 11 00 11 1111 11 11 00 00
19-Mar-10 12Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Combinational Logic CircuitCombinational Logic Circuitfrom Logic Function (cont.)from Logic Function (cont.)
A
B
C
F
ABC
G
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 4
19-Mar-10 13Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Boolean AlgebraBoolean Algebra
nn VERY nice machinery used to manipulate VERY nice machinery used to manipulate (simplify) Boolean functions(simplify) Boolean functions
nn George Boole (1815George Boole (1815--1864): “An 1864): “An investigation of the laws of thought”investigation of the laws of thought”
nn Terminology:Terminology:nn Literal:Literal: A variable or its complementA variable or its complementnn Product term:Product term: literals connected by literals connected by ••nn Sum term:Sum term: literals connected by +literals connected by +
19-Mar-10 14Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Boolean Algebra PropertiesBoolean Algebra PropertiesLet X: boolean variable, 0,1: constantsLet X: boolean variable, 0,1: constants
1.1. X + 0 = X X + 0 = X ---- Zero AxiomZero Axiom2.2. X X • 1 = X • 1 = X ---- Unit AxiomUnit Axiom3.3. X + 1 = 1 X + 1 = 1 ---- Unit PropertyUnit Property4.4. X X • 0 = 0 • 0 = 0 ---- Zero PropertyZero Property
19-Mar-10 15Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Boolean Algebra Properties (cont.)Boolean Algebra Properties (cont.)
Let X: boolean variable, 0,1: constantsLet X: boolean variable, 0,1: constants
5.5. X + X = X X + X = X ---- IdepotenceIdepotence6.6. X X • X = X • X = X ---- IdepotenceIdepotence7.7. X + X’ = 1 X + X’ = 1 ---- ComplementComplement8.8. X X • X’ = 0 • X’ = 0 ---- ComplementComplement9.9. (X’)’ = X(X’)’ = X ---- InvolutionInvolution
Unchanged in value following
multiplication by itself
19-Mar-10 16Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
The Duality PrincipleThe Duality Principlenn The dual of an expression is obtained by The dual of an expression is obtained by
exchanging (exchanging (•• and +), and (1 and 0) in it, and +), and (1 and 0) in it, provided that the precedence of operations is provided that the precedence of operations is not changed.not changed.
nn Cannot exchange x with x’ Cannot exchange x with x’ nn Example: Example:
nn Find H(x,y,z), the dual of F(x,y,z) = x’yz’ + x’y’zFind H(x,y,z), the dual of F(x,y,z) = x’yz’ + x’y’znn H = (x’+y+z’) (x’+y’+ z)H = (x’+y+z’) (x’+y’+ z)
nn Dual does not always equal the original Dual does not always equal the original expressionexpression
nn If a Boolean equation/equality is valid, its dual is also If a Boolean equation/equality is valid, its dual is also validvalid
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 5
19-Mar-10 17Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
The Duality Principle (cont.)The Duality Principle (cont.)With respect to duality, Identities 1 – 8 have the
following relationship:
1. X + 0 = X 2. X • 1 = X (dual of 1)3. X + 1 = 1 4. X • 0 = 0 (dual of 3)5. X + X = X 6. X • X = X (dual of 5)7. X + X’ = 1 8. X • X’ = 0 (dual of 8)
19-Mar-10 18Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
More Boolean Algebra PropertiesMore Boolean Algebra PropertiesLet X,Y, and Z: boolean variablesLet X,Y, and Z: boolean variables
10.10. X + Y = Y + XX + Y = Y + X 11.11. X X • Y = • Y = Y Y • X • X ---- CommutativeCommutative12.12. X + (Y+Z) = (X+Y) + Z X + (Y+Z) = (X+Y) + Z 13.13. XX•(Y•Z) = (X••(Y•Z) = (X•Y)Y)•Z •Z ---- AssociativeAssociative14.14. XX••(Y+Z) = X(Y+Z) = X•Y + X•Z •Y + X•Z 15.15. X+(YX+(Y••Z) = (XZ) = (X+Y) • (X+Z)+Y) • (X+Z)
---- DistributiveDistributive16.16. ((X + Y)’ = X’ X + Y)’ = X’ • Y’• Y’ 17.17. ((X X •• Y)’ = X’ +Y)’ = X’ + Y’Y’ ---- DeMorgan’sDeMorgan’s
In general,In general,( X( X11 + X+ X22 + … + X+ … + Xnn )’ = X)’ = X11’’••XX22’’ •• … … ••XXnn’, and ’, and ( X( X11••XX22••… … ••XXnn )’ = X)’ = X11’’ + + XX22’’ + + …… + + XXnn’’
19-Mar-10 19Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Absorption Property (Covering)Absorption Property (Covering)
1.1. x + x + x•yx•y = x= x2.2. x•(x•(x+yx+y) = x (dual)) = x (dual)nn Proof:Proof:
x + x + x•yx•y = x•1 + = x•1 + x•yx•y= x•(1+y) = x•(1+y) = x•1= x•1= x= x
QED (QED (22 true by duality)true by duality)
19-Mar-10 20Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Consensus TheoremConsensus Theorem
1.1. xyxy + + x’zx’z + + yzyz = = xyxy + + x’zx’z2.2. ((x+yx+y)•()•(x’+zx’+z)•)•((y+zy+z) ) = (= (x+yx+y)•()•(x’+zx’+z) ) ---- (dual)(dual)nn Proof:Proof:
xyxy + + x’zx’z + + yzyz = = xyxy + + x’zx’z + (+ (x+xx+x’)’)yzyz= = xyxy + + x’zx’z + xyz + + xyz + x’yzx’yz= (= (xyxy + xyz) + (+ xyz) + (x’zx’z + + x’zyx’zy))
nn = = xyxy(1(1 + z) + + z) + x’zx’z(1(1 + y)+ y)= = xyxy + + x’zx’z
QED (QED (22 true by duality).true by duality).
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 6
19-Mar-10 21Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Truth Tables (revisited)Truth Tables (revisited)
nn Enumerates all possible Enumerates all possible combinations of variable combinations of variable values and the corresponding values and the corresponding function value function value
nn Truth tables for some Truth tables for some arbitrary functions arbitrary functions FF11(x,y,z), F(x,y,z), F22(x,y,z), and (x,y,z), and FF33(x,y,z) are shown to the (x,y,z) are shown to the right.right.
xx yy zz FF11 FF22 FF33
00 00 00 00 11 1100 00 11 00 00 1100 11 00 00 00 1100 11 11 00 11 1111 00 00 00 11 0011 00 11 00 11 0011 11 00 00 00 0011 11 11 11 00 11
19-Mar-10 22Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Truth Tables (cont.)Truth Tables (cont.)nn Truth table: a Truth table: a uniqueunique representation of a representation of a
Boolean functionBoolean functionnn If two functions have identical truth tables, If two functions have identical truth tables,
the functions are equivalent (and vicethe functions are equivalent (and vice--versa).versa).nn Truth tables can be used to prove equality Truth tables can be used to prove equality
theorems. theorems. nn However, the size of a truth table grows However, the size of a truth table grows
exponentiallyexponentially with the number of variables with the number of variables involved, hence unwieldy. This motivates the involved, hence unwieldy. This motivates the use of Boolean Algebra.use of Boolean Algebra.
19-Mar-10 23Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Boolean expressionsBoolean expressions--NOT uniqueNOT unique
nn Unlike truth tables, expressions Unlike truth tables, expressions representing a Boolean function are representing a Boolean function are NOT unique.NOT unique.
nn Example:Example:nn F(x,y,z) = x’F(x,y,z) = x’••y’y’••z’ + x’z’ + x’••yy••z’ + xz’ + x••yy••z’z’nn G(x,y,z) = x’G(x,y,z) = x’•y’••y’•z’ + yz’ + y••z’z’
nn The corresponding truth tables for The corresponding truth tables for F() and G() are to the right. They are F() and G() are to the right. They are identical!identical!
nn Thus, F() = G()Thus, F() = G()
xx yy zz FF GG00 00 00 11 1100 00 11 00 0000 11 00 11 1100 11 11 00 0011 00 00 00 0011 00 11 00 0011 11 00 11 1111 11 11 00 00
19-Mar-10 24Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Algebraic ManipulationAlgebraic Manipulationnn Boolean algebra is a useful tool for Boolean algebra is a useful tool for
simplifying digital circuits.simplifying digital circuits.nn Why do it? Simpler can mean cheaper, Why do it? Simpler can mean cheaper,
smaller, faster.smaller, faster.nn Example: Simplify F = Example: Simplify F = x’yzx’yz + + x’yzx’yz’ + ’ + xzxz..
FF = = x’yzx’yz + + x’yzx’yz’’ + + xzxz= = x’yx’y((z+zz+z’)’) + + xzxz= = x’y•1x’y•1 + + xzxz= = x’yx’y + + xzxz
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 7
19-Mar-10 25Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Algebraic Manipulation (cont.)Algebraic Manipulation (cont.)nn Example: ProveExample: Prove
x’y’zx’y’z’ + ’ + x’yzx’yz’ + xyz’ = ’ + xyz’ = x’zx’z’ + ’ + yzyz’’nn Proof:Proof:
x’y’zx’y’z’+ ’+ x’yzx’yz’’+ xyz’+ xyz’= = x’y’zx’y’z’ + ’ + x’yzx’yz’ + ’ + x’yzx’yz’’ + xyz’+ xyz’= = x’zx’z’(’(y’+yy’+y) + ) + yzyz’(’(x’+xx’+x))= x’z’•1 + yz’•1= x’z’•1 + yz’•1= = x’zx’z’ + ’ + yzyz’’
QED.QED.
19-Mar-10 26Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Complement of a FunctionComplement of a Function
nn The complement of a function is derived The complement of a function is derived by interchanging (by interchanging (•• and +), and (1 and 0), and +), and (1 and 0), and complementing each variable.and complementing each variable.
nn Otherwise, interchange 1s to 0s in the Otherwise, interchange 1s to 0s in the truth table column showing F.truth table column showing F.
nn The The complementcomplement of a function IS NOT of a function IS NOT THE SAME as the THE SAME as the dualdual of a function.of a function.
19-Mar-10 27Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Complementation: ExampleComplementation: Example
nn Find G(x,y,z), the complement ofFind G(x,y,z), the complement ofF(x,y,z) = xy’z’ + x’yzF(x,y,z) = xy’z’ + x’yz
nn G = F’ = (xy’z’ + x’yz)’G = F’ = (xy’z’ + x’yz)’= (xy’z’)’ • (x’yz)’= (xy’z’)’ • (x’yz)’ DeMorganDeMorgan= (x’+y+z) • (x+y’+z’) = (x’+y+z) • (x+y’+z’) DeMorgan DeMorgan againagain
nn Note: The complement of a function can also Note: The complement of a function can also be derived by finding the function’s be derived by finding the function’s dual, dual, and and then complementing all of the literalsthen complementing all of the literals
19-Mar-10 28Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Canonical and Standard FormsCanonical and Standard Forms
nn We need to consider formal techniques We need to consider formal techniques for the simplification of Boolean for the simplification of Boolean functions.functions.nn Minterms and MaxtermsMinterms and Maxtermsnn SumSum--ofof--Minterms and ProductMinterms and Product--ofof--MaxtermsMaxtermsnn Product and Sum termsProduct and Sum termsnn SumSum--ofof--Products (SOP) and ProductProducts (SOP) and Product--ofof--Sums Sums
(POS)(POS)
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 8
19-Mar-10 29Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
DefinitionsDefinitionsnn Literal:Literal: A variable or its complementA variable or its complementnn Product term:Product term: literals connected by literals connected by ••nn Sum term:Sum term: literals connected by +literals connected by +nn Minterm:Minterm: a product term in which all the a product term in which all the
variables appear exactly once, either variables appear exactly once, either complemented or uncomplementedcomplemented or uncomplemented
nn Maxterm:Maxterm: a sum term in which all the a sum term in which all the variables appear exactly once, either variables appear exactly once, either complemented or uncomplementedcomplemented or uncomplemented
19-Mar-10 30Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
MintermMintermnn Represents exactly one combination in the Represents exactly one combination in the
truth table.truth table.nn Denoted by Denoted by mmjj, where , where jj is the decimal is the decimal
equivalent of the minterm’s corresponding equivalent of the minterm’s corresponding binary combination binary combination (b(bjj))..
nn A variable in A variable in mmjj is complemented if its value in is complemented if its value in bbjj is 0, otherwise is uncomplemented.is 0, otherwise is uncomplemented.
nn Example: Assume 3 variables (A,B,C), and Example: Assume 3 variables (A,B,C), and jj=3. =3. Then, bThen, bjj = 011 and its corresponding minterm is = 011 and its corresponding minterm is denoted by denoted by mmjj = A’BC= A’BC
19-Mar-10 31Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
MaxtermMaxtermnn Represents exactly one combination in the Represents exactly one combination in the
truth table.truth table.nn Denoted by Denoted by MMjj, where , where jj is the decimal is the decimal
equivalent of the maxterm’s corresponding equivalent of the maxterm’s corresponding binary combination binary combination (b(bjj))..
nn A variable in A variable in MMjj is complemented if its value in is complemented if its value in bbjj is 1, otherwise is uncomplemented.is 1, otherwise is uncomplemented.
nn Example: Assume 3 variables (A,B,C), and Example: Assume 3 variables (A,B,C), and jj=3. =3. Then, bThen, bjj = 011 and its corresponding maxterm = 011 and its corresponding maxterm is denoted by Mis denoted by Mjj = A+B’+C’= A+B’+C’
19-Mar-10 32Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Truth Table notation for Truth Table notation for Minterms and MaxtermsMinterms and Maxterms
nn Minterms and Minterms and Maxterms are Maxterms are easy to denote easy to denote using a truth using a truth table.table.
nn Example: Example: Assume 3 Assume 3 variables x,y,z variables x,y,z (order is fixed)(order is fixed)
xx yy zz MintermMinterm MaxtermMaxterm
00 00 00 x’y’z’ = mx’y’z’ = m00 x+y+z = Mx+y+z = M00
00 00 11 x’y’z = mx’y’z = m11 x+y+z’ = Mx+y+z’ = M11
00 11 00 x’yz’ = mx’yz’ = m22 x+y’+z = Mx+y’+z = M22
00 11 11 x’yz = mx’yz = m33 x+y’+z’= Mx+y’+z’= M33
11 00 00 xy’z’ = mxy’z’ = m44 x’+y+z = Mx’+y+z = M44
11 00 11 xy’z = mxy’z = m55 x’+y+z’ = Mx’+y+z’ = M55
11 11 00 xyz’ = mxyz’ = m66 x’+y’+z = Mx’+y’+z = M66
11 11 11 xyz = mxyz = m77 x’+y’+z’ = Mx’+y’+z’ = M77
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 9
19-Mar-10 33Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Canonical Forms (Unique)Canonical Forms (Unique)nn Any Boolean function F( ) can be Any Boolean function F( ) can be
expressed as a expressed as a uniqueunique sumsum of of minminterms terms and a unique and a unique productproduct of of maxmaxterms (under terms (under a fixed variable ordering).a fixed variable ordering).
nn In other words, every function F() has In other words, every function F() has two canonical forms:two canonical forms:nn Canonical SumCanonical Sum--OfOf--Products (sum of Products (sum of
minterms)minterms)nn Canonical ProductCanonical Product--OfOf--SumsSums (product of (product of
maxterms)maxterms)
19-Mar-10 34Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Canonical Forms (cont.)Canonical Forms (cont.)
nn Canonical SumCanonical Sum--OfOf--Products:Products:The minterms included are those mThe minterms included are those mjjsuch that F( ) = 1 in row such that F( ) = 1 in row jj of the truth of the truth table for F( ).table for F( ).
nn Canonical ProductCanonical Product--OfOf--Sums:Sums:The maxterms included are those MThe maxterms included are those Mjjsuch that F( ) = 0 in row such that F( ) = 0 in row jj of the truth of the truth table for F( ).table for F( ).
19-Mar-10 35Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
ExampleExamplenn Truth table for fTruth table for f11(a,b,c) at right(a,b,c) at rightnn The canonical sumThe canonical sum--ofof--products form products form
for ffor f11 isisff11(a,b,c) = m(a,b,c) = m11 + m+ m22 + m+ m44 + m+ m66
= a’b’c + a’bc’ + ab’c’ + abc’= a’b’c + a’bc’ + ab’c’ + abc’nn The canonical productThe canonical product--ofof--sums form sums form
for ffor f1 1 isisff11(a,b,c) = M(a,b,c) = M00 •• MM33 • • MM55 • • MM77
= (a+b+c)= (a+b+c)••(a+b’+c’)(a+b’+c’)• • (a’+b+c’)(a’+b+c’)••(a’+b’+c’).(a’+b’+c’).
nn Observe that: mObserve that: mjj = M= Mjj’’
aa bb cc ff11
00 00 00 0000 00 11 1100 11 00 1100 11 11 0011 00 00 1111 00 11 0011 11 00 1111 11 11 00
19-Mar-10 36Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Shorthand: Shorthand: ∑∑ and and ∏∏nn ff11(a,b,c) = (a,b,c) = ∑∑ mm(1,2,4,6), where(1,2,4,6), where ∑∑ indicates indicates
that this is a sumthat this is a sum--ofof--products form, and products form, and m(1,2,4,6) indicates that the minterms to be m(1,2,4,6) indicates that the minterms to be included are mincluded are m11, m, m22, m, m44, and m, and m66..
nn ff11(a,b,c) = (a,b,c) = ∏∏ M(0,3,5,7), where M(0,3,5,7), where ∏∏ indicates indicates that this is a productthat this is a product--ofof--sums form, and sums form, and M(0,3,5,7) indicates that the maxterms to be M(0,3,5,7) indicates that the maxterms to be included are Mincluded are M00, M, M33, M, M55, and M, and M77..
nn Since Since mmjj = M= Mjj’ for any ’ for any jj,,∑∑ mm(1,2,4,6) = (1,2,4,6) = ∏∏ M(0,3,5,7) = fM(0,3,5,7) = f11(a,b,c) (a,b,c)
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 10
19-Mar-10 37Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Conversion Between Canonical FormsConversion Between Canonical Forms
nn Replace Replace ∑∑ with with ∏∏ (or (or vice versavice versa) and replace those ) and replace those j’j’s that appeared in the original form with those that s that appeared in the original form with those that do not.do not.
nn Example:Example:ff11(a,b,c)(a,b,c) = a’b’c + a’bc’ + ab’c’ + abc’ = a’b’c + a’bc’ + ab’c’ + abc’
= m= m11 + m+ m22 + m+ m44 + m+ m66
= = ∑∑((1,2,4,61,2,4,6))= = ∏∏((0,3,5,70,3,5,7))= (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)= (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)
19-Mar-10 38Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Standard Forms (NOT Unique)Standard Forms (NOT Unique)nn Standard forms are “Standard forms are “like”like” canonical canonical
forms, except that not all variables forms, except that not all variables need appear in the individual product need appear in the individual product (SOP) or sum (POS) terms.(SOP) or sum (POS) terms.
nn Example:Example:ff11(a,b,c) = a’b’c + bc’ + ac’(a,b,c) = a’b’c + bc’ + ac’is a is a standardstandard sumsum--ofof--products formproducts form
nn ff11(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)is a is a standardstandard productproduct--ofof--sums form.sums form.
19-Mar-10 39Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Conversion of SOP from Conversion of SOP from standard to canonical formstandard to canonical form
nn Expand Expand nonnon--canonicalcanonical terms by inserting terms by inserting equivalent of 1 in each missing variable x:equivalent of 1 in each missing variable x:(x + x’) = 1(x + x’) = 1
nn Remove duplicate mintermsRemove duplicate mintermsnn ff11(a,b,c) = a’b’c + bc’ + ac’(a,b,c) = a’b’c + bc’ + ac’
= a’b’c + = a’b’c + (a+a’)(a+a’)bc’ + abc’ + a(b+b’)(b+b’)c’c’= a’b’c + = a’b’c + abc’abc’ + a’bc’ + + a’bc’ + abc’abc’ + ab’c’+ ab’c’= a’b’c + abc’ + a’bc + ab’c’= a’b’c + abc’ + a’bc + ab’c’
19-Mar-10 40Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Conversion of POS from Conversion of POS from standard to canonical formstandard to canonical form
nn Expand noncanonical terms by adding 0 in terms Expand noncanonical terms by adding 0 in terms of missing variables (of missing variables (e.g.e.g., xx’ = 0) and using the , xx’ = 0) and using the distributive lawdistributive law
nn Remove duplicate maxtermsRemove duplicate maxtermsnn ff11(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
= (a+b+c)•(= (a+b+c)•(aa’aa’+b’+c’)•(a’++b’+c’)•(a’+bb’bb’+c’)+c’)= (a+b+c)•(a+b’+c’)•= (a+b+c)•(a+b’+c’)•(a’+b’+c’)(a’+b’+c’)••
(a’+b+c’)•(a’+b+c’)•(a’+b’+c’)(a’+b’+c’)= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•(a’+b+c’)= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•(a’+b+c’)
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 11
19-Mar-10 41Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Karnaugh MapsKarnaugh Mapsnn Karnaugh maps (KKarnaugh maps (K--maps) are maps) are graphicalgraphical
representations of boolean functions.representations of boolean functions.nn One One map cellmap cell corresponds to a row in corresponds to a row in
the truth table.the truth table.nn Also, one map cell corresponds to a Also, one map cell corresponds to a
minterm or a maxterm in the boolean minterm or a maxterm in the boolean expressionexpression
nn MultipleMultiple--cell areas of the map cell areas of the map correspond to standard termscorrespond to standard terms..
19-Mar-10 42Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
TwoTwo--Variable MapVariable Map
m3m21
m1m00
10x1x2
0 1
2 3
NOTE: ordering of variables is IMPORTANT for f(x1,x2), x1 is the row, x2 is the column.
Cell 0 represents x1’x2’; Cell 1 represents x1’x2; etc. If a minterm is present in the function, then a 1 is placed in the corresponding cell.
m3m11
m2m00
10x2x1
0 2
1 3OR
19-Mar-10 43Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
TwoTwo--Variable Map (cont.)Variable Map (cont.)
nn Any two adjacent cells in the map differ Any two adjacent cells in the map differ by ONLY one variable, which appears by ONLY one variable, which appears complemented in one cell and complemented in one cell and uncomplemented in the other. uncomplemented in the other.
nn Example:Example:mm0 0 (=x(=x11’x’x22’) is adjacent to m’) is adjacent to m1 1 (=x(=x11’x’x22) and ) and mm2 2 (=x(=x11xx22’) but NOT m’) but NOT m3 3 (=x(=x11xx22) )
19-Mar-10 44Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
22--Variable Map Variable Map ---- Example Example nn f(xf(x11,x,x22) = x) = x11’x’x22’+ x’+ x11’x’x22 + x+ x11xx22’ ’
= m= m00 + m+ m11 + m+ m22= x= x11’ + x’ + x22’’
nn 1s placed in K1s placed in K--map for map for specified minterms mspecified minterms m00, m, m11, m, m22
nn Grouping (ORing) of 1s allows Grouping (ORing) of 1s allows simplificationsimplification
nn What (simpler) function is What (simpler) function is represented by each dashed represented by each dashed rectangle?rectangle?nn aa11’ = m’ = m00 + m+ m11nn aa22’ = m’ = m00 + m+ m22
nn Note mNote m00 covered twicecovered twice
xx11 00 11
00 11 11
11 11 00
x2
0 1
2 3
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 12
19-Mar-10 45Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Minimization as SOP using KMinimization as SOP using K--mapmap
nn Enter 1s in the KEnter 1s in the K--map for each product map for each product term in the functionterm in the function
nn Group Group adjacentadjacent KK--map cells containing 1s map cells containing 1s to obtain a product with fewer to obtain a product with fewer variables. Groups must be in power of 2 variables. Groups must be in power of 2 (2, 4, 8, …)(2, 4, 8, …)
nn Handle “boundary wrap” for KHandle “boundary wrap” for K--maps of 3 maps of 3 or more variables.or more variables.
nn Realize that answer may not be uniqueRealize that answer may not be unique
19-Mar-10 46Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
ThreeThree--Variable MapVariable Map
m6m7m5m41
m2m3m1m00
10110100yz
x0 1 3 2
4 5 7 6
-Note: variable ordering is (x,y,z); yz specifies column, x specifies row.-Each cell is adjacent to three other cells (left or right or top or bottom or edge wrap)
19-Mar-10 47Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
ThreeThree--Variable Map (cont.)Variable Map (cont.)
The types of structures The types of structures that are either minterms or that are either minterms or are generated by repeated are generated by repeated application of the application of the minimization theorem on a minimization theorem on a three variable map are three variable map are shown at right. shown at right. Groups of 1, 2, 4, 8 are Groups of 1, 2, 4, 8 are possible.possible.
minterm
group of 2 terms
group of 4 terms19-Mar-10 48Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
SimplificationSimplification
nn Enter minterms of the Boolean function Enter minterms of the Boolean function into the map, then group termsinto the map, then group terms
nn Example: f(a,b,c) = Example: f(a,b,c) = ac’ac’ + + abcabc + + bc’bc’nn Result: f(a,b,c) = Result: f(a,b,c) = ac’ac’+ + bb
11 11 1111 11
abc
11 11 1111 11
00 01 10 11
0
1
00 01 10 11
0
1
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 13
19-Mar-10 49Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
More ExamplesMore Examples
nn ff11(x, y, z) = (x, y, z) = ∑∑ m(2,3,5,7)m(2,3,5,7)
nn ff22(x, y, z) = (x, y, z) = ∑∑ m (0,1,2,3,6)m (0,1,2,3,6)
nn ff11(x, y, z) = x’y + xz(x, y, z) = x’y + xz
nnff22(x, y, z) = x’+yz’(x, y, z) = x’+yz’
yzyzXX 0000 0101 1111 1010
00 11 1111 11 11
11 11 11 1111
19-Mar-10 50Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
FourFour--Variable MapsVariable Maps
nn Top cells are adjacent to bottom cells. LeftTop cells are adjacent to bottom cells. Left--edge cells are adjacent to rightedge cells are adjacent to right--edge cells.edge cells.
nn Note variable ordering (WXYZ).Note variable ordering (WXYZ).
m11m10m9m810
m14m15m13m1211
m6m7m5m401
m2m3m1m000
10110100WX
YZ
19-Mar-10 51Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
FourFour--variable Map Simplificationvariable Map Simplificationnn One square represents a minterm of 4 One square represents a minterm of 4
literals.literals.nn A rectangle of 2 adjacent squares represents A rectangle of 2 adjacent squares represents
a product term of 3 literals.a product term of 3 literals.nn A rectangle of 4 squares represents a A rectangle of 4 squares represents a
product term of 2 literals.product term of 2 literals.nn A rectangle of 8 squares represents a A rectangle of 8 squares represents a
product term of 1 literal.product term of 1 literal.nn A rectangle of 16 squares produces a function A rectangle of 16 squares produces a function
that is equal to logic 1.that is equal to logic 1.
19-Mar-10 52Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
ExampleExamplenn Simplify the following Boolean function Simplify the following Boolean function
(A,B,C,D) = (A,B,C,D) = ∑∑m(0,1,2,4,5,7,8,9,10,12,13).m(0,1,2,4,5,7,8,9,10,12,13).nn First put the function g( ) into the map, and First put the function g( ) into the map, and
then group as many 1s as possible.then group as many 1s as possible.cd
ab
111
11
111
111
g(A,B,C,D) = c’+b’d’+a’bdg(A,B,C,D) = c’+b’d’+a’bd
111
11
111
111
00 01 11 10
00
01
11
10
00 01 11 10
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 14
19-Mar-10 53Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
55--Variable KVariable K--MapMap
101198
13 141512
5 674
1 230
BCDE
26272524
30312928
22232120
18191716
BCDE
A=0
A=1
A’BCDE’
ABCDE’
19-Mar-10 54Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Implicants and Implicants and Prime Implicants (PIs)Prime Implicants (PIs)
nn An An ImplicantImplicant (P) (P) of a function F is a of a function F is a product term which implies F, i.e., F(P) = 1.product term which implies F, i.e., F(P) = 1.
nn An implicant (PI) An implicant (PI) of F is called a of F is called a Prime Prime ImplicantImplicant of F if any product term of F if any product term obtained by deleting a literal of PI is NOT obtained by deleting a literal of PI is NOT an implicant of Fan implicant of F
nn Thus, a prime implicant is not contained in Thus, a prime implicant is not contained in any “larger” implicant.any “larger” implicant.
19-Mar-10 55Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
ExampleExamplenn Consider function f(a,b,c,d) whose Consider function f(a,b,c,d) whose
KK--map is shown at right.map is shown at right.nn a’b’a’b’ is is notnot a prime implicant a prime implicant
because it is contained in because it is contained in b’.b’.nn acdacd is is notnot a prime implicant a prime implicant
because it is contained in because it is contained in adad..nn b’, ad, and a’cd’ are prime b’, ad, and a’cd’ are prime
implicants.implicants. 111
111
111
11
b’
cd abad
a’cd’
a’b’
acd
19-Mar-10 56Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Essential Prime Implicants (EPIs)Essential Prime Implicants (EPIs)
nn If a minterm of a function F is included in If a minterm of a function F is included in ONLY one prime implicant ONLY one prime implicant pp, then , then p p is an is an essential prime implicantessential prime implicant of F.of F.
nn An essential prime implicant MUST appear in An essential prime implicant MUST appear in all possible SOP expressions of a function all possible SOP expressions of a function
nn To find essential prime implicants:To find essential prime implicants:nn Generate all prime implicants of a functionGenerate all prime implicants of a functionnn Select those prime implicants that contain at least Select those prime implicants that contain at least
one 1 that is not covered by any other prime one 1 that is not covered by any other prime implicant.implicant.
nn For the previous example, the PIs are b’, ad, For the previous example, the PIs are b’, ad, and a’cd’; all of these are essential.and a’cd’; all of these are essential.
11111111111
b’ad
a’cd’
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 15
19-Mar-10 57Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Another ExampleAnother Examplenn Consider fConsider f22(a,b,c,d), whose K(a,b,c,d), whose K--map map
is shown below.is shown below.nn The only essential PI is The only essential PI is b’db’d..
11
11 11 11
11 11
11 11 11
cdab
19-Mar-10 58Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Systematic Procedure for Systematic Procedure for Simplifying Boolean FunctionsSimplifying Boolean Functions1.1. Generate Generate allall PIs of the function.PIs of the function.2.2. Include all essential PIs.Include all essential PIs.3.3. For remaining minterms not included in For remaining minterms not included in
the essential PIs, select a set of other the essential PIs, select a set of other PIs to cover them, with minimal PIs to cover them, with minimal overlap in the set.overlap in the set.
4.4. The resulting simplified function is the The resulting simplified function is the logical logical OROR of the product terms of the product terms selected above.selected above.
19-Mar-10 59Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
ExampleExample
nn f(a,b,c,d) = f(a,b,c,d) = ∑∑m(0,1,2,3,4,5,7,14,15).m(0,1,2,3,4,5,7,14,15).
nn Five grouped terms, not all Five grouped terms, not all needed.needed.
nn 3 shaded cells covered by only 3 shaded cells covered by only one termone term
nn 3 EPIs, since each shaded cell 3 EPIs, since each shaded cell is covered by a different term.is covered by a different term.
nn F(a,b,c,d) = a’b’ + a’c’ + a’d + abcF(a,b,c,d) = a’b’ + a’c’ + a’d + abc
11
111
1111ab
cd
19-Mar-10 60Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Product of Sums SimplificationProduct of Sums Simplificationnn Use sumUse sum--ofof--products simplification on products simplification on
the the zeroszeros of the function in the Kof the function in the K--map map to get F’.to get F’.
nn Find the complement of F’, i.e. (F’)’ = FFind the complement of F’, i.e. (F’)’ = Fnn Recall that the complement of a boolean Recall that the complement of a boolean
function can be obtained by (1) taking the function can be obtained by (1) taking the dual and (2) complementing each literal.dual and (2) complementing each literal.
nn OR, using DeMorgan’s Theorem.OR, using DeMorgan’s Theorem.
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 16
19-Mar-10 61Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
POS ExamplePOS Example
0000
1100
0111
1111ab
cd
• F’(a,b,c,d) = ab’ + ac’ + a’bcd’• Find dual of F’, dual(F’) = (a+b’)(a+c’)(a’+b+c+d’)• Complement of literals in dual(F’) to get F
F = (a’+b)(a’+c)(a+b’+c’+d) (verify that this is the same as in slide 60)
19-Mar-10 62Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Don't Care ConditionsDon't Care Conditionsnn There may be a combination of input values whichThere may be a combination of input values which
nn will will never never occuroccurnn if they do occur, the output is of no concern.if they do occur, the output is of no concern.
nn The function value for such combinations is called The function value for such combinations is called a a don't caredon't care..
nn They are usually denoted with They are usually denoted with xx. Each . Each xx may be may be arbitrarily assigned the value 0 or 1 in an arbitrarily assigned the value 0 or 1 in an implementation.implementation.
nn Don’t cares can be used to Don’t cares can be used to furtherfurther simplify a simplify a functionfunction
19-Mar-10 63Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Minimization using Don’t CaresMinimization using Don’t Cares
nn Treat don't cares as if they are 1s to Treat don't cares as if they are 1s to generate PIs.generate PIs.
nn Delete PI's that cover only don't care Delete PI's that cover only don't care minterms.minterms.
nn Treat the covering of remaining don't Treat the covering of remaining don't care minterms as optional in the care minterms as optional in the selection process (selection process (i.e.i.e. they may be, but they may be, but need not be, covered).need not be, covered).
19-Mar-10 64Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
ExampleExamplenn Simplify the function f(a,b,c,d) Simplify the function f(a,b,c,d)
whose Kwhose K--map is shown at the right.map is shown at the right.nn f = a’c’d+ab’+cd’+a’bc’ f = a’c’d+ab’+cd’+a’bc’
orornn f = a’c’d+ab’+cd’+a’bd’f = a’c’d+ab’+cd’+a’bd’nn The middle two terms are EPIs, while The middle two terms are EPIs, while
the first and last terms are selected the first and last terms are selected totocover the minterms mcover the minterms m11, m, m44, and m, and m55..
nn (There’s a third solution!)(There’s a third solution!)
xx11xx0010111010
xx11xx0010111010
00 11 00 1111 11 00 1100 00 xx xx11 11 xx xx
abcd
000111 10
00 01 11 10
CSE221: Logic Design, Spring 2003 19-Mar-10
Chapter 2-i: Combinational Logic Circuits (Sections 2.1-- 2.5) 17
19-Mar-10 65Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Another ExampleAnother Examplenn Simplify the function Simplify the function
g(a,b,c,d) whose Kg(a,b,c,d) whose K--map map is shown at right.is shown at right.
nn g = a’c’+ abg = a’c’+ aboror
nn g = a’c’+b’dg = a’c’+b’d
xx 11 00 0011 xx 00 xx11 xx xx 1100 xx xx 00
xx 11 00 0011 xx 00 xx11 xx xx 1100 xx xx 00
xx 11 00 0011 xx 00 xx11 xx xx 1100 xx xx 00
abcd
19-Mar-10 66Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
Algorithmic minimizationAlgorithmic minimization
nn What do we do for functions with more What do we do for functions with more than 4than 4--5 variables?5 variables?
nn You can “code up” a minimiser You can “code up” a minimiser (Computer(Computer--Aided Design, CAD)Aided Design, CAD)nn QuineQuine--McCluskey algorithmMcCluskey algorithmnn Iterated consensusIterated consensus
nn We won’t discuss these techniques hereWe won’t discuss these techniques here