Chapter 9 Finite-State Machines

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Chapter 9 Finite-State Machines

Chapter 9 Finite-State Machines

Finite-state machine background Finite-state machine background Writing VHDL for a FSM Writing VHDL for a FSM FSM initializationFSM initialization FSM flipflop output signalFSM flipflop output signal FSM synthesisFSM synthesis ExerciseExercise

Slides 2-9 based on: Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

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Describing embedded system’s processing behaviorDescribing embedded system’s processing behavioro Can be extremely difficultCan be extremely difficult

Complexity increasing with increasing IC capacityComplexity increasing with increasing IC capacity Past: washing machines, small games, etc.Past: washing machines, small games, etc.

Hundreds of lines of codeHundreds of lines of code Today: TV set-top boxes, Cell phone, etc.Today: TV set-top boxes, Cell phone, etc.

Hundreds of thousands of lines of codeHundreds of thousands of lines of code Desired behavior often not fully understood in beginningDesired behavior often not fully understood in beginning

Many implementation bugs due to description Many implementation bugs due to description mistakes/omissionsmistakes/omissions

o English (or other natural language) common starting pointEnglish (or other natural language) common starting point Precise description difficult to impossiblePrecise description difficult to impossible Example: Motor Vehicle Code – thousands of pages long...Example: Motor Vehicle Code – thousands of pages long...

Introduction

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An example of trying to be precise in EnglishAn example of trying to be precise in English

California Vehicle CodeCalifornia Vehicle Code Right-of-way of crosswalksRight-of-way of crosswalks

(b) The provisions of this section shall not relieve a pedestrian from the duty (b) The provisions of this section shall not relieve a pedestrian from the duty of using due care for his or her safety. No pedestrian shall suddenly leave a of using due care for his or her safety. No pedestrian shall suddenly leave a curb or other place of safety and walk or run into the path of a vehicle which curb or other place of safety and walk or run into the path of a vehicle which is so close as to constitute an immediate hazard. No pedestrian shall is so close as to constitute an immediate hazard. No pedestrian shall unnecessarily stop or delay traffic while in a marked or unmarked crosswalk.unnecessarily stop or delay traffic while in a marked or unmarked crosswalk.

21950. (a) The driver of a vehicle shall yield the right-of-way to a pedestrian 21950. (a) The driver of a vehicle shall yield the right-of-way to a pedestrian crossing the roadway within any marked crosswalk or within any unmarked crossing the roadway within any marked crosswalk or within any unmarked crosswalk at an intersection, except as otherwise provided in this chapter.crosswalk at an intersection, except as otherwise provided in this chapter.

(c) The provisions of subdivision (b) shall not relieve a driver of a vehicle (c) The provisions of subdivision (b) shall not relieve a driver of a vehicle from the duty of exercising due care for the safety of any pedestrian within from the duty of exercising due care for the safety of any pedestrian within any marked crosswalk or within any unmarked crosswalk at an intersection.any marked crosswalk or within any unmarked crosswalk at an intersection.

All that just for crossing the street (and there’s much more)!All that just for crossing the street (and there’s much more)! How can we (precisely) capture behavior?How can we (precisely) capture behavior?

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Introductory example: An elevator controllerIntroductory example: An elevator controller

Simple elevator Simple elevator controllercontroller Request ResolverRequest Resolver

resolves various floor resolves various floor requests into single requests into single requested floorrequested floor

Unit ControlUnit Control moves moves elevator to this elevator to this requested floorrequested floor

“Move the elevator either up or down to reach the requested floor. Once at the requested floor, open the door for at least 10 seconds, and keep it open until the requested floor changes. Ensure the door is never open while moving. Don’t change directions unless there are no higher requests when moving up or no lower requests when moving down…”

Partial English description

buttonsinside

elevator

UnitControl

b1

down

open

floor

...

RequestResolver

...

up/downbuttons on each

floor

b2

bN

up1

up2

dn2

dnN

req

up

System interface

up3

dn3

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Finite-state machine (FSM) modelFinite-state machine (FSM) model

Trying to capture this behavior as sequential program is a bit Trying to capture this behavior as sequential program is a bit awkwardawkward

Instead, we might consider an FSM model, describing the system Instead, we might consider an FSM model, describing the system as:as: Possible statesPossible states

E.g., E.g., IdleIdle, , GoingUpGoingUp, , GoingDnGoingDn, , DoorOpenDoorOpen Possible transitions from one state to another based on inputPossible transitions from one state to another based on input

E.g., req > floorE.g., req > floor Actions that occur in each stateActions that occur in each state

E.g., In the E.g., In the GoingUpGoingUp state, u,d,o,t = 1,0,0,0 (up = 1, down, open, and timer_start = state, u,d,o,t = 1,0,0,0 (up = 1, down, open, and timer_start = 0)0)

Try it...Try it...

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Finite-state machine (FSM) modelFinite-state machine (FSM) model

Idle

GoingUp

req > floor

req < floor

!(req > floor)

!(timer < 10)

req < floor

DoorOpen

GoingDn

req > floor

u,d,o, t = 1,0,0,0

u,d,o,t = 0,0,1,0

u,d,o,t = 0,1,0,0

u,d,o,t = 0,0,1,1

u is up, d is down, o is open

req == floor

!(req<floor)

timer < 10

t is timer_start

UnitControl process using a state machine

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An FSM is a 6-tuple An FSM is a 6-tuple FF<<SS, , II, , OO, , FF, , HH, , ss00>> SS is a set of all states { is a set of all states {ss00, , ss11, …, , …, ssll}} II is a set of inputs { is a set of inputs {ii00, , ii11, …, , …, iimm}} OO is a set of outputs { is a set of outputs {oo00, , oo11, …, , …, oonn}} FF is a next-state function ( is a next-state function (SS x x II → → SS)) HH is an output function ( is an output function (SS → → OO)) ss00 is an initial stateis an initial state

Moore-typeMoore-type Associates outputs with states (as given above, Associates outputs with states (as given above, HH maps maps S S → → OO))

Mealy-typeMealy-type Associates outputs with transitions (Associates outputs with transitions (HH maps maps SS x x II → → OO))

Shorthand notations to simplify descriptionsShorthand notations to simplify descriptions Implicitly assign 0 to all unassigned outputs in a stateImplicitly assign 0 to all unassigned outputs in a state Implicitly AND every transition condition with clock edge (FSM is synchronous)Implicitly AND every transition condition with clock edge (FSM is synchronous)

Formal definitionFormal definition

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Formal definitionFormal definition

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Describing a system as a finite state machineDescribing a system as a finite state machine

1. List all possible states1. List all possible states2. For each state, list possible transitions, with conditions, to other states

3. For each state and/or transition, list associated actions

4. For each state, ensure exclusive and complete exiting transition conditions• No two exiting conditions can

be true at same time– Otherwise nondeterministic

state machine

• One condition must be true at any given time– Reducing explicit transitions

should be avoided when first learning

req > floor

!(req > floor) u,d,o, t = 1,0,0,0

u,d,o,t = 0,0,1,0

u,d,o,t = 0,1,0,0

u,d,o,t = 0,0,1,1

u is up, d is down, o is open

req < floor

req > floor

req == floor

req < floor

!(req<floor)

!(timer < 10)

timer < 10

t is timer_start

Idle

GoingUp

DoorOpen

GoingDn

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Writing VHDL for a FSM Writing VHDL for a FSM

Consider FSM transition diagram

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use IEEE.std_logic_1164.all;entity RWCNTL is port( CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic);end RWCNTL;

architecture RTL of RWCNTL is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;begin comb : process (CURRENT_STATE, START, RW, LAST) begin DONE <= '0'; RDSIG <= '0'; WRSIG <= '0';

Use case statement to describe the combinationalcircuit and a clock sensitive process to infer flip-flops

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case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then NEXT_STATE <= READING; else NEXT_STATE <= WAITING; end if; when WRITING => WRSIG <= '1';


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if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; NEXT_STATE <= IDLE; end case; end process;

seq : process begin wait until CLOCK'event and CLOCK = '1'; CURRENT_STATE <= NEXT_STATE; end process;end RTL;

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Writing VHDL for a FSMWriting VHDL for a FSM

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Writing VHDL for a FSMWriting VHDL for a FSM

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Performance of FSMPerformance of FSM

Similar to regular sequential circuit Similar to regular sequential circuit

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Sample timing diagram

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State assignmentState assignment

State assignment: assign binary State assignment: assign binary representations to symbolic statesrepresentations to symbolic states

In a synchronous FSMIn a synchronous FSM All assignments workAll assignments work Good assignment reduce the complexity of Good assignment reduce the complexity of

next-state/output logicnext-state/output logic Typical assignmentTypical assignment

Binary, Gray, one-hot, almost one-hotBinary, Gray, one-hot, almost one-hot

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State assignmentState assignment

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FSM initializationFSM initialization

library IEEE;use IEEE.std_logic_1164.all;entity RWCNTLR is port( RESETn : in std_logic;RESETn : in std_logic; CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic);end RWCNTLR;

architecture RTL of RWCNTLR is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;begin comb : process(CURRENT_STATE, START, RW, LAST) begin DONE <= '0'; RDSIG <= '0'; WRSIG <= '0';

To asynchronously reset FSM add if statement which includes elseif with rising edge of the clock

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case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then NEXT_STATE <= READING; else NEXT_STATE <= WAITING; end if; when WRITING =>

WRSIG <= '1';

if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; NEXT_STATE <= IDLE; end case;end process;seq : process (CLOCK, RESETn) begin if (RESETn = '0') then CURRENT_STATE <= IDLE; elsif (CLOCK'event and CLOCK = '1') then CURRENT_STATE <= NEXT_STATE; end if; end process;end RTL;

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library IEEE;use IEEE.std_logic_1164.all;entity RWCNTLR1 is port( RESETn : in std_logic; CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic);end RWCNTLR1;

architecture RTL of RWCNTLR1 is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;begin comb : process(RESETn, CURRENT_STATE, START, RW, LAST) begin DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; if (RESETn = '0') then NEXT_STATE <= IDLE; else

To infer a synchronous reset use if statement before case statement in the combinational part

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case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then NEXT_STATE <= READING; else NEXT_STATE <= WAITING; end if; when WRITING => WRSIG <= '1';

if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; NEXT_STATE <= IDLE; end case;end if; end process; seq : process (CLOCK, RESETn) begin if (RESETn = '0') then CURRENT_STATE <= IDLE; elsif (CLOCK'event and CLOCK = '1') then CURRENT_STATE <= NEXT_STATE; end if; end process;end RTL;

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FSM flip-flop output signalFSM flip-flop output signal

library IEEE;use IEEE.std_logic_1164.all;entity RWCNTLRF is port( RESETn : in std_logic; CLOCK : in std_logic; START : in std_logic; RW : in std_logic; LAST : in std_logic; RDSIG : out std_logic; WRSIG : out std_logic; DONE : out std_logic);end RWCNTLRF;

architecture RTL of RWCNTLRF is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; signal DONE_comb, RDSIG_comb, WRSIG_comb : std_logic;begin comb : process(CURRENT_STATE, START, RW, LAST) begin DONE_comb <= '0'; RDSIG_comb <= '0'; WRSIG_comb <= '0';

To have outputs driven by flip-flops use output signal assignment in the process under rising edge of the clock

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FSM flip-flop output signalFSM flip-flop output signal

if LAST = '0' then NEXT_STATE <= WRITING; else NEXT_STATE <= WAITING; end if; when WAITING => DONE_comb <= '1'; NEXT_STATE <= IDLE; end case; end process; seq : process (CLOCK, RESETn) begin if (RESETn = '0') then CURRENT_STATE <= IDLE; DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; elsif (CLOCK'event and CLOCK = '1') then CURRENT_STATE <= NEXT_STATE; DONE <= DONE_comb;

case CURRENT_STATE is when IDLE => if START = '0' then NEXT_STATE <= IDLE; elsif RW = '1' then NEXT_STATE <= READING; else NEXT_STATE <= WRITING; end if; when READING => RDSIG_comb <= '1'; if LAST = '0' then NEXT_STATE <= READING; else NEXT_STATE <= WAITING; end if; when WRITING => WRSIG_comb <= '1';

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FSM flipflop output signalFSM flipflop output signal

RDSIG <= RDSIG_comb; WRSIG <= WRSIG_comb; end if; end process;end RTL;

Note that synthesized circuit has 3 more latches

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Comparing to the original design the output signals are latched at the next clock edge

Comparing to the original design the output signals are latched at the next clock edge

Note that synthesized circuit has 3 more latches

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if (RESETn = '0') then CURRENT_STATE <= IDLE; DONE <= '0'; RDSIG <= '0'; WRSIG <= '0'; elsif (CLOCK'event and CLOCK = '1') then DONE <= '0'; RDSIG <= '0'; WRSIG <= '0';

architecture COMBINED of RWCNTLRF is type STATE_TYPE is (IDLE, READING, WRITING, WAITING); signal CURRENT_STATE : STATE_TYPE;begin seq : process (CLOCK, RESETn) begin

This code can be simplified if the case statement is included inside if statement in the seq process

temporary signals are avoided and simulation runs faster

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case CURRENT_STATE is when IDLE => if START = '0' then CURRENT_STATE <= IDLE; elsif RW = '1' then CURRENT_STATE <= READING; else CURRENT_STATE <= WRITING; end if; when READING => RDSIG <= '1'; if LAST = '0' then CURRENT_STATE <= READING; else CURRENT_STATE <= WAITING; end if;

when WRITING => WRSIG <= '1'; if LAST = '0' then CURRENT_STATE <= WRITING; else CURRENT_STATE <= WAITING; end if; when WAITING => DONE <= '1'; CURRENT_STATE <= IDLE; end case; end if; end process;end COMBINED;

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FSM synthesisFSM synthesis Some synthesis tools can synthesize the FSMs. They usually generate better results than a general

synthesis from VHDL code. It is better for an FSM to be an independent block

(VHDL code). This makes the synthesis process easier, especially

in writing synthesis constraints, encoding states, and synthesis commands.

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To Create a State Diagram To Create a State Diagram

Select Select New SourceNew Source on the on the ProjectProject menu. menu. Select Select State DiagramState Diagram from the list in the dialog box. from the list in the dialog box. Enter a name for the new state diagram. Enter a name for the new state diagram. Enter a directory in which the state diagram will reside.Enter a directory in which the state diagram will reside. Click Click NextNext. . Click Click FinishFinish. The StateCAD program displays. . The StateCAD program displays. Select Select Design WizardDesign Wizard on the on the FileFile menu in StateCAD. Click menu in StateCAD. Click

Save FileSave File Click the Click the Generate HDLGenerate HDL button. button. Close StateCAD. Close StateCAD. Click Click Add SourceAdd Source on the on the ProjectProject menu to add the state menu to add the state

diagram .dia file and the HDL module to your ISE project.diagram .dia file and the HDL module to your ISE project.

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FSMFSM

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FSMFSM

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FSMFSM

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Synthesized FSMSynthesized FSM

------ File: D:\FDNTN\ACTIVE\PROJECTS\FSM\fsm1.vhd-- File: D:\FDNTN\ACTIVE\PROJECTS\FSM\fsm1.vhd-- created: 10/25/99 23:08:10-- created: 10/25/99 23:08:10-- from: 'D:\FDNTN\ACTIVE\PROJECTS\FSM\fsm1.asf'-- from: 'D:\FDNTN\ACTIVE\PROJECTS\FSM\fsm1.asf'-- by fsm2hdl - version: 2.0.1.52-- by fsm2hdl - version: 2.0.1.52----library IEEE;library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;use IEEE.std_logic_unsigned.all;

library SYNOPSYS;library SYNOPSYS;use SYNOPSYS.attributes.all;use SYNOPSYS.attributes.all;

entity fsm1 is entity fsm1 is port (clock: in STD_LOGIC;port (clock: in STD_LOGIC; last: in STD_LOGIC;last: in STD_LOGIC; rw: in STD_LOGIC;rw: in STD_LOGIC; start: in STD_LOGIC;start: in STD_LOGIC; done: out STD_LOGIC;done: out STD_LOGIC; rdsig: out STD_LOGIC;rdsig: out STD_LOGIC; wrsig: out STD_LOGIC);wrsig: out STD_LOGIC);end;end;

architecture fsm1_arch of fsm1 is-- SYMBOLIC ENCODED state machine: Sreg0type Sreg0_type is (idle, reading, waiting, writing);signal Sreg0: Sreg0_type;begin--concurrent signal assignments--diagram ACTIONS;Sreg0_machine: process (clock)beginif clock'event and clock = '1' thencase Sreg0 is

when idle =>if rw='0' then

Sreg0 <= writing;elsif start='0' then

Sreg0 <= idle;elsif rw='1' then

Sreg0 <= reading;end if;

when reading =>if last='0' then

Sreg0 <= reading;elsif last='1' then

Sreg0 <= waiting;end if;

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Synthesized FSMSynthesized FSM

when waiting =>Sreg0 <= idle;

when writing =>if last='0' then

Sreg0 <= writing;elsif last='1' then

Sreg0 <= waiting;end if;

when others =>null;

end case;end if;end process;

-- signal assignment statements for combinatorial outputsrdsig_assignment:rdsig <= '1' when (Sreg0 = reading and last='0') else '1' when (Sreg0 = reading and last='1') else '1';

done_assignment:done <= '1' when (Sreg0 = waiting) else '1';

wrsig_assignment:wrsig <= '1' when (Sreg0 = writing and last='0') else '1' when (Sreg0 = writing and last='1') else '1';

end fsm1_arch;

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StateCADStateCAD

Translates state diagrams to HDL based designsTranslates state diagrams to HDL based designs Automatically analyzes designs for problems such asAutomatically analyzes designs for problems such as

Stuck-at statesStuck-at states Conflicting state assignmentsConflicting state assignments Indeterminate conditionsIndeterminate conditions

Includes Includes StateBenchStateBench

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StateCADStateCAD

Support concurrent Support concurrent state machinesstate machines

Graphical operators Graphical operators for states for states

Mealy & Moore outputsMealy & Moore outputs ResetsResets Combinatorial and Combinatorial and

synchronous logicsynchronous logic Text commentsText comments

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FSM Wizard in StateCADFSM Wizard in StateCAD

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Logic Wizard in StateCADLogic Wizard in StateCAD

StateCAD Logic Wizard StateCAD Logic Wizard for data flow structures for data flow structures Shifters, registers,latches, Shifters, registers,latches,

counters, muxes, etc. counters, muxes, etc. Requires object type, Requires object type,

attributes, and attributes, and signal names signal names

Handles boolean Handles boolean equations within the wizard equations within the wizard

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OverviewOverview

StateCAD diagrams have .dia extensionsStateCAD diagrams have .dia extensions File names have an eight character limitFile names have an eight character limit

StateCAD outputStateCAD output Language specific filesLanguage specific files

VHDL, Verilog, or ABELVHDL, Verilog, or ABEL VHDL and Verilog output files can be compiled VHDL and Verilog output files can be compiled

using various toolsusing various tools ExemplarExemplar SynopsysSynopsys

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Beginning a DiagramBeginning a Diagram

Project Project New Source New Source State DiagramState Diagram File NameFile Name

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Adding StatesAdding States

In the Draw Mode tool bar, In the Draw Mode tool bar, use the State Mode command use the State Mode command

States are given unique names when they are added or copiedStates are given unique names when they are added or copied May be used as actual state namesMay be used as actual state names Can be changed or editedCan be changed or edited

Syntax of states:Syntax of states:

NAME_ONLY NAMEOUTPUTS=1;

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OutputsOutputs

Output list contains equationsOutput list contains equations Output equationsOutput equations State variablesState variables

Outputs support complex data flow logicOutputs support complex data flow logic Bit or vector equationsBit or vector equations CountersCounters MuxesMuxes

Example:Example:NAME

CNTR <= CNTR + 1;BUSOUT = (sigA OR sigB) AND NOT(sigC OR sigD)

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OutputsOutputs

Output Wizard is the Output Wizard is the easiest way to add outputs easiest way to add outputs In Edit State (double-click In Edit State (double-click

on a state), select the on a state), select the Output Wizard button Output Wizard button

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TransitionsTransitions

Use the Transition button to draw curved and straight Use the Transition button to draw curved and straight transitions:transitions: Straight transitions: Click on one state, then click on another stateStraight transitions: Click on one state, then click on another state Curved transitions: Curved transitions:

Click on one state Click on one state (a small square (a small square appears), another appears), another small square will small square will follow the cursor (click to place), one more square will appear, place follow the cursor (click to place), one more square will appear, place the final square on the state destination the final square on the state destination

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Curved TransitionsCurved Transitions

Multiple segment Multiple segment transitions transitions Enable through Enable through

Options menu Options menu Graphics Graphics

Deselect “Single Segment Curve”Deselect “Single Segment Curve” Unlimited number of segmentsUnlimited number of segments Each segment contains a starting point, two Each segment contains a starting point, two

control points, and an endpointcontrol points, and an endpoint

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Transition ConditionsTransition Conditions

To add a transition condition, double-click on the To add a transition condition, double-click on the transition for the Edit Condition dialog boxtransition for the Edit Condition dialog box

Conditions are Boolean equationsConditions are Boolean equations Syntax errors and indeterminate conditions are checked Syntax errors and indeterminate conditions are checked

during compilationduring compilation

Conditions may use inputs, outputs, and logic Conditions may use inputs, outputs, and logic variablesvariables State names and variables from one machine may be State names and variables from one machine may be

used in the condition of another machine. This allows used in the condition of another machine. This allows communication between state machinescommunication between state machines

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ResetReset

Reset is taken from any state, when its Reset is taken from any state, when its condition is truecondition is true

One synchronous and one asynchronous reset One synchronous and one asynchronous reset are allowed per state machineare allowed per state machine

Reset condition should not contain variables Reset condition should not contain variables used in any other transition of the state machineused in any other transition of the state machine Reset overrides the state transition conditionsReset overrides the state transition conditions

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ResetReset

Use the Reset Mode command:Use the Reset Mode command:

Click on an empty region for your start pointClick on an empty region for your start point Click on the desired reset stateClick on the desired reset state You will automatically be asked to select the You will automatically be asked to select the

mode (asynchronous or synchronous)mode (asynchronous or synchronous) The condition is automatically added (Reset) The condition is automatically added (Reset)

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Text and CommentsText and Comments

To add text and comments to state diagrams, To add text and comments to state diagrams, use the Text Mode: use the Text Mode:

Enter text here

Add as comments to HDL code

Make attributesvisible

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Text and CommentsText and Comments Test vectors added into the HDL and included files can Test vectors added into the HDL and included files can

be referenced by including text in HDLbe referenced by including text in HDL

Language specific logic not supported by StateCAD Language specific logic not supported by StateCAD may be implementedmay be implemented

Caution: When adding comments in HDL, text lines Caution: When adding comments in HDL, text lines may be broken by StateCAD, and the new line will may be broken by StateCAD, and the new line will begin without a comment marker in HDLbegin without a comment marker in HDL

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WizardsWizards

FSM Wizard or FSM Wizard or Allows you to quickly create basic state machines Allows you to quickly create basic state machines

Optimization Wizard orOptimization Wizard or Collects information on design goals and target devices, to Collects information on design goals and target devices, to

provide optimized results for speed, area, gate count, etc.provide optimized results for speed, area, gate count, etc. Optimizes code for target device AND synthesis toolOptimizes code for target device AND synthesis tool

Design WizardDesign Wizard Combines FSM Wizard and Optimization Wizard into oneCombines FSM Wizard and Optimization Wizard into one Only available through the Wizard Toolbar (Window Only available through the Wizard Toolbar (Window Wizard Wizard

Toolbar)Toolbar)

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WizardsWizards

Logic Wizard orLogic Wizard or Develops data flow logicDevelops data flow logic Supports counters, muxes, Supports counters, muxes,

shifters, latches, and gates shifters, latches, and gates

Wizard ToolbarWizard Toolbar

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CompilationCompilation

Compilation translates state Compilation translates state diagrams into HDLdiagrams into HDL Automatic error checking, Automatic error checking,

logic minimization, logic minimization, state state assignmentsassignments

Performs syntax check, Performs syntax check, language problems, language problems, and design and design problemsproblems

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Compiler Configuration OptionsCompiler Configuration Options Access Configurations Access Configurations

options through options through the menu bar:the menu bar: Options Options

ConfigurationConfiguration OptionsOptions

Delete unread Delete unread variablesvariables

Retain output Retain output valuesvalues

Implied elseImplied else LanguageLanguage

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Compiler Configuration OptionsCompiler Configuration Options

Check optionsCheck options Indeterminate Indeterminate

transitionstransitions Conflicting Conflicting

State State assignmentsassignments

State State AssignmentsAssignments

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SummarySummary

State diagrams can be translated into VHDL, Verilog, or State diagrams can be translated into VHDL, Verilog, or ABELABEL

Numerous toolbars are available to aid in your diagram Numerous toolbars are available to aid in your diagram designdesign

States and state transitions are easily added through States and state transitions are easily added through buttons in the Draw Mode Toolbarbuttons in the Draw Mode Toolbar

The Output Wizard gives access to the Logic Wizard, so The Output Wizard gives access to the Logic Wizard, so you can easily add output equations or conditions to any you can easily add output equations or conditions to any state or transitionstate or transition

Designs are compiled and translated with a simple push Designs are compiled and translated with a simple push buttonbutton

Chapter 9 Finite-State Machines

Documents

Transcript of Chapter 9 Finite-State Machines