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Transcript of Chapter 8 External Memory Interface (EMIF). Dr. Naim Dahnoun, Bristol University, (c) Texas...
Chapter 8Chapter 8
External Memory Interface External Memory Interface (EMIF)(EMIF)
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 2
Learning ObjectivesLearning Objectives
The need for an External Memory Interface The need for an External Memory Interface (EMIF).(EMIF).
Memory types.Memory types. C6211/C6711 memory map.C6211/C6711 memory map. C6211/C6711 EMIF features and signals.C6211/C6711 EMIF features and signals. Memory space control registers.Memory space control registers. Asynchronous interface (A/D & D/A).Asynchronous interface (A/D & D/A). Internal Timer.Internal Timer. Application notes: Application notes: SRAMSRAM, , SBSRAM, SBSRAM, SDRAMSDRAM
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 3
Need for an EMIFNeed for an EMIF
Traditional DSP (with no EMIF):Traditional DSP (with no EMIF):
Peripheral/Peripheral/MemoryMemory
H/W H/W InterfaceInterface DSPDSP
When interfacing a slow peripheral/memory to a fast DSP, some hardware interface is required.When interfacing a slow peripheral/memory to a fast DSP, some hardware interface is required. This hardware interface requires fast components in order to keep up with the DSP.This hardware interface requires fast components in order to keep up with the DSP.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 4
Need for an EMIFNeed for an EMIF
Traditional DSP (with no EMIF):Traditional DSP (with no EMIF):
Peripheral/Peripheral/MemoryMemory
H/W H/W InterfaceInterface DSPDSP
Drawback of the hardware interface:Drawback of the hardware interface: High cost (additional components).High cost (additional components). Power consumption.Power consumption. Difficult to debug.Difficult to debug. Cannot be upgraded.Cannot be upgraded. Prone to errors.Prone to errors.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 5
The EMIFThe EMIF The EMIF supports a The EMIF supports a glueless interface glueless interface to several external devices, including:to several external devices, including:
Synchronous burst SRAM (SBSRAM).Synchronous burst SRAM (SBSRAM). Synchronous DRAM (SDRAM).Synchronous DRAM (SDRAM). Asynchronous devices, including SRAM, ROM and FIFO’s.Asynchronous devices, including SRAM, ROM and FIFO’s. An external shared-memory device.An external shared-memory device.
For more information on different memory types see For more information on different memory types see Links\Links\SPRA631.pdfSPRA631.pdf..
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 6
The EMIFThe EMIF
The C621x/C671x services requests of the external bus from the requestors:The C621x/C671x services requests of the external bus from the requestors: On-chip Enhanced Direct Memory Access (EDMA) controller.On-chip Enhanced Direct Memory Access (EDMA) controller. External shared-memory device controller.External shared-memory device controller.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 7
The EMIFThe EMIF
C6000 DSP core
Data Path A
EMIF
OtherPeripherals
InterruptSelector
PowerDownLogic
BootConfiguration
EnhancedDMA
Controller
PLL
L2Memory
L1P Cache
L2D Cache
Instruction Fetch
Instruction Dispatch
Instruction Decode
A Register File
D1S1 M1L1
Data Path B
B Register File
D2S2 M2L2
ControlRegisters
ControlLogic
Test
In-CircuitEmulation
InterruptControl
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 8
C6211/C6711 EMIF FeaturesC6211/C6711 EMIF Features
Features C621x / C671x
Bus Width 32
# Memory Spaces 4
Addressable Space (Mbytes) 512
Synchronous Clocking Independent ECLKIN
Width Support 8/16/32
Supported Memory Type at CE1 All types
Control Signals Mixed all control signals
Synchronous memory in system Both SDRAM and SBSRAM
Additional registers SDEXT
PDT Support No
ROM/Flash Yes
Asynchronous memory I/O Yes
Pipeline SBSRAM Yes
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 9
C6211/C6711 EMIF SignalsC6211/C6711 EMIF Signals
For a description of the signals see: \Links\signals.pdfFor a description of the signals see: \Links\signals.pdf
ExternalMemoryInterface
Enhanceddata
memorycontroller
InternalPeripheral bus
ECLKIN
ECLKOUT
ED[31:0]'
EA[21:2]'
CE[3:0]
BE[3:0]
ARDY
(AOE')/ (SDRAS') / (SSOE')
(ARE') / SDCAS') (SSADS')
(AWE') / (SDWE') / (SSWE')
HOLD'
HOLDA'
BUSREQControl
Registers
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 10
C6211/C6711 EMIF ConfigurationC6211/C6711 EMIF Configuration
The following need to be configured when interfacing the DSP to an The following need to be configured when interfacing the DSP to an external device using the EMIF:external device using the EMIF:
(1) Memory space control registers (software):(1) Memory space control registers (software):These registers describe the type and timing of the external memory to be used.These registers describe the type and timing of the external memory to be used.
(2)(2) EMIF chip enable (hardware):EMIF chip enable (hardware):There are four chip enable (CE0, CE1, CE2 and CE3) that are used when accessing a specific memory location (e.g. if you try to access memory 0x9000 0000 then CE1 will be activated, see next slide).There are four chip enable (CE0, CE1, CE2 and CE3) that are used when accessing a specific memory location (e.g. if you try to access memory 0x9000 0000 then CE1 will be activated, see next slide).
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 11
C6211/C6711 EMIF Memory SpacesC6211/C6711 EMIF Memory SpacesMemory Block Description Block Size (Bytes) HEX Address Range
Internal RAM (L2) 64K 0000 0000 - 0000 FFFF
Reserved 24M-64K 0001 0000 - 017F FFFF
EMIF Registers 256k 0180 0000 - 0183 FFFF
L2 Registers 256k 0184 0000 - 0187 FFFF
HPI Registers 256k 0188 0000 - 018B FFFF
McBSP 0 Registers 256k 018C 0000 - 018F FFFF
McBSP 1 Registers 256k 0190 0000 - 0193 FFFF
Timer 0 Registers 256k 0194 0000 - 0197 FFFF
Timer 1 Registers 256k 0198 0000 - 019B FFFF
Interrupt selector Registers 256k 019C 0000 - 019F FFFF
EDMA RAM and EDMA Registers 256k 01A0 0000 - 01A3 FFFF
Reserved 64M-256k 01A4 0000 - 01FF FFFF
QDMA Registers 52 0200 0000 - 0200 FFFF
Reserved 736M-52 0200 0034 - 2FFF FFFF
MCBSP 0/1 Data 256M 3000 0000 - 3FFF FFFF
Reserved 1G 4000 0000 - 7FFF FFFF
EMIF CE0 256M 8000 0000 - 8FFF FFFF
EMIF CE1 256M 9000 0000 - 9FFF FFFF
EMIF CE2 256M A000 0000 - AFFF FFFF
EMIF CE3 256M B000 0000 - BFFF FFFF
Reserved 1G C000 0000 - FFFF FFFF
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 12
Memory Space Control RegistersMemory Space Control Registers
0000_00000000_0000
0180_00000180_0000
Memory MapMemory Map
PeripheralsPeripherals
Space Control Registers
CE1 ControlCE1 Control
CE3 ControlCE3 Control
CE0 ControlCE0 Control
CE2 ControlCE2 Control
Global ControlGlobal Control
SDRAM Refresh PrdSDRAM Refresh Prd
SDRAMSDRAM ControlControl
180_0004180_0004
180_0014180_0014
180_0008180_0008
180_0010180_0010
180_001C180_001C180_0018180_0018
180_0000180_0000
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 13
C6211/C6711 EMIF RegistersC6211/C6711 EMIF Registers
Global Control (Global Control (GBLCTLGBLCTL): the EMIF global control register configures ): the EMIF global control register configures parameters that are common to all the CE spaces.parameters that are common to all the CE spaces.
Rsv Rsv Rsv Rsv BUSREQ ARDY HOLD HOLDANO
HOLD Rsv Rsv CLK1EN CLK2EN Rsv Rsv Rsv
Rsv
31 16
15 14 13 23456789101112 1 0
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 14
C6211/C6711 EMIF RegistersC6211/C6711 EMIF Registers
Question: Why do we need different spaces?Question: Why do we need different spaces?
CE0, CE1, CE2, CE3 space control registers (CE0, CE1, CE2, CE3 space control registers (CECTLCECTL): are used to specify the ): are used to specify the type and the read and write timing used for a particular space.type and the read and write timing used for a particular space.
Answer:Answer: Different spaces allow different types of devices to be used at the Different spaces allow different types of devices to be used at the same time.same time.
TA Read Strobe MTYPE WRITEHOLD
ReadHold
15 14 13 23478 0
Write Setup Write Strobe Write Hold Read Setup
31 192021222728 16
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 15
EMIF Case StudyEMIF Case Study
DSK interface to:DSK interface to: AD768 DAC.AD768 DAC. AD9220 ADC.AD9220 ADC.
DSKDSKEEMMIIFF
AD9220 AD9220 ADCADC
AD9220 AD9220 ADCADC
AD768 AD768 DACDAC
AD768 AD768 DACDAC
Channel 1Channel 1
Channel 2Channel 2
Channel 1Channel 1
Channel 2Channel 2
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 16
EMIF Case Study: AD768 DACEMIF Case Study: AD768 DAC
Specification:Specification:
AD768 data sheetAD768 data sheet
FEATURES:FEATURES:30 msps Update Rate30 msps Update Rate16-Bit Resolution16-Bit ResolutionLinearity: Linearity: 1/2 LSB DNL @ 14 Bits1/2 LSB DNL @ 14 Bits
1 LSB INL @ 14 Bits1 LSB INL @ 14 BitsFast Settling: 25ns Full-Scale Settling to 0.025%Fast Settling: 25ns Full-Scale Settling to 0.025%SFDR @ 1 MHZ Output: 86 dBcSFDR @ 1 MHZ Output: 86 dBcTHD @ 1 MHZ Output: 71 dBcTHD @ 1 MHZ Output: 71 dBcLow Glitch Impulse: 35 pV-sLow Glitch Impulse: 35 pV-sPower Dissipation: 465 mWPower Dissipation: 465 mWOn-chip 2.5V referenceOn-chip 2.5V referenceEdge Triggered LatchesEdge Triggered LatchesMultiplying Reference CapabilityMultiplying Reference Capability
APPLICATIONS:APPLICATIONS:Arbitrary Waveform GenerationArbitrary Waveform GenerationCommunications Waveform ReconstructionCommunications Waveform ReconstructionVector Stroke DisplayVector Stroke Display
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 17
EMIF Case Study: AD768 DACEMIF Case Study: AD768 DAC
Functional Block Diagram:Functional Block Diagram:
AD768 data sheetAD768 data sheet
LSBs: CURRENT SOURCES, SWITCHES, AND 12k R-2R LADDERS
MSBs: SEGMENTED CURRENT SOURCES AND SWITCHES
CONTROLAMP
2.5 vBANDGAP
REFERENCE
MSBDECODERand EDGE-
TRIGGEREDBIT
LATCHES
DB0 (LSB)
DB15 (MSB)
DCOM VDD
AD768
1K1K
VEE
LADCOM
INOUTB
INOUTA
NRIREFINREFOUTREFCOMNCCLOCK
FUNCTIONAL BLOCK DIAGRAM
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 18
EMIF Case Study: AD768 DACEMIF Case Study: AD768 DAC
Timing:Timing:
AD768 data sheetAD768 data sheet
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 19
EMIF Case Study: AD768 DACEMIF Case Study: AD768 DAC
C6711 Asynchronous Write Timing:C6711 Asynchronous Write Timing:
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 20
Setting Async TimingSetting Async Timing
000b = 8-bit-wide ROM000b = 8-bit-wide ROM001b = 16-bit-wide ROM001b = 16-bit-wide ROM010b = 32-bit-wide Async010b = 32-bit-wide Async011b = 32-bit-wide SDRAM011b = 32-bit-wide SDRAM100b = 32-bit-wide SBSRAM100b = 32-bit-wide SBSRAM
Set CE3 and to 32-bit ASYNCSet CE3 and to 32-bit ASYNCCE3CE3 .equ.equ 1800014h1800014h
mvkl.s1mvkl.s1 CE3, A0CE3, A0mvkh.s1mvkh.s1 CE3, A0CE3, A0ldwldw *A0, A1*A0, A1nop 4nop 4andand A1, 0xff0f, A1A1, 0xff0f, A1setset A1, 5, 5, A1A1, 5, 5, A1stw .d1stw .d1 A1, *A0A1, *A0
Read SetupRead Setup WriteWriteHoldHold Write StrobeWrite Strobe Write SetupWrite Setup
3131 2828 2727 2222 2121 20 20 19 19 1616
ReadReadHoldHold
Write Hold Write Hold MSBMSBMTYPEMTYPETATA Read StrobeRead Strobe
1515 1414 1313 88 77 44 33 22 00
RW, + 111111 RW, + 111111 RW, +0010RW, +0010 RW, +0RW, +0 RW, +11RW, +11
RW, +1111RW, +1111 RW, +111111RW, +111111 RW, +11RW, +11 RW, +1111RW, +1111
Note: There are more Note: There are more MTYPE options. See: \MTYPE options. See: \Links\spru190d.pdfLinks\spru190d.pdf
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 21
EMIF Case Study: AD768 DACEMIF Case Study: AD768 DAC
Hardware Interface:Hardware Interface:
AD768 data sheetAD768 data sheet
D/A
Da
ug
hte
rca
rd C
on
ne
cto
r
16
AnalogueOut
(Chan 2)
CLK
/XAWE
/XCE3
XD[0..15]
D/A16
AnalogueOut
(Chan 1)
CLK
XD[16..31]
AnalogueBuffering
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 22
EMIF Case Study: AD9220 ADCEMIF Case Study: AD9220 ADC
Specifications:Specifications:
AD9220 data sheetAD9220 data sheet
FEATURESFEATURESMonolithic 12-Bit A/D Converter Product FamilyMonolithic 12-Bit A/D Converter Product FamilyFamily Members Are: AD9221, AD9223, and AD9220Family Members Are: AD9221, AD9223, and AD9220Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS and 10 MSPSFlexible Sampling Rates: 1.5 MSPS, 3.0 MSPS and 10 MSPSLow Power Dissipation: 59 mW, 100 mW and 250 mWLow Power Dissipation: 59 mW, 100 mW and 250 mWSingle +5V SupplySingle +5V SupplyIntegral Nonlinearity Error: 0.5 LSBIntegral Nonlinearity Error: 0.5 LSBDifferential Nonlinearity Error: 0.3 LSBDifferential Nonlinearity Error: 0.3 LSBInput Referred Noise: 0.09LSBInput Referred Noise: 0.09LSBComplete On-Chip Sample-and-Hold Amplifier and Complete On-Chip Sample-and-Hold Amplifier and
Voltage ReferenceVoltage ReferenceSignal-to-Noise and Distortion Ratio: 70dBSignal-to-Noise and Distortion Ratio: 70dBSpurious-Free Dynamic Range: 86dBSpurious-Free Dynamic Range: 86dBOut-of-range IndicatorOut-of-range IndicatorStraight Binary Output DataStraight Binary Output Data28-Lead SOIC and 28-Lead SSOP28-Lead SOIC and 28-Lead SSOP
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 23
EMIF Case Study: AD9220 ADCEMIF Case Study: AD9220 ADC
Functional Block Diagram:Functional Block Diagram:
AD9220 data sheetAD9220 data sheet
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 24
EMIF Case Study: AD9220 ADCEMIF Case Study: AD9220 ADC
Timing:Timing:
AD9220 data sheetAD9220 data sheet
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 25
EMIF Case Study: AD9220 ADCEMIF Case Study: AD9220 ADC
C6711 Asynchronous Read Timing:C6711 Asynchronous Read Timing:
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 26
Setting Async TimingSetting Async Timing
000b = 8-bit-wide ROM000b = 8-bit-wide ROM001b = 16-bit-wide ROM001b = 16-bit-wide ROM010b = 32-bit-wide Async010b = 32-bit-wide Async011b = 32-bit-wide SDRAM011b = 32-bit-wide SDRAM100b = 32-bit-wide SBSRAM100b = 32-bit-wide SBSRAM
Set CE3 and to 32-bit ASYNCSet CE3 and to 32-bit ASYNCCE3CE3 .equ.equ 1800014h1800014h
mvkl.s1mvkl.s1 CE3, A0CE3, A0mvkh.s1mvkh.s1 CE3, A0CE3, A0ldwldw *A0, A1*A0, A1nop 4nop 4andand A1, 0xff0f, A1A1, 0xff0f, A1setset A1, 5, 5, A1A1, 5, 5, A1stw .d1stw .d1 A1, *A0A1, *A0
Read SetupRead Setup WriteWriteHoldHold Write StrobeWrite Strobe Write SetupWrite Setup
3131 2828 2727 2222 2121 20 20 19 19 1616
ReadReadHoldHold
Write Hold Write Hold MSBMSBMTYPEMTYPETATA Read StrobeRead Strobe
1515 1414 1313 88 77 44 33 22 00
RW, + 111111 RW, + 111111 RW, +0010RW, +0010 RW, +0RW, +0 RW, +011RW, +011
RW, +1111RW, +1111 RW, +111111RW, +111111 RW, +11RW, +11 RW, +1111RW, +1111
Note: There are more Note: There are more MTYPE options. See: \MTYPE options. See: \Links\spru190d.pdfLinks\spru190d.pdf
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 27
EMIF Case Study: AD9220 ADCEMIF Case Study: AD9220 ADC
Hardware Interface:Hardware Interface:
AD9220 data sheetAD9220 data sheet
A/D
Da
ug
hte
rca
rd C
on
ne
cto
r
16
AnalogueIn
(Chan 2)
CLK
/XAOE
/XCE3
XD[0..15]
A/D16
AnalogueIn
(Chan 1)
CLK
XD[16..31]
AnalogueBuffering
Latch
Latch
/OE
/OE
CLK
CLK
XTOUT0
16
16
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 28
EMIF Case Study: Sharing the BusEMIF Case Study: Sharing the Bus
Both ADCs and DACs are mapped to the Both ADCs and DACs are mapped to the same address space (CE3 = 0xB000 0000).same address space (CE3 = 0xB000 0000).
A/D
Da
ug
hte
rca
rd C
on
ne
cto
r
16
CLK
/XAOE
/XCE3
XD[0..15]
A/D16
CLK
XD[16..31]
Latch
Latch
/OE
/OE
CLK
CLK
XTOUT0
16
16
D/A16
CLK
/XAWE
/XCE3
XD[0..15]
D/A16
CLK
XD[16..31]
/CE3/CE3000011
/XAOE/XAOE0011xx
/XAWE/XAWE1100xx
/OE/OE001111
DAC_CLKDAC_CLK110011
/XAOE activates the latched A/D /XAOE activates the latched A/D output only during the read sequenceoutput only during the read sequence
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 29
EMIF Case Study: Daughter Board InterfaceEMIF Case Study: Daughter Board Interface
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 30
EMIF Case Study: HardwareEMIF Case Study: Hardware The INTDSK1115 daughtercard from ATE Communications contains:The INTDSK1115 daughtercard from ATE Communications contains:
CODEC.CODEC. 2 x ADC (AD9920).2 x ADC (AD9920). 2 x DAC (AD768).2 x DAC (AD768).
See schematics for further details:See schematics for further details: \Links\Schematics Page 1.pdf\Links\Schematics Page 1.pdf \Links\Schematics Page 2.pdf\Links\Schematics Page 2.pdf \Links\Schematics Page 3.pdf\Links\Schematics Page 3.pdf \Links\Schematics Page 4.pdf\Links\Schematics Page 4.pdf
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 31
EMIF Case Study: HardwareEMIF Case Study: Hardware
It requires +12V, -12V and 5V power supplies:It requires +12V, -12V and 5V power supplies:
+12V -12V GND +5V
DSK
Warning: Do NOT supply power to J4 and J8 at the same time.
Pin Signal Type1 +12V O2 -12V O3 DGND -4 +5V O
DaughtercardConnector
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 32
EMIF Case Study: SoftwareEMIF Case Study: Software Procedure:Procedure:
(1)(1) Set the EMIF registers.Set the EMIF registers.
(2)(2) Set the internal timer to generate the sampling frequency.Set the internal timer to generate the sampling frequency.
(3)(3) Ensure that the DSK6211_6711.gel is loaded.Ensure that the DSK6211_6711.gel is loaded.
(4)(4) Write the functions for reading and writing from/to the ADC and DAC respectively.Write the functions for reading and writing from/to the ADC and DAC respectively.
(5)(5) Set the interrupts.Set the interrupts.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 33
EMIF Case Study: Software - EMIFEMIF Case Study: Software - EMIF
(1)(1) Setting the Global Control Register:Setting the Global Control Register:
The GBLCTL register is common to all spaces and can be configured as The GBLCTL register is common to all spaces and can be configured as follows:follows:
#define EMIF_GCTL#define EMIF_GCTL 0x018000000x01800000
*(unsigned int *) EMIF_GCTL = 0x3300*(unsigned int *) EMIF_GCTL = 0x3300
Rsv Rsv Rsv Rsv BUSREQ ARDY HOLD HOLDANO
HOLD Rsv Rsv CLK1EN CLK2EN Rsv Rsv Rsv
Rsv
31 16
15 14 13 23456789101112 1 0
0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0
3 3 00
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 34
EMIF Case Study: Software - EMIFEMIF Case Study: Software - EMIF
Setting the CE Control Register:Setting the CE Control Register: Which space can be used to access the ADCs?Which space can be used to access the ADCs? From the DSK6211_6711.gel (From the DSK6211_6711.gel (DSK6211_6711_gel.pdfDSK6211_6711_gel.pdf) file we can see that the CE2 and CE3 are not used and are available on the Daughtercard interface.) file we can see that the CE2 and CE3 are not used and are available on the Daughtercard interface. In this application the CE3 space has been used.In this application the CE3 space has been used.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 35
EMIF Case Study: Software - EMIFEMIF Case Study: Software - EMIF
Setting the CE3 Control Register:Setting the CE3 Control Register: MTYPE?MTYPE?
The memory is configured as 32-bit asynchronous.The memory is configured as 32-bit asynchronous.
Therefore: MTYPE = 0010b.Therefore: MTYPE = 0010b.
B0000000B0000000
MemoryMemory
32-bits32-bits
addressaddress
A/D 1A/D 1A/D 2A/D 2
D/A 1D/A 1D/A 2D/A 2
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 36
Setting the CE3 Control Register:Setting the CE3 Control Register: MTYPE = 0010bMTYPE = 0010b: 32-bit async: 32-bit async Read/Write Hold = 011bRead/Write Hold = 011b: 3 x ECLKOUT: 3 x ECLKOUT Read/Write Strobe = 111111bRead/Write Strobe = 111111b: 31 x ECLKOUT: 31 x ECLKOUT Read/Write Setup = 1111bRead/Write Setup = 1111b: 15 x ECLKOUT: 15 x ECLKOUT
Therefore the CE3 space can be configured as follows:Therefore the CE3 space can be configured as follows:
EMIF Case Study: Software - EMIFEMIF Case Study: Software - EMIF
#define EMIF_CE3#define EMIF_CE3 0x018000140x01800014
*(unsigned int *) EMIF_CE3 = 0xffffff23*(unsigned int *) EMIF_CE3 = 0xffffff23
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 37
(2)(2) Select a timer: there are two timers available, Timer 0 and Timer 1.Select a timer: there are two timers available, Timer 0 and Timer 1. The two internal timers are controlled by six memory-mapped registers (3 registers each):The two internal timers are controlled by six memory-mapped registers (3 registers each):
(a)(a) Timer control registers: sets the operating modes.Timer control registers: sets the operating modes.
(b)(b) Timer period registers: holds the number of timer clock cycles to count.Timer period registers: holds the number of timer clock cycles to count.
(c)(c) Timer counters: holds current value of the incrementing counter.Timer counters: holds current value of the incrementing counter.
Note: the timer clock is the CPU clock divided by 4.Note: the timer clock is the CPU clock divided by 4.
EMIF Case Study: Software - TimerEMIF Case Study: Software - TimerSetting the sample rate: Using the internal timerSetting the sample rate: Using the internal timer
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 38
EMIF Case Study: Software - TimerEMIF Case Study: Software - Timer
RegisterRegisterAddressAddress
Timer 0Timer 0 Timer 1Timer 1 DescriptionDescription
Timer controlTimer controlTimer periodTimer period
Timer counterTimer counter
0x0194 00000x0194 00000x0194 00040x0194 0004
0x0194 00080x0194 0008
0x0198 00000x0198 00000x0198 00040x0198 0004
0x0198 00080x0198 0008
Sets the operating modeSets the operating modeHolds the number of timer Holds the number of timer clock cycles to countclock cycles to countHolds the current counter Holds the current counter valuevalue
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 39
FCPUFCPU
Initialise the timer:Initialise the timer:
EMIF Case Study: Software - TimerEMIF Case Study: Software - Timer
CPU Frequency = FCPU = 150000000 HzCPU Frequency = FCPU = 150000000 Hz
Sampling rate = SRATE = 4000 HzSampling rate = SRATE = 4000 Hz
TPRD = = = 468.75TPRD = = = 468.75
= 0x01D5 = 0x01D5
4 x 2 x 40004 x 2 x 4000150000000150000000
3200032000
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 40
#define FCPU 150000000 /* CPU clock frequency */#define SRATE 800000 /* data sample rate 800kHz */#define TPRD (FCPU/(4*2*SRATE)) /* timer period, using the clock mode */
TIMER_Handle hTimer; /* Handle for the timer device */
void start_timer1(){ *(unsigned volatile int *)TIMER1_CTRL = 0x000; /* Disable output of Timer 1 */ IRQ_map(IRQ_EVT_TINT1,8); hTimer = TIMER_open(TIMER_DEV1, TIMER_OPEN_RESET);
/* Configure up the timer. */ TIMER_configArgs(hTimer, TIMER_CTL_OF(0x000003c1), TIMER_PRD_OF(TPRD), TIMER_CNT_OF(0) ); /* Start Timer 1 in clock mode */ *(unsigned volatile int *)TIMER1_CTRL = 0x3C1;//clock mode /* Finally, enable the timer which will drive everything. */ TIMER_start(hTimer);}
The timer can be programmed as follows:The timer can be programmed as follows:
EMIF Case Study: Software - TimerEMIF Case Study: Software - Timer
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 41
EMIF Case Study: Software - Loading GELEMIF Case Study: Software - Loading GEL(3)(3) For the DSK6211 and DSK6711 select the DSK6211_6711.gel using:For the DSK6211 and DSK6711 select the DSK6211_6711.gel using:
Method 1:Method 1: FFile:Load ile:Load GGELEL
Location: ti\cc\gel\Location: ti\cc\gel\
Method 2:Method 2: You can automatically execute a specific GEL function at startup as follows:You can automatically execute a specific GEL function at startup as follows:
(1)(1) Select Setup CCS.Select Setup CCS.
(2)(2) Select the C6x11 DSK and right click.Select the C6x11 DSK and right click.
(3)(3) Select the “Startup GEL file(s)”.Select the “Startup GEL file(s)”.
(4) (4) Type the file location as shown:Type the file location as shown:
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 42
EMIF Case Study: Software - Loading GELEMIF Case Study: Software - Loading GEL
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 43
EMIF Case Study: Reading and Writing to EMIF Case Study: Reading and Writing to the A/D and D/Athe A/D and D/A
(4)(4) The ADC and DAC are memory-mapped and therefore can be accessed just The ADC and DAC are memory-mapped and therefore can be accessed just like accessing a memory.like accessing a memory.
#define INTDSK_CE3 0xB0000000#define INTDSK_CE3 0xB0000000
unsigned int analogue_in = 0;unsigned int analogue_in = 0;
unsigned int analogue_out = 0;unsigned int analogue_out = 0;
interrupt void timerINT1 (void)interrupt void timerINT1 (void)
{{
analogue_in = *(unsigned volatile int *) INTDSK_CE3;analogue_in = *(unsigned volatile int *) INTDSK_CE3;
/* data processing *//* data processing */
ad1 = analogue_in & 0xffff0000;ad1 = analogue_in & 0xffff0000; /* mask ad2 *//* mask ad2 */
ad2 = analogue_in & 0x0000ffff; ad2 = analogue_in & 0x0000ffff; /* mask ad1 *//* mask ad1 */
ad1 = ad1 << 4;ad1 = ad1 << 4;
ad2 = ad2 << 4;ad2 = ad2 << 4;
*(unsigned volatile int *) INTDSK_CE3 = analogue_out;*(unsigned volatile int *) INTDSK_CE3 = analogue_out;
}}
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 44
IRQ_nmiEnable ();IRQ_nmiEnable ();
EMIF Case Study: Setting the InterruptEMIF Case Study: Setting the Interrupt
(5)(5) Timer1 is used to generate the interrupts:Timer1 is used to generate the interrupts:
The interrupt causes the execution of an ISR to take place (e.g. “InoutISR”).The interrupt causes the execution of an ISR to take place (e.g. “InoutISR”).
Procedure for setting interrupt:Procedure for setting interrupt:
(1)(1) Map the CPU interrupt and the source:Map the CPU interrupt and the source:#include <intr.h>#include <intr.h>#include <regs.h>#include <regs.h>
IRQ_map (IRQ_EVT_TINIT, 8);IRQ_map (IRQ_EVT_TINIT, 8);
(2)(2) Enable the appropriate bit of the IER:Enable the appropriate bit of the IER:IRQ_enable (IRQ_EVT_TINT1);IRQ_enable (IRQ_EVT_TINT1);
(3)(3) Enable the NMI:Enable the NMI:
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 45
EMIF Case Study: Setting the InterruptEMIF Case Study: Setting the Interrupt
(4)(4) Enable global interrupts:Enable global interrupts:
Note: (4) has to be done last as it releases all the interrupts.Note: (4) has to be done last as it releases all the interrupts.
IRQ_globalEnable ();IRQ_globalEnable ();
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 46
EMIF Case Study: Complete CodeEMIF Case Study: Complete Code Project location: Project location:
\Code\Chapter 08 - EMIF\A_D_D_A_inout\\Code\Chapter 08 - EMIF\A_D_D_A_inout\ Project name: Project name:
A_D_D_A_inout.pjtA_D_D_A_inout.pjt Links:Links:
\Links\main.pdf\Links\main.pdf \Links\Daughtercard Photo.pdf\Links\Daughtercard Photo.pdf \Links\Daughtercard Datasheet.pdf\Links\Daughtercard Datasheet.pdf \Links\AD768.pdf\Links\AD768.pdf \Links\AD9220.pdf\Links\AD9220.pdf
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Chapter 8, Slide 47
INTDSK1115 Daughtercard Test CodeINTDSK1115 Daughtercard Test Code Project location: Project location:
\Code\Chapter 08 - EMIF\Code\Chapter 08 - EMIF Project name: Project name:
Test A/D, D/A and Codec:Test A/D, D/A and Codec: \TestApp\testapp_bios.pjt \TestApp\testapp_bios.pjt Test A/D and D/A:Test A/D and D/A: \WaveGen\wavegen_bios.pjt\WaveGen\wavegen_bios.pjt
Links:Links: \Links\Test Procedure.pdf\Links\Test Procedure.pdf
Chapter 8Chapter 8
External Memory Interface External Memory Interface (EMIF)(EMIF)
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