Chapter 8 continued
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Transcript of Chapter 8 continued
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Chapter 8 continued
Mealy FSMs
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FSM Model Variants
• Moore-type– Outputs depend only on Present State
• Mealy-type– Outputs depend on Present State AND Inputs
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Specify Desired Circuit• One input w• One output z• All changes occur on positive edge of clock• Output z = 1 if
– During immediately preceding clock cycle the input w was equal to 1 AND is currently equal to 1
• Output z = 0 otherwiseClockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10
w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
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Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
New Machine
Old Machine
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A w 0 = z 0 =
Reset
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
A A
zw
clk
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A B w 0 = z 0 =
Reset w 1 = z 0 =
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
A A B
zw
clk
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A
w 0 = z 0 =
B w 0 = z 0 =
Reset w 1 = z 0 =
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
A A B A
zw
clk
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A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
Reset w 1 = z 0 =
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
A A B A B
zw
clk
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A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
Reset w 1 = z 0 =
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
A A B A B B
zw
clk
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A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
Reset w 1 = z 0 =
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
A A B A B B A
zw
clk
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A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
Reset w 1 = z 0 =
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
A A B A B B A B
zw
clk
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A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
Reset w 1 = z 0 =
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
A A B A B B A B B
zw
clk
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A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
Reset w 1 = z 0 =
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
A A B A B B A B B B
zw
clk
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A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
Reset w 1 = z 0 =
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0
A A B A B B A B B B A
During present clock cycle output value on arc from Present State node Note difference from Moore model in
where output is shown output changes asynchronously
zw
clk
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State Table & State Assignment
Present Next state Output z
state w = 0 w = 1 w = 0 w = 1
A A B 0 0 B A B 0 1
Present Next state Outputstate w = 0 w = 1 w = 0 w = 1
y Y Y z z
A 0 0 1 0 0 B 1 0 1 0 1
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Derivation of Next-state and Output Expressions
Present Next state Outputstate w = 0 w = 1 w = 0 w = 1
y Y Y z z
A 0 0 1 0 0 B 1 0 1 0 1
yw 0 10 0 01 1 1
Y Truth Tabley w Y0 0 00 1 11 0 01 1 1 Y = w
yw 0 10 0 01 0 1
z Truth Tabley w z0 0 00 1 01 0 01 1 1 z = y.w
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Asynchronous Behavior of Mealy Model
• If z is connected to another synchronous clock no problem• If z is connected to another circuit not controlled by the
same clock a potential problem exists
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D Q
Q
D Q
Q
Clock
Resetn
y 2
y 1
Y 2
Y 1
w
z
Analysis of Synchronous State Machines
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D Q
Q
D Q
Q
Clock
Resetn
y 2
y 1
Y 2
Y 1
w
z
How many states?Create Present State/Next State/Output table
Present Next State
state Output
z
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D Q
Q
D Q
Q
Clock
Resetn
y 2
y 1
Y 2
Y 1
w
z
Present Next State
state w = 0 w = 1 Output
y 2 y 1 Y 2 Y 1 Y 2 Y 1 z
0 0 0 0 01 0 0 1 0 0 10 0 1 0 0 0 11 0 1 1 0 0 11 1
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Counter Using Sequential State Machine
• Counting Sequence is 0,1,2,…,6,7,0,1,…• Input w
– If w = 0 present count remains the same– If w = 1 count is incremented
• Create State Diagram• Create State Table• Create State Assignments
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FSM with Two Inputs• Inputs w1 and w2• Outputs z• If w1 = w2 during any four consecutive
clock cycles z = 1• Otherwise z = 0
w1 0 1 1 0 1 1 1 0 0 0 1 1 0w2 1 1 1 0 1 0 1 0 0 0 1 1 1z 0 0 0 0 1 0 0 0 0 1 1 1 0
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Homework
• Brown 8.3 & 8.5– Create
• State Diagram• State Table• State Assignment Table