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Chapter 7

Parallel Input/Output

This chapter presents the following I/O techniques:

Simple, blind data transfers Strobed data transfers Data transfers with handshaking

Simple, blind data transfers

Example:(Switch-LED connection to PORTC)

The circuit shows light emitting diode (LED) outputs and switch inputs connected to the port C pins.Each bit in the data direction register (DDRC) specifies the direction of the corresponding pin in portC. Each associated bit in the port C register will indicate the corresponding switch status or drive thecorresponding LED. Driving an LED high will turn it off and driving it low will turn on the LED.When the switch is open, voltage at a port C input is 5 V. When a switch is closed, the correspondingport C input is pulled low to ground.

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Example:Seven-Segment display

Each segment of a seven-segment display is an LED. A character can be displayed by illuminatingsome of the segments in the group of seven. Most displays include extra segments to be used asdecimal points. There are two types of seven-segment LEDs:

1. Common anode connection 2. Common cathode connection( current is sinking when bit is low) ( current is sinking when bit is high)

x 0 0 1 1 0 0 1

g f e d c b a g f e d c b a0: segment illuminated 1: segment illuminated

ldp rdp

af b

ge c

d

5v

a I

R

b0

b0

I

R

a

x 1 0 0 1 1 1 1

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In general instead of isolated current limiting resistors, drivers such as MC14495-1 Hexadecimal-to-seven Segment Latch/decoder ROM/driver are used. The MC14495-1 accepts a binary number,decodes it, and drives the appropriate segments to display the number.

Example:Write a software to display the digit 5 when port C is connected to a noninverting buffer.The buffer drives a common anode seven-segment display. Assume no decimal point is connected

(dp) g f e d c b a1 0 0 1 0 0 1 0 = $92

DISP5 EQU $92 ; binary number for coding 5REGBAS EQU $1000 ; register block pointerPORTC EQU $03 ; Port C register address offsetDDRC EQU $07 ; Port C data direction register address offset

BEGINLDX #REGBAS ; point to registers blockBSET DDRC,X $FF ; define portc as outputLDAA #DISP5 ; load the numberSTAA PORTC,X ; send data to portc

Example:If you do not use a hexadecimal-to-seven segment decoder, you have to do the conversionusing a look-up table.

LDY #REGBASLDX #TABLE ; TABLE can be an EEPROM location to mark the

; beginning of 16-byte blockLDAB DATA ; get single digit hex representation of dataABXLDAA $00,XSTAA PORTC,Y

MC 14495-1 7 segmentdisplay

B0B1B2B3

B4 LE

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KEYBOARD INTERFACING

12-key keypad circuit

Each key has a momentary contact switch that is connected to an intersection of row and columnwires. When a key is released, an open circuit exists between all wires/terminals. When a key ispressed the contact closure connects the row and column wire. Thus, a short circuit exists betweenrow and column wires when a key is pressed. To determine which key is pressed, a microcontrollermust scan the rows and columns to identify the row and column intersection of the short circuit. Akeyboard decoder can drive a signal to a column and sense the row lines to determine which key ispressed, if any. Port C is a convenient port to use (see the following figure) because its lines can beconfigured as input or output. To identify the key code, the microprocessor scans each contact insequence.

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Simple keyboard interfaceDebouncing

Bouncing is the tendency of any two metal contacts in an electronic device to generate multiplesignals as the contacts close or open. When you press a key on your computer keyboard, you expect asingle contact to be recorded by your computer. In fact, however, there is an initial contact, a slightbounce or lightening up of the contact, then another contact as the bounce ends, yet another bounceback, and so forth. A similar effect takes place when a switch made using a metal contact is opened.The usual solution is a debouncing device or software that ensures that only one digital signal can beregistered within the duration of a given time (usually milliseconds).

Example: Keyboard decoding

ORG $100MAIN LDS #$00FF ; initialize stack

LDX #REGBAS ; point to registersJSR INITKYBD ; initialize keyboard interface

MAIN1JSR GETKEY ; wait for key to be pressedJSR BREAKKEY ; then wait for it to be releasedBRA MAIN1 ; and repeat loop

* Subroutine INITKYBD* Initializes the keyboard interface

* Calling Register* IX = register block address* Return Registers* CCR affectedINITKYBD

PSHA ; preserve registersLDAA #%00001111STAA DDRC,X ; PC0-3 output, PC4-7 inputPULA ; restore registersRTS ; return

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* Subroutine GETKEY* Waits for key to be pressed and returns its key code* Calling Registers* IX = register block address* Return Registers* ACCA = key code* CCR affected

GETKEYPSHB ; preserve registers

GETKEY1JSR IDKEY ; return key code in ACCACMPA #0 ; if key == 0 then repeat scanBEQ GETKEY1JSR DEBOUNCE ; debounce delayPSHA ; save key found prior to debounceJSR IDKEY ; return new key code in ACCAPULB ; if key != key-1 then repeat scanCBABNE GETKEY1 ; else returnPULB ; restore registersRTS

* ----------------------------------------------------------

* Subroutine BREAKKEY* Waits for key to be released (break condition)* Calling Registers* IX = register block address* No return registers except that CCR affected

BREAKKEYPSHA

BREAK1JSR IDKEY ; key code of zeroCMPA #0 ; means break occurredBNE BREAK1 ; if break detected then debounceJSR DEBOUNCEJSR IDKEY ; and check for break againCMPA #0BNE BREAK1 ; if no break then repeatPULA ; else returnRTS

*Subroutine IDKEY* Returns key code from keyboard. A key code of zero

* means that no key was pressed.* Calling Registers* IX = register block address* Return Registers* ACCA = key code

IDKEYPSHY ; preserve registersPSHBLDY #KYTAB ; point to table, init keypt

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CLRA ; key = 0IDKEY1

INCA ; key++INY ; keypt++LDAB 0,Y ; drive port C outputsSTAB PORTC,XANDB #$F0 ; mask off LS nibblePSHA ; preserve keyLDAA PORTC,XANDA #$F0 ; mask off LS nibbleCBA ; if portc == *keypt then returnPULA ; note CCR is not unaffected, so next decision is about CBA resultBEQ IDKEY2 ; if key < lastkey (12)CMPA #12 ; then repeat idkey1BLO IDKEY1CLRA ; else key = 0 if no key pressed

IDKEY2PULB ; restore registersPULYRTS ; return(key)

* Subroutine DEBOUNCE* Delay 10 ms at E = 2 MHz* No calling or return registers

DEBOUNCEPSHX ; preserve registerLDX #$0D06 ; init loop counter

* this is the delay loopDEBOUNCE1

DEX

BNE DEBOUNCE1PULX ; restore registerRTS ; return

* Look-up table to map port C data to each key code

* Note that interface has PC7 connected to logic high

KYTABFCB $FF ; key code of zero, don't careFCB $EE, $DE, $BEFCB $ED, $DD, $BDFCB $EB, $DB, $BBFCB $E7, $D7, $B7

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Strobed I/O

An I/O port may have to read a sequence of bytes or transmit a sequence. Parallel communicationinterfaces used in printers, floppy disks and parallel buses for peripheral communication use controlsignals to coordinate the transfer of data. The simplest controlled data transfer technique is strobedI/O. This method of performing I/O operations uses a control line, the strobe, to notify the receivingunit of the availability of data. When a microprocessor sends data to a peripheral, it tells the peripheralthat data is available by sending a strobe signal. Similarly, if the microprocessor is reading data from aperipheral, it has to know when the next data is sent. The peripheral can send a strobe signal to notifythe microprocessor that new data is available.

Basic strobed I/O operation:

Device performing the write places data onto data bus (its output port) Strobe signal is asserted (for 2 cycles in 68HC11) Strobe signal causes data to be latched into input port of the receiving device Strobe signal causes an I/O interrupt to occur or a flag to be set -- in either case the receiving

device is signaled to indicate that new data has arrived

It is up to the receiving device to read the new data at its input port in a "timely" fashionTwo control pins for strobed I/O: Strobe A (STRA) and strobe B (STRB).

68HC11 register support for strobed I/ O

DDRC -- data direction register for port C (at $1007)PORTCL -- port C input latch -- data is latched on STRA edge (at $1005) used for strobed

and handshake I/OPORTC -- input pins for port C -- not latched (at $1003)PORTB -- latched output data port B outputs data using STRB (at $1004)PIOC -- parallel I/ O control register (at $1002) determines how the microcontroller will

behave for parallel operations.

PIOC register explanation:

STAF (Strobe A Flag)0 = Inactive1 = Set at the active edge of STRA pin.

The Strobe A Flag bit can be read by the program. It is set by the STRA active edge which is definedby the state of the EGA bit. The programmer can use the STAF to find out if data has been latchedinto PORTCL. A two-step process clears the STAF bit. First, the PIOC register is read. If the STAFbit is set, reading the data in PORTCL clears the STAF bit.

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STAI (Strobe A Interrupt Enable)

0 = No hardware interrupt generated (default).1 = Interrupt requested when STAF = 1.

The STAI bit enables or disables the interrupt request from being generated when STRA is asserted.

CWOM (Port C Wire-OR Mode)0 = Port C outputs normal (default)1 = Port C outputs Open-drain

The CWOM bit in the PIOC allows the outputs to be configured as open-drain, wire-OR bits to beconnected directly to a bus that has pull-up transistors.

HNDS (Handshake simple strobe mode select)

0 = Simple strobe mode (default)1 = Full handshake mode.

OIN (Output/Input handshake select) (Only in handshake mode)

0 = Input (default)1 = Output

PLS (Pulse mode select for STRB Output) (Only in handshake mode)0 = STRB level active1 = STRB pulses

EGA (Active edge select for STRA)0 = High to low (falling)1 = Low to high (rising, default)

INVB (Invert STRB out) (Only in handshake mode)

0 = STRB active low.

1 = STRB active high (default)

Strobed input operations using PORTC

Data is placed at the input pins of PORTC STRA is asserted by peripheral device, causing

o Data to be latched into PORTCLo STAF flag to be assertedo Interrupt initiated, if interrupts are enabled

Data is read into the processor from PORTCL To clear STAF, read PIOC first and then PORTCL

Example:(transfer 10 bytes from port C into a memory array)

ORG $100

LDX #REGBASCLR DDRC,X ; configure port C as inputLDAA #$02 ; configure PIOC registerSTAA PIOC,X ; active STRA is rising edgeLDY #PTR ; initialize storage pointerLDAB #$0A ; initialize byte counter (10 bytes are going to be read)

; poll STAF bit to detect the rising edge in STRA signal

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CIN BRCLR PIOC,X $80 CIN ; same as LDAA PIOC,X, ANDA #$80, BEQ CINLDAA PORTCL,X ; read port CL to get the input when STRA was detectedSTAA 0,Y ; and store itINY ; repeat 10 timesDECBBNE CINSTOP ; then stop

Strobed Output

Peripheral device is connected to PORT B When the MCU writes to PORT B,

o Data is placed on PORT B pins,o STRB is automatically asserted low for 2 clock cycles.

Peripheral device should use STRB to latch the data STRB can be configured as active-high or active-low

Example:(transfer 10 bytes from a memory array to the port)ORG $100

LDY #PTR ; initialize data pointerREPEATLDAA 0,Y ; send out data when it occursSTAA PORTB,X ; note, MCU also pulses STRB low for two E cyclesINY ; repeat for next data transferBRA REPEAT

Example: You are given the following components:

- A simple unencoded keypad organized as a 2x5 matrix,in which the bouncing is eliminated by the switchhardware. A switch at a cross point connects the rows

and columns when pressed and there is no need forsoftware debounce handling.

- An output device, which displays the BCD number at itsinput terminals. The inputs are latched and displayedeach time LE signal is activated.

You are required to design an M68HC11 based system such that the system displays the number code

of the pressed key. Each time a new key is pressed, the display will be updated accordingly. In yoursystem, use interrupt driven strobed I/O technique. Logic one and zero are available but no othercomponents, apart from resistors and logic gates are available.

a) Give the connection diagram of your system that connects the given components to M68HC11 toperform the required task assuming that processor operates in the single-chip micro-controllermode.

a Displaybcd

LE

BCDinput

0 1 2 3 4

5 6 7 8 9

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b) Using your connection diagram, write a complete M68HC11 program to do the required task. Thedisplay should show zero initially. Write your program in assembly language using labels. Forclarity, give as much comments as possible and use a reasonable number of instructions.

Solution:

REGBASE EQU $1000

PIOC EQU $02PORTC EQU $03

PORTB EQU $04PORTCL EQU $05DDRC EQU $07

PORTDIR EQU %11000000 ; PC7-6: output, PC5-4: inputPIOCDATA EQU %01000000 ; STAI enabled, simple strobe mode selected

; STRA falling edge, SRTB automatically activelow.

ORG $IRQ_PSEUDO_VECTOR ; address of the interrupt pseudo vectorJMP STAF_ISR ; jump to the address of the interrupt subroutine

ORG $5000 ; main programLDS #STACKBASE ; initialize stack address

LDX #REGBASE ; initialize register base addressLDAA #PORTDIR ; initialize port C directionsSTAA DDRC,XLDAA #PIOCDATA ; initialize port C control registerSTAA PIOC,XBCLR PORTC,X $CO ; clear Port C 7-6CLI ; enable interrupt

CONTWAIBRA CONT

0 1 2 3 4

5 6 7 8 9

a Displaybcd

LE

PC7

PC6

PC0PC1PC2PC3PC4

M68HC11STRA

PB0PB1PB2PB3

STRB

to 5 pull-upresistors

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STAF_ISR ; interrupt subroutineJSR INKEY ; if an interrupt occurs go to INKEY sunroutineSTAA PORTB,X ; store ACCA to Port B

EXIT RTI

INKEYBCLR PORTC,X $80 ; Prot C 7 is clearedBSET PORTC,X $40 ; Port C 6 is setLDAB PORTC,X ; read Port CCLRA ; ACCA stores the pressed keys column numberCLR OFFSET ; for first row/ second row separation

SHIFTLSRBBCC FOUND ; if the checked bit is clear then it is the pressed keyINCA ; otherwise increment ACCACMPA #$05 ; if the pressed key is in first rowBNE SHIFT ; continue to checkLDAB #$05 ; otherwise continue checking with the second rowSTAB OFFSETCLRABSET PORTC,X $80BCLR PORTC,X $40LDAB PORTC,XBRA SHIFT

FOUNDADDA OFFSET ; obtain the pressed keys number from the column

number and offsetLDAB PIOC,X ; clear STAFLDAB PORTCL,XBCLR PORTC,X $C0 ; clear Port C 7-6RTS ; return to the interrupt subroutine

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Handshaking I/O

Strobed input includes a signal from the peripheral telling the MCU that data is available. Butthere is no signal from the MCU to the peripheral telling it that the MCU is ready to receivedata. Similarly, strobed output includes a signal for the MCU to tell the peripheral that data isavailable. But there is no signal from the peripheral to the MCU to tell the MCU that the

peripheral is ready to receive data.

When there is a transfer of data, there may a set of rules, which defines when and how totransfer each byte. This set of rules is known as a data exchange protocol. A protocol is a setof standard procedures used in data communications that coordinates the transmitting andreceiving of information.

The handshake protocol is an agreement whereby the receiver acknowledges each unit of datait receives. The transmitter waits for this acknowledgement before it sends the next unit. Aparallel I/O subsystem handshake protocol in general, transfers each byte as a unit.

The 68HC11 supports automatic handshaking for parallel I/O for port C. This is determined

by configuring the control register PIOC. An automatic handshake means that the hardwareresponds to certain signals automatically without using any program instructions.

It is possible to use PORTCL, STRA and STRB to set up a full handshaking I/O transferprotocol. In this case STRA is always used as a pathway for peripheral communication to theMCU and STRB is always used for communication from the MCU to the peripheral.

To use automatic handshaking, the HNDS bit of PIOC should be set to 1, and the OIN shouldbe set to 0 for input handshake and 1 for output handshake.

Input Handshake

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There are two options for the signal going from the MCU to the peripheral on STRB. IfPLS=0 then STRB will be level active, if PLS=1 then STRB will be pulsed. These two modesare also known as interlocked and pulsed handshaking, respectively.

Pulsed input operation with handshake:

The peripheral will generate a pulse on strobe A to indicate that it has sent data. The 68HC11responds to the pulse. It should have a program that responds by reading the data in. When68HC11 reads the data, it automatically acknowledges the peripheral device by pulsingSRTB for two clock cycles. This is known as pulsed handshake operation.

The figure below shows the timing diagram for the case when 68HC11 is configured forSTRA active falling and STRB active low. To cause the output acknowledge pulse in inputhandshake mode, the PORTCL register must be read by 68HC11 software after readingPIOC.

Summary:

Peripheral pulses STRA to indicate that data is present When 68HC11 reads the data (from PORTCL), it automatically generates an

acknowledgment strobe on STRB for 2 cycles

This mode is selected by initializing the PLS bit (bit 2 of the PIOC) to 1

Interlocked input operation with handshake:

In this case STRB acts like a ready signal. It is active only when the MCU is ready to read

data. This is its normal condition. When it is busy with the process of reading in data, theready line is deasserted. It asserts again after the MCU has read the data.

Figure below shows interlocked operation when strobe B, the ready line, is active low. Whenthe peripheral sees the ready line deasserted, it should follow the rules by not sending newdata at that time. When the 68HC11 reads the contents of data latch register PORTCL, strobeB asserts automatically to indicate that the MCU is ready for new data. The peripheral shouldnot send new data until it sees the strobe B line low.

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Summary:

Here, STRB acts as a READY signal Asserted = 68HC11 ready to receive data Negated = 68HC11 is not ready -- do not send data now This mode is selected by initializing the PLS bit (bit 2 of the PIOC) to 0

Example: Simple input handshake subroutine.

*Program simply reads in data as it comes.*Subsystem configuration is interlocked

ORG $100

DIR EQU $00CONF EQU $01

DEMOIN LDX #REGBAS ;point to registersCLR DIR ;configure for input handshakeLDAA #$10 ;HNDS=1 OIN,PLS,EGA,INVB=0STAA CONFJSR INITHNDS

REPEATIN JSR INHNDA ;read input data continuouslyNOPBRA REPEATIN

*Subroutine INITHNDS*Initializes port c for handshake mode

INITHNDS PSHA ;preserve registersBCLR PIOC,X $10 ;put in strobe mode firstLDAA PIOC,X ;then clear STAF if setLDAA PORTCL,X

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LDAA DIR ;set up port C directionSTAA DDRC,XLDAA CONFSTAA PIOC,XPULA ;restore registersRTS

*Subroutine INHNDS*Uses input handshake to read port C

INHNDS BRCLR PIOC,X $80 INHNDS ;poll for STRA transitionLDAA PORTCL,X ;input strobed data and clear STAFRTS

Output Handshake

Strobe A is an input ready or busy line and strobe B is an output strobe line. To configureport C for output handshake, set bit OIN to 1.

Port C is used for output handshake operations, along with STRB and STRA STRB is the output "data available" strobe STRA is the acknowledgment / input ready strobe line PIOC bit 3, OIN, set to 1 for output operations

Pulsed operation:

The 68HC11 writes data to port C (PORTCL) and automatically sends a strobe signal bypulsing strobe B for two clock cycles. This tells the peripheral that data is available for it to

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read. The peripheral reads the data and responds by asserting a ready signal. This tells theMCU that the peripheral has read the data and is ready for new data. The 68HC11 sees theready signal as a transition on pin STRA. It sees it because the active edge of STRA causesflag bit STAF to set. The MCU can now write the next byte to register PORTCL.

Figure below shows the timing diagram when strobes A (edge) and B (pulse) are configured

to be active low for polled I/O operation. The flag-clearing sequence of bit STAF is to readcontrol register PIOC first and then write to data latch register PORTCL.

Summary:

68HC11 writes data to PORTCL and automatically asserts STRB for 2 cycles Peripheral device reads data upon receipt of the STRB strobe Peripheral asserts its READY line (68HC11's input STRA line) to signal receipt

of data

PIOC bit 2, PLS set to 1 for pulsed modeInterlocked operation:

Writing to PORTCL asserts strobe B. When the 68HC11 receives the acknowledgement (orready), it deasserts strobe B. Writing new data to PORTCL will assert strobe B again. Forinterlocked output handshake the configuration routine must reset bit PLS and set bit OIN incontrol register PIOC.

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Summary:

Upon writing data to PORTCL, STRB is asserted STRB negated only upon ACK

Example: Simple program code for output handshake.

*Program simply outputs same data when requested by peripheral.*Subsystem is interlocked.

ORG $100DIR EQU $00

CONF EQU $01

OUTDATA EQU $02DEMOOUT LDX #REGBAS ;point to registers

LDAA #$FF ;configure for output directionSTAA DIRLDAA #$18 ;and output handshake, interlockedSTAA CONFJSR INITHNDS

REPEATOUT LDAA OUTDATAJSR OUTHNDSBRA REPEATOUT

*Subroutine uses output handshake to send data to port C and*waits for peripheral ready before returning

OUTHNDS STAA PORTCL,X ;output data clears STAF alsoOUTHNDS1 BRCLR PIOC,X $80 OUTHNDS1 ;polling for STRA transition

RTS

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Parallel subsystem summary

Ports B and Care available for I/O only in the single chip mode -- can be replaced by thePRU (port replacement unit) when in expanded mode

Port A3 input, 3 output, 2 bi-directional pinsBits DDRA7 and DDRA3 in PACTL set direction for A7 and A3

Port BParallel output only (single chip mode)

Port CData register is PORTCLatched register is PORTCLEach bit is bi-directionalDirection set using the register DDRC

Port D6 bi-directional pins, directions set by DDRDPin 6 = STRA, Pin 7 = STRB(These pins become AS and R/W* in expanded multiplexed mode)

Port E8-bit input only

Conditions on resetAll data direction bits are set to 0 (input)Output port bits are set to 0Input port bits are high impedance

Strobed I/OStrobed output via Port B, strobed input via Port CDetected edge on STRA causes input data to be latched in PORTCL and STAF flag in PIOCregister to be set (and interrupt, if enabled)Writing data to Port B also pulses STRB

Handshake I/OPort C used for either input or output operationInput: read data from PORTCLOutput: write data to PORTCL

Some Parallel Interface Standards

The Centronics Parallel Interface is commonly used for printers. It defines how to connect a printer toa computer and the form of the data sent to it. Microcontrollers often use this standard because manyprinters use a microcontroller. Also, some other microcontroller systems send output to a printer. Ahandshake protocol is defined by this standard.

IEEE-488 General-Purpose Instrumentation Bus (GPIB) standard is used for communication betweena computer and instruments. For example, a computer tells a digital storage csope to sample data andsend the data to the computer for analysis. IEEE-488 specifies the physical characteristics and theprotocol for transferring bytes of data. It also uses handshaking.

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The small computer systems interface (SCSI) is designed for communications between personalcomputers and intelligent I/O devices such as disk drives, tape dries and remote printers.