Chapter 11: Operating System Support Dr Mohamed Menacer Taibah University 2007-2008.
Chapter 7: System Buses Dr Mohamed Menacer Taibah University 2007-2008.
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Transcript of Chapter 7: System Buses Dr Mohamed Menacer Taibah University 2007-2008.
Chapter 7:Chapter 7:System BusesSystem Buses
Dr Mohamed MenacerDr Mohamed MenacerTaibah UniversityTaibah University
2007-20082007-2008
Bus StructuresBus Structures
There are a number of possible There are a number of possible interconnection systemsinterconnection systems
Single and multiple BUS structures are Single and multiple BUS structures are most commonmost common
e.g. Control/Address/Data bus (PC)e.g. Control/Address/Data bus (PC)
e.g. Unibus (DEC-PDP)e.g. Unibus (DEC-PDP)
What is a Bus?What is a Bus?
A communication pathway connecting two A communication pathway connecting two or more devicesor more devices
Usually broadcast Usually broadcast
Often groupedOften grouped A number of channels in one busA number of channels in one bus e.g. 32 bit data bus is 32 separate single bit e.g. 32 bit data bus is 32 separate single bit
channelschannels
Power lines may not be shownPower lines may not be shown
Data BusData Bus
Carries dataCarries data Remember that there is no difference Remember that there is no difference
between “data” and “instruction” at this levelbetween “data” and “instruction” at this level
Width is a key determinant of performanceWidth is a key determinant of performance 8, 16, 32, 64 bit8, 16, 32, 64 bit
Address busAddress bus
Identify the source or destination of dataIdentify the source or destination of data
e.g. CPU needs to read an instruction e.g. CPU needs to read an instruction (data) from a given location in memory(data) from a given location in memory
Bus width determines maximum memory Bus width determines maximum memory capacity of systemcapacity of system e.g. 8080 has 16 bit address bus giving 64k e.g. 8080 has 16 bit address bus giving 64k
address space address space
Control BusControl Bus
Control and timing informationControl and timing information Memory read/write signalMemory read/write signal Interrupt requestInterrupt request Clock signalsClock signals
Bus Interconnection SchemeBus Interconnection Scheme
Bus ArchitectureBus Architecture
What do buses look What do buses look like?like? Parallel lines on Parallel lines on
circuit boardscircuit boards Ribbon cablesRibbon cables Strip connectors on Strip connectors on
mother boardsmother boardse.g. PCIe.g. PCI
Sets of wiresSets of wires
Single Bus ProblemsSingle Bus Problems
Lots of devices on one bus leads to:Lots of devices on one bus leads to: Propagation delaysPropagation delays
Long data paths mean that co-ordination of bus Long data paths mean that co-ordination of bus use can adversely affect performanceuse can adversely affect performance
If aggregate data transfer approaches bus capacityIf aggregate data transfer approaches bus capacity
Most systems use multiple buses to Most systems use multiple buses to overcome these problemsovercome these problems
Traditional (ISA) (with cache)Traditional (ISA) (with cache)
High Performance BusHigh Performance Bus
Bus TypesBus Types
DedicatedDedicated Separate data & address linesSeparate data & address lines
MultiplexedMultiplexed Shared linesShared lines Address valid or data valid control lineAddress valid or data valid control line Advantage - fewer linesAdvantage - fewer lines DisadvantagesDisadvantages
More complex controlMore complex control
Ultimate performanceUltimate performance
Bus ArbitrationBus Arbitration
More than one module controlling the busMore than one module controlling the bus
e.g. CPU and DMA controllere.g. CPU and DMA controller
Only one module may control bus at one Only one module may control bus at one timetime
Arbitration may be centralised or Arbitration may be centralised or distributeddistributed
Centralised or Distributed Centralised or Distributed ArbitrationArbitration
CentralisedCentralised Single hardware device controlling bus Single hardware device controlling bus
accessaccessBus ControllerBus Controller
ArbiterArbiter May be part of CPU or separateMay be part of CPU or separate
DistributedDistributed Each module may claim the busEach module may claim the bus Control logic on all modulesControl logic on all modules
TimingTiming
Co-ordination of events on busCo-ordination of events on bus
SynchronousSynchronous Events determined by clock signalsEvents determined by clock signals Control Bus includes clock lineControl Bus includes clock line A single 1-0 is a bus cycleA single 1-0 is a bus cycle All devices can read clock lineAll devices can read clock line Usually sync on leading edgeUsually sync on leading edge Usually a single cycle for an eventUsually a single cycle for an event
Synchronous Timing DiagramSynchronous Timing Diagram
PCI BusPCI Bus
Peripheral Component InterconnectionPeripheral Component Interconnection
Intel released to public domainIntel released to public domain
32 or 64 bit32 or 64 bit
50 lines50 lines
PCI Bus Lines (required)PCI Bus Lines (required)
Systems linesSystems lines Including clock and resetIncluding clock and reset
Address & DataAddress & Data 32 time mux lines for address/data32 time mux lines for address/data Interrupt & validate linesInterrupt & validate lines
Interface ControlInterface Control
ArbitrationArbitration Not sharedNot shared Direct connection to PCI bus arbiterDirect connection to PCI bus arbiter
Error linesError lines
PCI Bus Lines (Optional)PCI Bus Lines (Optional)
Interrupt linesInterrupt lines Not sharedNot shared
Cache supportCache support
64-bit Bus Extension64-bit Bus Extension Additional 32 linesAdditional 32 lines Time multiplexedTime multiplexed 2 lines to enable devices to agree to use 64-2 lines to enable devices to agree to use 64-
bit transferbit transfer
JTAG/Boundary ScanJTAG/Boundary Scan For testing proceduresFor testing procedures
PCI CommandsPCI Commands
Transaction between initiator (master) and Transaction between initiator (master) and targettarget
Master claims busMaster claims bus
Determine type of transactionDetermine type of transaction e.g. I/O read/writee.g. I/O read/write
Address phaseAddress phase
One or more data phasesOne or more data phases
PCI Bus ArbiterPCI Bus Arbiter