Chapter 7 Microsequencer Control Unit Design

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Chapter 7 Microsequencer Control Unit Design

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Chapter 7 Microsequencer Control Unit Design. 7.1 Basic Microsequencer Design. Microsequencer It stores its control signals in a lookup ROM, microcode memory. The lookup ROM asserts the control signals in the proper sequence to realize the instructions. Microsequencer operations - PowerPoint PPT Presentation

Transcript of Chapter 7 Microsequencer Control Unit Design

Page 1: Chapter 7 Microsequencer Control Unit Design

Chapter 7

Microsequencer

Control Unit Design

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7.1 7.1 Basic Microsequencer Basic Microsequencer DesignDesign

MicrosequencerMicrosequencer– It stores its control signals in a lookup It stores its control signals in a lookup

ROM, microcode memory.ROM, microcode memory.– The lookup ROM asserts the control The lookup ROM asserts the control

signals in the proper sequence to realize signals in the proper sequence to realize the instructions. the instructions.

Microsequencer operationsMicrosequencer operations– Microinstruction: consists of several bit Microinstruction: consists of several bit

fields, which are micro-operation field and fields, which are micro-operation field and next address field. next address field.

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Figure 7.1 Generic microsequencer organization

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Microinstruction formats Microinstruction formats

Figure 7.2Figure 7.2 Select field: To determine the source of Select field: To determine the source of

the address of the microinstructionthe address of the microinstruction ADDR field: To specify an absolute ADDR field: To specify an absolute

address for performing an absolute address for performing an absolute jump by the microsequencer.jump by the microsequencer.

Micro-operations field: To generate Micro-operations field: To generate control signalscontrol signals– Horizontal microcodeHorizontal microcode– Vertical microcode Vertical microcode

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Figure 7.2

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Horizontal microcode and Vertical Horizontal microcode and Vertical microcodemicrocode

Horizontal microcodeHorizontal microcode– One bit in the micro-operations field of the One bit in the micro-operations field of the

microinstruction is assigned to each micro-microinstruction is assigned to each micro-operation.operation.

– This can result in large microinstruction.This can result in large microinstruction. Vertical microcodeVertical microcode

– The micro-operations are grouped into fields.The micro-operations are grouped into fields.– Vertical microinstructions require fewer bits Vertical microinstructions require fewer bits

than their equivalent horizontal than their equivalent horizontal microinstructions.microinstructions.

– The microsequencer must incorporate a The microsequencer must incorporate a decoder for each micro-operation signals. decoder for each micro-operation signals.

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7.2 7.2 Design and implementation Design and implementation of a very simple microsequencerof a very simple microsequencer

Layout: Figure 7.3 Layout: Figure 7.3

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Figure 7.3

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Mapping logicMapping logic

The microsequencer will use the The microsequencer will use the same mapping function(Refer to same mapping function(Refer to Figure 6.9.Figure 6.9.

1 IR[1..0] 01 IR[1..0] 0– This will produce addresses of 1000, This will produce addresses of 1000,

1010,1100,1110 for ADD1, AND1, 1010,1100,1110 for ADD1, AND1, JUMP1, and INC1, respectively.JUMP1, and INC1, respectively.

– Figure 7.4 , Table 7.1, Table 7.2Figure 7.4 , Table 7.1, Table 7.2

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Figure 7.4

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Generating the micro-operations Generating the micro-operations using horizontal microcodeusing horizontal microcode

A microsequencer has two tasksA microsequencer has two tasks– To generate the correct micro-operationsTo generate the correct micro-operations– To follow the correct sequence of the states.To follow the correct sequence of the states.

The micro-operations and their mnemonics are The micro-operations and their mnemonics are shown in Table 7.3.shown in Table 7.3.

The complete list of control signals is given in The complete list of control signals is given in Table 7.6.Table 7.6.

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Generating the micro-operations Generating the micro-operations using vertical microcodeusing vertical microcode

Figure 7.5Figure 7.5

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Figure 7.5

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Guidelines for groupingGuidelines for grouping

– Whenever two micro-operations occur during Whenever two micro-operations occur during the same state, assign them to different fields.the same state, assign them to different fields.

– Include a NOP in each field if necessary(Table Include a NOP in each field if necessary(Table 7.7).7.7).

– Distribute the remaining micro-operations to Distribute the remaining micro-operations to make best use of the micro-operation field make best use of the micro-operation field bits.bits.

– Group together micro-operations that modify Group together micro-operations that modify the same registers in the same fields.the same registers in the same fields.

Table 7.8, Figure 7.6 Table 7.8, Figure 7.6

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Figure 7.6

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NonoinstructionsNonoinstructions

Figure 7.AFigure 7.A It encodes all micro-operations in a It encodes all micro-operations in a

single field.single field. The microcode memory outputs a The microcode memory outputs a

value that points to a location in value that points to a location in nano-memory.nano-memory.

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Figure 7A

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7.3 7.3 Design and implementation of a Design and implementation of a Relatively simple microsequencerRelatively simple microsequencer

Refer to Figure 6.12Refer to Figure 6.12 Two state, JNPZ1 and JMPZ1 are Two state, JNPZ1 and JMPZ1 are

created for the states -JMPZY1, created for the states -JMPZY1, JMPZN1, JPNZY1, JPNZN1(Figure JMPZN1, JPNZY1, JPNZN1(Figure 7.7)7.7)

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Figure 7.7

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Basic layout for the Basic layout for the microsequencermicrosequencer

Figure 7.8Figure 7.8– The box “+1” is a hardware The box “+1” is a hardware

incrementer.incrementer.– Since the state diagram has 39 Since the state diagram has 39

states, microsequencer needs a 6-states, microsequencer needs a 6-bit address.bit address.

– Mapping function: IR[3..0]00.Mapping function: IR[3..0]00.– Table 7.11Table 7.11

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SEL signalSEL signal

Unconditional jump and Unconditional jump and conditional jump (Refer to Table conditional jump (Refer to Table 7.12)7.12)

BT: Branch logic (Table 7.14)BT: Branch logic (Table 7.14)

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Figure 7.8

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7.4 7.4 Reducing the number Reducing the number of microinstructionsof microinstructions

MicrosubroutineMicrosubroutine– Figure 7.9 & 7.10Figure 7.9 & 7.10

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Figure 7.9

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Figure 7.10

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Reducing the number of Reducing the number of microinstructions(continuemicroinstructions(continue

d)d) Microcode jumpsMicrocode jumps Figure 7.11Figure 7.11

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Figure 7.11

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7.5 7.5 Microprogrammed Microprogrammed control vs. Hardwired control vs. Hardwired

controlcontrol Complexity of the instruction setsComplexity of the instruction sets Ease of modificationEase of modification Clock speedClock speed

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7.6 7.6 Pentium Pentium MicroprocessorMicroprocessor

Figure 7.12Figure 7.12

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Figure

7.12