Chapter 7: Main Memory

CS 170, Fall 2011

8.2

Program Execution & Memory Management

Program execution

Swapping

Contiguous Memory Allocation

Paging

Structure of the Page Table

Segmentation

8.3

Multistep Processing of a User Program

8.4

Binding of Instructions and Data to Memory

happen at three different stages

Compile time: If memory location known a priori, absolute code can be generated.

Load time: Must generate relocatable code if memory location is not known at compile time

Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another.

8.5

Logical vs. Physical Address Space

Logical address – generated by the CPU; also referred to as virtual address

Physical address – address seen by the memory unit

Logical and physical addresses are the same in compile-time and load-time address-binding schemes;

logical (virtual) and physical addresses differ in execution-time address-binding scheme

8.6

Memory-Management Unit (MMU)

Hardware device that maps virtual to physical address

In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory

8.7

Base and Limit Registers

A pair of base and limit registers define the logical address space

8.8

Hardware Support for Relocation and Limit Registers

8.9

Swapping

A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution

Backing store – fast disk large enough to accommodate copies of memory images for user processes

Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed

8.10

Schematic View of Swapping

8.11

Contiguous Memory Allocation

Main memory has two partitions:

Resident operating system,

usually held in low memory

User processes then held in high memory

Hardware support and protection

Base register contains value of smallest physical address

Limit register contains range of logical addresses – each logical address must be less than the limit register

MMU maps logical address dynamically

OS

process 5

process 8

process 2

8.12

Contiguous Allocation (Cont.)

Multiple-partition allocation

Hole – block of available memory; holes of various size are scattered throughout memory

When a process arrives, it is allocated memory from a hole large enough to accommodate it

Operating system maintains information about:a) allocated partitions b) free partitions (hole)

OS

process 5

process 8

process 2

OS

process 5

process 2

OS

process 5

process 2

OS

process 5

process 9

process 2

process 9

process 10

8.13

Lastallocatedblock (14K)

Before

8K

12K

22K

18K

6K8K

14K

36K

Free block

Allocated block

Example: Allocate 16K block

Which free block to allocate for a new request of 16K block?

8.14

Dynamic Memory Allocation Methods

First-fit: Allocate the first hole that is big enough Fast

Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size Produces the smallest leftover hole Slow, leading more external fragmentation

Worst-fit: Allocate the largest hole; must also search entire list Produces the largest leftover hole Slow

How to satisfy a request of size n from a list of free holes

8.15

Lastallocatedblock (14K)

Before After

8K 8K

12K 12K

22K

18K

6K 6K8K 8K

14K 14K

6K

2K

36K20K

Worst Fit

Free block

Allocated block

Best Fit

First Fit

Example: Allocate 16K block

8.16

Fragmentation Issues External Fragmentation – total memory space exists to

satisfy a request, but it is not contiguous

Case 1 Case 2

8.17

Methods to reduce external fragmentation

Compaction

Shuffle memory contents to place all free memory together in one large block

Compaction is possible only if relocation is dynamic, and is done at execution time

I/O problem

Latch job in memory while it is involved in I/O

Do I/O only into OS buffers

Another strategy: paging

8.18

Example of Relocation for Compaction

8.19

Paging: Equal-size memory partitioning

Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8,192 bytes)

Divide logical memory into blocks of same size called pages or logical pages

To run a program of size n pages, need to find n free frames and load program

8.20

Paging Model of Logical and Physical Memory

A page table is needed to translate logical to physical addresses

8.21

Management of Free Space

Before allocation After allocation

8.22

Fragmentation Issues

Remove/reduce external fragmentation, but lead to Internal Fragmentation

– allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used

8K

8K

8 M

8K

8K

process 1

Unused

8 K allocated forProcess 1

8.23

Address Translation Scheme Address generated by CPU is divided into:

Page number (p) – used as an index into a page table which contains base address of each page in physical memory

Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit

page number page offset

p d

m - n n

8.24

Paging Hardware

8.25

Hardware Support of Page Table Page table is kept in main memory

Page-table base register (PTBR) points to the page table

Page-table length register (PRLR) indicates size of the page table

Every data/instruction access requires two memory accesses.

One for the page table and one for the data/instruction.

Slowness due to two memory access can be addressed by using a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)

8.26

Associative Memory for TLB

Associative memory – parallel search

Address translation (p, d)

If p is in associative register, get frame # out

Otherwise get frame # from page table in memory

Page # Frame #

8.27

Paging Hardware With TLB

8.28

Example: Performance Characteristics of TLB

Typical TLB Size: 8 - 4,096 entries

Access time: 0.5 - 1 clock cycle

Miss penalty: 10 - 100 clock cycles

Miss rate: 0.01 - 10%

If a TLB hit takes 1 clock cycle, a miss takes 30 clock cycles, and the miss rate is 1%,

the effective memory cycle rate for page mapping:

1*0.99 + (1+30)X0.01=1.30

Total memory access = page mapping + memory access = 31.30 clock cycles

8.29

Memory Protection

Memory protection implemented by associating protection bit with each frame

Valid-invalid bit attached to each entry in the page table:

“valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page

“invalid” indicates that the page is not in the process’ logical address space

8.30

Valid (v) or Invalid (i) Bit In A Page Table

8.31

Shared Pages through Paging

Shared code

One copy of read-only code shared among processes (i.e., text editors, compilers, window systems).

Shared code must appear in same location in the logical address space of all processes

Private code and data

Each process keeps a separate copy of the code and data

The pages for the private code and data can appear anywhere in the logical address space

8.32

Shared Pages Example

8.33

Structure of the Page Table

How is a page table implemented?

Hierarchical Paging

Hashed Page Tables

Inverted Page Tables

8.34

One-Level Page Table

What is the maximum size of logical space?

Mapping of pages

8.35

Hierarchical Page Tables

Motivating example:

32 -bit address space with 4KB per page.

Page table would contain 2^32/ 2^12= 1 million entries.

4 bytes per entry

Need a 4MB page table with contiguous space.

Is there 4MB contiguous space for each process?

Can we divide this page table into multiple page tables hierarchically?

8.36

Two-Level Page-Table Scheme

8.37

Two-Level Paging Example

A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits a page offset consisting of 12 bits

The page number is further divided into: a 10-bit page number a 10-bit page offset

where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table

page number page offset

pi p2 d

10 10 12

8.38

Address-Translation Scheme

8.39

Three-level paging in a 64-bit address space

8.40

Linear Address in Linux

Broken into four parts:

8.41

Hashed Page Tables

Common in address spaces > 32 bits

Use hash table to limit the cost of search

to one — or at most a few — page-table entries

One hash table per process

This page table contains a chain of elements hashing to the same location

Use this hash table to find the physical page of each logical page

If a match is found, the corresponding physical frame is extracted

8.42

Hashed Page Table

8.43

Inverted Page Table

One hash table for all processes

One entry for each real page of memory

Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page

Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs

8.44

Inverted Page Table Architecture

8.45

Segmentation

Memory-management scheme that supports user semantic view of memory

A program is a collection of segments A segment is a logical unit such as:

main program

procedure

function

method

object

common block

stack

symbol table

arrays

8.46

Example of Segmentation

8.47

Segmentation Hardware