CHAPTER 7 First we convert 19 10 and -4 10 to eight-bit two’s complement form then we ... 1000 The...

CHAPTER 7

Exercises

E7.1 (a) For the whole part, we have: Quotient Remainders 23/2 11 1 11/2 5 1 5/2 2 1 2/2 1 0 1/2 0 1

Reading the remainders in reverse order, we obtain: 2310 = 101112

For the fractional part we have 2 × 0.75 = 1 + 0.5 2 × 0.50 = 1 + 0

Thus we have 0.7510 = 0.1100002

Finally, the answer is 23.7510 = 10111.112

(b) For the whole part we have:

Quotient Remainders 17/2 8 1 8/2 4 0 4/2 2 0 2/2 1 0 1/2 0 1

Reading the remainders in reverse order we obtain: 1710 = 100012

For the fractional part we have 2 × 0.25 = 0 + 0.5 2 × 0.50 = 1 + 0

Thus we have 0.2510 = 0.0100002


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(c) For the whole part we have: Quotient Remainders 4/2 2 0 2/2 1 0 1/2 0 1

Reading the remainders in reverse order we obtain: 410 = 1002

For the fractional part, we have 2 × 0.30 = 0 + 0.6 2 × 0.60 = 1 + 0.2 2 × 0.20 = 0 + 0.4 2 × 0.40 = 0 + 0.8 2 × 0.80 = 1 + 0.6 2 × 0.60 = 1 + 0.2

Thus we have 0.3010 = 0.0100112


E7.2 (a) 1101.1112 = 1×23 + 1×22 +0×21 +1×20 +1×2-1 +1×2-2 +1×2-3 = 13.87510

(b) 100.0012 = 1×22 +0×21 +0×20 +0×2-1 +0×2-2 +1×2-3 = 4.12510

E7.3 (a) Using the procedure of Exercise 7.1, we have 9710 = 11000012

Then adding two leading zeros and forming groups of three bits we have 001 100 0012 = 1418

Adding a leading zero and forming groups of four bits we obtain 0110 0001 = 6116 (b) Similarly 22910 = 111001012 = 3458 = E516

E7.4 (a) 728 = 111 010 = 1110102 (b) FA616 = 1111 1010 0110 = 1111101001102

E7.5 19710 = 0001 1001 0111 = 000110010111BCD

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E7.6 To represent a distance of 20 inches with a resolution of 0.01 inches, we need 20/0.01 = 2000 code words. The number of code words in a Gray code is 2L in which L is the length of the code words. Thus we need L = 11, which produces 2048 code words.

E7.7 (a) First we convert to binary 2210 = 16 + 4 + 2 = 101102

Because an eight-bit representation is called for, we append three leading zeros. Thus +22 becomes

00010110 in two’s complement notation. (b) First we convert +30 to binary form 3010 = 16 + 8 + 4 + 2 = 111102 Attaching leading zeros to make an eight-bit result we have 3010 = 000111102

Then we take the ones complement and add 1 to find the two’s complement:

one’s complement: 11100001 add 1 +1 11100010 Thus the eight-bit two’s complement representation for -3010 is

11100010. E7.8 First we convert 1910 and -410 to eight-bit two’s complement form then we

add the results. 19 00010011 -4 111111100 15 00001111 Notice that we neglect the carry out of the left-most bit. E7.9 See Tables 7.3 and 7.4 in the book.

E7.10 See Table 7.5 in the book.

E7.11 (a) To apply De Morgan’s laws to the expression

CBAB + first we replace each logic variable by its inverse

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CBBA + then we replace AND operations by OR operations and vice versa ))( CBB ++(A finally we invert the entire expression so we have ))(( CBBACBAB ++=+D = (b) Following the steps of part (a) we have ]) GFHG ++([F ]) GFHG ++([F )])( GFHG ++[(F )])([(])([ GFHGFGFHGF ++=++E = E7.12 For the AND gate we use De Morgan’s laws to write

)( BAAB += See Figure 7.21 in the book for the logic diagrams.

E7.13 The truth table for the exclusive-OR operation is

A B A ⊕ B 0 0 0 0 1 1 1 0 1 1 1 0

Focusing on the rows in which the result is 1, we can write the SOP expression BABABA +=⊕ The corresponding logic diagram is shown in Figure 7.25a in the book. Focusing on the rows in which the result is 0, we can write the POS expression ))(( BABABA ++=⊕ The corresponding logic diagram is shown in Figure 7.25b in the book.

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E7.14 The truth table is shown in Table 7.7 in the book. Focusing on the rows in which the result is 1, we can write the SOP expression

RGFDRGDFRGDFDGRFRDGFGRDF

mA+++++=

= ∑ )12 9, 8, 7, 6, 3,(

Focusing on the rows in which the result is 0, we can write the POS expression

)())()((

15) 14, 13, 11, 10, 5, 4, 2, 1, 0,(

RGDFRGDFRGDFRGDFMA

++++++++++++=

= ∏L

E7.15 The Truth table is shown in Table 7.8.

E7.16 (a) DCBA (b) DCBA

E7.17 See Figure 7.34 in the book. E7.18 See Figure 7.35 in the book. E7.19 Because S is high at t = 0, Q is high and remains so until R becomes high

at t = 3. Q remains low until S becomes high at t = 7. Then Q remains high until R becomes high at t = 11.

E7.20 See Table 7.9. E7.21 See Figure 7.49 in the book.

Problems P7.1* 1. When noise is added to a digital signal, the logic levels can still be

exactly determined, provided that the noise is not too large in amplitude. Usually, noise cannot be completely removed from an analog signal. 2. Component values in digital circuits do not need to be as precise as in analog circuits. 3. Very complex digital logic circuits (containing millions of components) can be economically produced. Analog circuits often call for large

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capacitances and/or precise component values that are impossible to manufacture as large-scale integrated circuits.

P7.2 A bit is a binary symbol that can assume values of 0 or 1. A byte is a word consisting of eight bits. A nibble is a four-bit word.

P7.3 In positive logic, the logic value 1 is represented by a higher voltage

range than the voltage range for logic 0. The reverse is true for negative logic.

P7.4 The noise margins for a logic circuit are defined as NML = VIL − VOL and NMH = VOH − VIH

in which VIL is the highest input voltage accepted as logic 0, VIH is the lowest input voltage accepted as logic 1, VOL is the highest logic-0 output voltage, and VOH is the lowest logic-1 output voltage. Large values for the noise margins are important so noise added to or subtracted from logic signals in the interconnects does not change the operation of the logic circuit.

P7.5 In serial transmission, the bits of a word are transmitted one after another over a single pair of wires. In parallel transmission, multiple bits are transmitted simultaneously over a parallel set of wires.

P7.6 (a)* 5.625 (b) 7.75 (c) 10.25 (d) 7.875

(e) 8.3125 (f)* 21.375

P7.7 (a) 1710 = 100012 = 00010111BCD

(b) 8.510 = 1000.12 = 1000.0101BCD

(c)* 9.7510 = 1001.112 = 1001.01110101BCD

(d) 73.0312510 = 1001001.000012 =01110011.00000011000100100101BCD

(e) 67.37510 = 1000011.0112 = 01100111.001101110101BCD

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P7.8 Seven-bit words are needed to express the decimal integers 0 through 100 in binary form (because 27 = 128). Ten-bit words are needed to express the decimal integers 0 through 1000 in binary form (because 210 = 1024). Twenty-bit words are needed to express the decimal integers 0 through 106 in binary form (because 220 = 1048576).

P7.9 (a)* 1101.11 + 101.111 = 10011.101

(b) 1011 + 101 = 10000 (c) 10001.111 + 0101.001 = 10111.000

P7.10 (a)* 10010011.0101BCD + 00110111.0001BCD = 93.510 + 37.110 = 130.610 = 000100110000.0110BCD

(b) 01011000.1000BCD + 10001001.1001BCD = 58.810 + 89.910 = 148.710 = 000101001000.0111BCD

P7.11 (a) 17310 = 101011012 = 2558 = AD16

(b) 299.510 = 100101011.12 = 453.48 = 12B.816 (c) 735.75 = 1011011111.112 = 1337.68 = 2DF.C16

(d)* 313.062510 = 100111001.00012 = 471.048 = 139.116 (e) 112.2510 = 1110000.012 = 160.28 = 70.416

P7.12 (a) 19 = 00010011 (eight-bit signed two’s complement)

(b) -19 = 11101101 (c)* 75 = 01001011 (d)* -87 = 10101001 (e) -95 = 10100001 (f) 99 = 01100011

P7.13 (a) FA.F16 = 11111010.11112 = 372.748 = 250.937510

(b) 2A.116 = 101010.00012 = 52.048 = 42.062510 (c) 777.716 = 11101110111.01112 = 3567.348 = 1911.437510

P7.14 (a) 777.78 = 111111111.1112 = 1FF.E16 = 511.87510

(b) 123.58 = 1010011.1012 = 53.A16 = 83.62510 (c) 24.48 = 10100.1002 = 14.816 20.510

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P7.15 (a) Counting in decimal, 778 follows 777. (b) Counting in octal, 1000 follows 777. (c) Counting in hexadecimal, 778 follows 777.

P7.16 (a) A 3-bit binary number can represent the decimal integers 0 through 7. (b) A 3-digit octal number can represent the decimal integers 0 through 511. (c) A 3-digit hexadecimal number can represent the decimal integers 0 through 4095.

P7.17* Write the 3-bit code shown in Figure 7.9. Then, extend the list by writing the 3-bit code in reverse order. Finally, prepend a 0 to each word in top half of the list and prepend a 1 to each word in the bottom half. The resulting four-bit Gray code is: 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 The Gray code is used for coding positions of movable parts. In a Gray code, each code word differs in only one bit from its neighboring code words, so that erroneous position indications are avoided during transitions.

P7.18 (a)* FA5.616 = 4005.37510

(b)* 725.38 = 469.37510 (c) 3F4.816 = 1012.510

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(d) 73.258 = 59.32812510 (e) FF.F016 = 255.937510

P7.19

P7.20 ) 17 00010001

01000000 00111111 11000000 (e)

00000100 00000011 11111100 (d)01010110 01010101 10101010 (c)00000000 11111111 00000000 (b)00011000 00010111 11101000 *(a)

Complement sTwo'Complement sOne'

⇒⇒

⇒⇒

⇒⇒

⇒⇒

⇒⇒4847648476

(a +15 00001111 32 00100000 (b) 17 00010001 -15 11110001 2 00000010 (c)* 33 00100001 -37 11011011 -4 11111100 (d) 15 00001111 -63 11000001 -48 11010000 (e) 49 00110001

-44 11010100 5 00000101

P7.21 verflow and underflow are not possible if the two numbers to be added sign

verflow has occurred.

P7.23* AND operation is replaced by OR, the OR operation is replaced by AND,

Ohave opposite signs. If the two numbers to be added have the same and the result has the opposite sign, underflow or o

P7.22 A truth table lists all of the combinations of the variables in a logic expression as well as the value of the expression. If the variables in a logic expression are replaced by their inverses, the

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and the entire expression is inverted, the resulting logic expression yields the same values as before the changes. In equation form, we have: AABC = CCB ++ ( ) CBABA =++

P7.24

AB C

AND gate:

00 0

0 10 0 11 1

AB C

01

OR gate:

00 0

1 10 1 11 1

01

A

A

Inverter:

0 1 1 0

AB C

NAND gate:

01 1 10 1

00 1

11 0 NOR gate:

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AB C 00 1 01 0 10 0 11 0 Exclusive OR gate:

10 1 11 0

P7.25 ne method to prove the validity of a Boolean identity is to list the truth s he identity give the same result for

P7.26

AB C 00 0 01 1

Otable and show that both ides of teach combination of logic variables.

(a) BAABCD += A B C D 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0

1 0 0 1 1 1

1 0 1 1 0 0 1 1 1 1 (b)* DCCBAABE ++= A B C D E 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0

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0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1

1 1 0 0 1 0 1

1

1 1 1 1 1 1 0 1 1 1 1 1 (c) ( )YWWXZ ++= X Y W Z 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0

1 0 0 1 1 1

1 0 1 1 0 0 1 1 1 1 (d) CBAAD ++= A B C D 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1

0 1 1 1

1 0 1 0 1 1 0 1 1 1 1 1

(e) )( BCAD += A B C D 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0

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1 0

( )CBAF +=

0 0 1 0 1 0 1 1 0 0 1 1 1 0

P7.27 )

( )BA +=

(a

(b) BCF + (c) BF + ( ) DBCA +=

P7.28* A + B + C BCA B C ( )(A ) A +

1 1 1 1 1 0 0 1 1

1 1 1

P7.29

0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0

1 0 1 1 1 1 0 1 1 1 1 1

))(( ABABAABABABA ++++

1 1 1 1 1 0 1 0 0

1

matches that for

0 0 0 1 0

).)(( ABABA ++

0

BABAABA ++

1 1 1 1 Notice that the column for B

P7.30 0 0 0

1 1 1 0 1 1 1 1 1 1

0 0 1

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P7.31

P7.32 (a)

CBAF +=

BCACABCBAF ++=

1 1 1 11 0 1 11 1 0 11 0 0 10 1 1 00 0 1 0 0 1 0 0

0 0 0 0)( CBACBACABABCCBA +++

) (b

(c)* ( )( )( )CBACBACBAF ++++++=

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(a)

))()(( CBACBACBACBAC ++++++=+

( ) ( )( )DACBADACABF ++=++=P7.33 (b) ( ) ( )DCBADCBAF +=++= (c) ( ) ( CBACBACBAF ++=++= )( )CBA + (d)* BACBACBACBACBAF +=++++++= ))()(( CBAC +

CBA )(=

(e)* BAABCF +=

P7.34 tes are said to be sufficient for combinatorial logic because any olea xpression can be implemented solely with NAND gates. ila , NO gate are fici .

P7.35 this ircu if sw tch closed and if either of the other two itch is c ed, e ou ut is high. Thus, we can write:

NAND gaBo n eSim rly R s suf ent In c it, i C issw es los th tp

D +

A B C D The truth table is:

1 0 0 0

1 0 0

P7.36 this rcu the utput is high only if switch A is open (A low) and if

her the other two switches is open. Thus, we can write

0 0 0 0 0 0 1 1 0

BA +=

0 1 1 0

1 0 1 1 1 1 0 0 1 1 1 1

In ci it, oeit of )(CD

B C D

The truth table is: A

0 0 1 0

1 1 1

0 0 0 1

0 1 0 1 0

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1 0 0 0 1 0 1 0

1 1 0

P7.37

1 1 0 0 1 (a) Applying DeMorgan's laws to the output, we have

ABBAC =+= Thus, the gate shown is equivalent to a NAND gate. (b) Applying DeMorgan's laws to the output, we have

EDEDF +== Thus, the gate shown is equivalent to a NOR gate.

P7.38 In synthesizing a logic expression as a sum of products, we focus on the

hese lines. Then the products are summed.

e is 0. A logical sum of logic

ariables and their inverses is written that yields 0 for each of these lines. Then the sums are comb ed in an AND gate.

e of a decoder is a circuit that uses a BCD input to produce the logic signals needed to drive the elements of a seven-segment display.

other example s the three-to-eight-line decoder that has a three-bit input and eight output lines. The 3-bit input word selects one of the output lines and that output becomes high.

P7.40*

lines of the truth table for which the result is 1. A logical product of logic variables and their inverses is written that yields 1 for each of t In synthesizing a logic expression as a product of sums, we focus on thlines of the truth table for which the resultv

in

ABCCBACBACBAF +++=

( )∑= 7,5,2,0m

P7.39 An exampl

An i

( )∏= 6,4,3,1M

( )( )( )( )CBACBACBACBAF ++++++++=

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P7.41 BCACBAG += ( )3,0m∑=

))()()()()(( CBACBACBACBACBACBAG ++++++++++++= ( )∏= 7,6,5,4,2,1M

P7.42 ABCCABCBACBACBACBACBAH ++++++= ( )∑= 7,6,5,4,2,1,0m

( ) ( )3MCBAH =++=

P7.43 ABCCABBCAI ++= ∑= )7,6,3(m

))()()()(( CBACBACBACBACBAI ++++++++++= ∑= )5,4,2,1,0(M

P7.44 ABCCABCBABCACBAJ ++++= ∑= )7,6,5,3,1(m ))()(( CBACBACBAJ ++++++= ∑= )4,2,0(M P7.45 ABCCABCBACBAK +++= ∑= )7,6,1,0(m ))()()(( CBACBACBACBAK ++++++++= ∑= )5,4,3,2(M P7.46 Applying DeMorgan's Laws to the output of the circuit, we have

CDABCDAB =+ Thus, the circuit is

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P7.47 Applying DeMorgan's Laws to the output of the circuit, we have )()())( DCBADCB +++=+(A +

Thus, the circuit is

P7.48 (a) The truth table is: B E F G I 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 (b) ( )∑= 13,12,8,5,4mI (c) ( )∏= 15,14,11,10,9,7,6,3,2,1,0MI (d) GFBFEI +=

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P7.49* The truth table is: A B A ⊕ B 0 0 0 0 1 1 1 0 1 1 1 0 Thus, we can write the product of sums expression and apply DeMorgan’s

Laws to obtain:

)()( BABABABAB =+=A ⊕ The circuit is:

P7.50 The truth table is: A B A ⊕ B 0 0 0 0 1 1 1 0 1 1 1 0

Thus, we can write the product of sums expression and apply DeMorgan’s Laws to obtain:

)()())(( BABABABAB +++=++=A ⊕

The circuit is:

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P7.51 The truth table (x = don't cares) is:

B8 B4 B2 B1 A B 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 x x 1 0 1 1 x x 1 1 0 0 x x 1 1 1 0 x x 1 1 1 1 x x ( )∏= 6,4,1MA ( )∏= 6,5MB The circuits are:

261

P7.52* (a) S1 S2 ST E

0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 (b) ( )∑ +== TT SSSSSSmE 21216,1 (c) Circuit diagram:

P7.53* (a) The Karnaugh map is:

262

(b) DCACBF +=

(c) Inverting the map, and writing the minimum SOP expression yields CDCBACF ++= . Then applying DeMorgan's laws gives

))()(( DCCBCA +++F = P7.54 (a) The Karnaugh map is:

(b) BCACBD +=

(c) Inverting the map, and writing the minimum SOP expression yields two possibilities: CBCBACD ++= and CBCBABD ++= Then, applying DeMorgan's laws gives the POS expressions: ))()(( CBCBCAD +++= and ))()(( CBCBBAD +++=

P7.55 (a) The Karnaugh map is:

(b) ACCAD += (c) CACAD += ))(( CACAD ++=

263


(b) BCABD +=

(c) Inverting the map, and writing the minimum SOP expression yields CABD += . Then applying DeMorgan's laws gives

BCABCABD +=+= )( which is the same as the expression found in part (b) so the implementation is the same.


(b) BCDDABF += (c) The circuit is:

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(d) Inverting the map, and writing the minimum SOP expression yields DCBDAF ++= . Then applying DeMorgan's laws gives )()( DCBDAF ++=

P7.58* (a) The Karnaugh map is:

(b) DCABF += (c) The circuit is:

(d) Inverting the map, and writing the minimum SOP expression yields

DBCBDACAF +++= . Then, applying DeMorgan's laws gives

))()()(( DBCBDACAF ++++=

265


(b) BCDABCG += (c) The circuit is:


CBDAG ++= . Then, applying DeMorgan's laws gives BCDAG )( +=


(b) ADBCH +=

266

(c) The circuit is:


DCDBCABAH +++= . Then, applying DeMorgan's laws gives ))()()(( DCDBCABAH ++++= .


(b) DAC +AI =

(c) The circuit is:


CDAI += . Then, applying DeMorgan's laws gives )( DCAI += .

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P7.62 The Karnaugh map (with the decimal equivalent of each word in the upper right hand corner of each square) is:

By inspection the minimal SOP expression is: 18 BBX = P7.63 The Karnaugh map (with the decimal equivalent of each word in the upper

right hand corner of each square) is:

By inspection, the minimal SOP expression is:

2848 BBBBX += Inverting the map, and writing the minimum SOP expression yields

428 BBBX += . Then, applying DeMorgan's laws gives )( 428 BBBX += .

268

P7.64 The Karnaugh map (with the hexadecimal equivalent of each word in the upper right hand corner of each square) is:

By inspection the minimal SOP expression is:

41BBX =

Inverting the map, and writing the minimum SOP expression yields

41 BBX += . Then, applying DeMorgan's laws gives 41BBX = .

P7.65 The truth table is:

S I1 I2 O1 O2 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 0 0 0 0 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1

The Karnaugh maps are:

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The logic circuit is:

P7.66 The Karnaugh map for a three-member council is:

By inspection, we see that three two-cubes are needed and the minimal

SOP expression is BCACABX ++= Clearly, the minimal SOP checks to see if at least one group of two

members has voted yes.

For a five-member council, the Karnaugh map consists of two four-variable maps, one for A = 1 and one for A = 0.

270

Notice that six four-cubes are needed to cover the A = 1 part of the

map. Think of the A = 0 map as being (over or under) the A = 1 map. Four two cubes are needed to cover the A = 0 part of the map. However each of these cubes can be combined with corresponding cubes in the A = 1 part of the map to form four 4-cubes. The minimum SOP expression is:

CDEBDEBCEBCDACEACDADEABEABDABCX +++++++++=

Here the minimal SOP expression checks to see if at least one group of three members has voted yes.

P7.67 The Karnaugh map is

By inspection, we see that six one cubes are needed. Thus the minimal SOP expression is:

CDBADCBADBCADCBADCBADCABX +++++=

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P7.68 (a) The truth table for the circuit of Figure P7.68 is

A B C D P 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1

1 1 1 1 0

(b) The Karnaugh map for P is:

From the map, we see that no simplification is possible and the minimum

SOP is actually the sum of minterms: = ∑ 14) 13, 11, 8, 7, 4, 2, ,1(mP

(c) The parity check can be performed by the same method as used in Figure P7.68, namely to XOR all of the bits. The circuit is:

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P7.69 By inspection, we see that AX =

The Karnaugh maps for Y and Z are:

BABAY += CBCBZ += P7.70 By inspection, we see that XA =

The Karnaugh maps for B and C are:

YXYXB += XYZZYXZYXZYXC +++=

273

P7.71* (a) DBBCAF ++=

(b) BCBDAG ++=

(c) DCBCBAH ++=

274

(d) DI =

P7.72 (a) FHA =

(b) HFGFB +=

275

(c) HGHGC +=

(d) ID =

P7.73 (a) BDBCAW ++=

276

(b) DCBDBCBX ++=

(c) DCCDY +=

(d) DZ =

277

P7.74 (a) WZWXA +=

(b) ZWYXYZYXB ++=

(c) ZYZYC +=

278

(d) ZD =

P7.75

P7.76 See Figure 7.39 in the text. P7.77 See Figure 7.44 in the text. P7.78 Asynchronous inputs are recognized independently of the clock signal.

Synchronous inputs are recognized only if the clock is high. P7.79 In edge triggering, the input values present immediately prior to a

transition of the clock signal are recognized. Input values (and changes in input values) at other times are ignored.

P7.80 See Figure 7.47 in the text.

279

P7.81* The successive states are:

Q0 Q1 Q2 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1 (repeats) Thus, the register returns to the initial state after seven shifts.

P7.82 (a) With an OR gate, we have:

Q0 Q1 Q2

1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 After the register reaches the 111 state, it remains in that state and never returns to the starting state. (b) With an AND gate, we have: Q0 Q1 Q2 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 After the register reaches the 000 state, it remains in that state and never returns to the starting state.

280

P7.83

The period of the 0Q waveform is double that of INV . Similarly, the

period of 1Q is twice that of 0Q . Thus, flip flops connected in this manner divide the frequency of an input signal by two and by four.

P7.84

3Q becomes high at 7=t and quickly resets all four flip flops.

281

P7.85*

Q J K D memory 0 0 0 0 reset 0 0 1 0 set 0 1 0 1 toggle 0 1 1 1 memory 1 0 0 1 reset 1 0 1 0 set 1 1 0 1 toggle 1 1 1 0

KQJKJQJKQKJQD +++= ( ) ( )JJKQKKJQ +++= KQJQ +=

P7.86

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P7.87 (a) The logic diagram for the counter is:

(b) The truth table for the encoder is:

Q3 Q2 Q1 D1 D2 D3 D4 D5 D6 D7

0 0 0 x x x x x x x 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 0 1 1 1 0 1 1 1 0 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 x x x x x x x The Karnaugh maps are:

283

From the maps we can write:

3271 QQDD +== 362 QDD == 14 QD = and 3253 QQDD == The logic diagram is:

P7.88 (a) There are four diodes and to make one revolution in two seconds each

diode must be on for 0.5 s. Thus, the frequency of the clock is 2 Hz. (b) The modulo-4 counter is:

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(c) The truth table is S Q2 Q1 D1 D2 D3 D4

0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 0 1 0 1 1 1 0 1 0 0 The minimimal SOP expressions are:

211 QQD = SQQSQQD 21212 += 213 QQD = SQQSQQD 21214 +=

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CHAPTER 7 First we convert 19 10 and -4 10 to eight-bit two’s complement form then we ... 1000 The...

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Transcript of CHAPTER 7 First we convert 19 10 and -4 10 to eight-bit two’s complement form then we ... 1000 The...