Chapter 7 – Counterhoangtrang/lecture note/ECE290... · 3. Synchronous counter: Not full counter:...

Computer Eng 1 ECE290

Chapter 7 – Counter

HOANG Trang

Overview

Counter: review Asynchronous counter Synchronous countery

HOANG Trang Chapter 7-Counter 2

1. Counter: review

Counter:=> proceed through a well-defined seq ence of states in response to a co nt signalsequence of states in response to a count signal+ Modulo definition: the number of states

000

Q2Q1Q0 Typically:

+ No data input000

100001 m = 5

+ No data input

+ Inputs are usually clock pulses

+ Output is the state

011101

p

+ Could have control lines


101

1. Counter: review

Modulo m2 ( ) f ll t 000

Q2Q1Q0

m=2exp(n) => full countern: the number of FF

000

1000001 m = 5

011101

Ex: m=5 < 2exp(3): => NOT Full Counter

101Examples:

BCD counter: 0,1,2,3,4,5,6,7,8,9,0,1,2,…

3-bit binary counter: 000,001,010,011,100,101,110,111,000,001,…

Increment-by-3 counter: 0,3,6,9,0,3,…

G d t 00 01 11 10 00


Gray code counter: 00, 01, 11, 10, 00, …

Mod 4 counter: 000, 001, 010, 011, 000,…

1. Counter: type of counter

Asynchronous counter (or Ripple counter)output of FF connects to CLK of next FFp

T Q1 T Q1 T Q1

Q0 (LSB) Q1 Q2 (MSB)

. .

QCK QCK QCKCLK

S h ll f FF CLK d h Synchronous counter: all of FF-CLK are connected together Q0 (LSB)Q2 (MSB) Q1

T2 Q2

QCK

1

.

.

T1 Q1

QCK

T0 Q0

QCK


Q2CK2CK

Q1CK1 Q0CK0

..

2. Asynchronous counter (or Ripple counter)

Asynchronous counter (or Ripple counter)=> Usually use T-FF, JK-FFy

T Q1 J Q

CK

1 .QCK K Q

+ Full Counter (m=2exp(n))=> Counter Upp=> Counter Down (count backward)

+ Not full counter (m<2exp(n))


( p( ))

2. Asynchronous counter (or Ripple counter): Full counter->counter Up

Counter UpQ0 (LSB) Q1 Q2 (MSB)

T Q1 T Q1 T Q1. .QCK QCK QCK

CLK

CK

(LSB) Q0

Q1

0


(MSB) Q2

2. Asynchronous counter (or Ripple counter): Full counter -> counter Down

Counter DownQ0 (LSB) Q2 (MSB)Q1

Counter Down

J Q

CK

1 . J Q

CK

1 . J Q

CK

1 ...CK

K Q K Q K QCK

CK

(LSB) Q0

Q1


(MSB) Q2

2. Asynchronous counter (or Ripple counter): Not Not full counter: how to design? Example 1

How to design?=> Need to use FF with asynchronous input signal Preset/ClearPreset=active -> Output=1 ; Clear=active -> Output=0

Example1: design Counter UP Modulo=5: 000, 001,010,011,100,000 by using T-FF with low-active

asynchronous input Preset, Clear.

Idea to design: we call Z: reset signal to reset Counter. When Counter is 101 (not used state) => Z is active to reset Counter back to 000back to 000



Idea to design: When Counter is 101 (not used state) => Z is active to reset Counter back to 000active to reset Counter back to 000


Called: “Reset state”


Example: design Counter DOWN Modulo=5, initial state is 2. 010 001 000 111 110 010 by using T-FF with low-active010, 001,000,111,110,010,… by using T-FF with low-active

asynchronous input Preset, Clear.


Called: “Reset state”


Example: design Counter DOWN Modulo=5, initial state is 2. 010 001 000 111 110 010 by using T-FF with low-active010, 001,000,111,110,010,… by using T-FF with low-active

asynchronous input Preset, Clear.How to come back to initial state 010??



O


counter DOWN

3. Synchronous counter: how to design? Design steps

Synchronous counter: all of FF-CLK are connected together Design steps:

+ Specification

+ The number of FF? (from SPEC)

Design steps:

+ Next state table

+ From excitation table of specified FF and Next state table => find INPUT functions.

+ Draw circuit.

Recall Excitation table


3. Synchronous counter: Full counter: how to design? Example 1

Example 1: design counter by using T-FFQ2Q1Q0 = 010, 101, 110, 001, 000, 111, 100, 011, 010, …Q2Q1Q0 010, 101, 110, 001, 000, 111, 100, 011, 010, …

Number of FF: 3

N t t t d it ti t blNext state and excitation table:


3. Synchronous counter: Not full counter: how to design? 2 methods

How to design? m< 2exp(n)St t i t d i d i i f F ll C t State in counter: design as design in case of Full Counter

State not in counter (not-used state): 2 design-methods+ Method 1: Next state of Not-used state is “X”+ Method 1: Next state of Not-used state is X+ Method 2: Next state of Not-used state is any State in counter. Example: Design synchronous counter by using T-FF, Preset and p g y y g ,

Clear signal: are active “high”


3. Synchronous counter: Not full counter: how to design? Method 1

Using method 1: Next state of Not-used state is “X”

+

+

+


+


Using method 1: Next state of Not-used state is “X”


Must use RS (Reset) to initiate counter: Q2Q1Q0 = 001


Using method 2: Next state of Not-used state is any State in counter

etc


3. Synchronous counter: Not full counter: how to analyze?

Analyze a specified counter:Draw state diagramDraw state diagram

steps: + Excitation function from circuit+ Next state table

+ State diagram

Example:


3. Synchronous counter: Not full counter: how to analyze?

Excitation functions:


QUIZ: counter

Please choose which one you like.1. JK-FFCounter 3-bit Gray codeQ2Q1Q0 = 000 001 011 010 110 111 101 100 000Q2Q1Q0 = 000, 001, 011, 010, 110, 111, 101, 100, 000, …2. Counter: 0,2,4,6,8,0Design a counter: 12-10-8-6-4-2-0-1-3-5-7-9-11. Please show your work (desgin steps, draw state transition diagram,…)Use T-FF.Use J-K FF.

Design a counter: 12-10-8-6-4-2-0-1-3-5-7-9-11. Please show your work (desgin steps, draw state transition diagram,…)Use T-FF.U J K FF


Use J-K FF.

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