Chapter 7: Addressing Reliability in Physical Design
Transcript of Chapter 7: Addressing Reliability in Physical Design
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Chapter 7: Addressing Reliability in Physical Design
7.1 Parasitic Effects in Silicon
7.2 Surface Effects
7.3 Interconnect Parasitics
7.4 Overvoltage Protection
7.5 Migration Effects in Metal
Chapter 7: Addressing Reliability in Physical Design
1
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Chapter 7: Addressing Reliability in Physical Design
7.1 Parasitic Effects in Silicon7.1.1 Substrate Debiasing7.1.2 Injection of Minority Carriers7.1.3 Latchup7.1.4 Breakdown Voltage aka Blocking Capability of p-n Junctions
7.2 Surface Effects7.2.1 Parasitic Channel Effects7.2.2 Hot Carrier Injection
7.3 Interconnect Parasitics7.3.1 Line Losses7.3.2 Signal Distortions7.3.3 Crosstalk
7.4 Overvoltage Protection7.4.1 Electrostatic Discharge (ESD)7.4.2 Antenna Effect
7.5 Migration Effects in Metal7.5.1 Electromigration7.5.2 Thermal Migration7.5.3 Stress Migration7.5.4 Mitigating Electromigration7.5.5 Mitigating Thermal and Stress Migration
2
Chapter 7: Addressing Reliability in Physical Design
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Chapter 7: Addressing Reliability in Physical Design
Substratepotential
0 V
ΔV
Substrate contact (p+)Substrate
Oxide
Substrate current injector
Wire of net “SUB”
Bondpad “GND”
Bond wire
Die
XY
X
Substratecurrent
Rsub1 Rsub2
Isub = Isub1 + Isub2
Isub1 Isub2
Substratecurrent
Rcont Rcont
3
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Chapter 7: Addressing Reliability in Physical Design
Isub
NPN in saturation
p+-substrate
p–-epi
n-well n-well
Place p+ contactas near as possible! Negligible Moderate
Parasitic resistances in Isub path: High
Wire of net “SUB”
Oxide
Holes =
+ + +
JI diode
n-doped bulk siliconn- n+
p- p+ p-doped bulk silicon
Oxide (SiO2)
Metal (wire)
Ref. A
Ref. B
4
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Chapter 7: Addressing Reliability in Physical Design
p+-Substrate
p--EpiVictim
Oxide
(4) Electrons diffuse(3) Culprit emits electrons
Victim
IV
(1) External pull down below ground
Space-charge regions (attract electrons)
(5) Victims (other n-wells) collect electrons
Pad
VictimCulprit
(2) Forward bias
5
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Chapter 7: Addressing Reliability in Physical Design
Guard rings
P--Epi
GND rail
VDD rail
Bondpad
Agressive
n-well
(injector)
Electron-collecting guard
ring (NSD) tied to VDD
Hole-providing guard
ring (PSD substrate
contacts) tied to GND
n-buried layer
Deep-n+
NSD NSD
n-well
p--epi
p+-sub
STI
Space-
charge
regions
CMOS BiCMOS
Space-charge region
Highest
possible
potential
6
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Chapter 7: Addressing Reliability in Physical Design
NMOS-FET
p-sub
DS GB
Pull down below VSS
D SG B
IN
OUT VDDVSS
QNPN
QPNP
Rsub Rwell
Latch uptrigger
Pull up aboveVDD (or n-well)
Edges from IN feed through to OUT
Parasitic circuit
PMOS-FET
CDBN CDB
P
In Out
VDD
VSS
Intendedcircuit VDD
VSS
OUTOUT
CDBP
QNPN
Rwell
QPNP
Rsub
CDBN
n-wellCJI
CJI
n-doped bulk siliconn- n+
p- p+ p-doped bulk silicon
Oxide (SiO2)
Poly (gate)
7
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Chapter 7: Addressing Reliability in Physical Design
PMOS region NMOS region
n-well tie-down
(VDD)
p-sub tie-down
(VSS)
NSD
PSDDS
Backgate contacts laid out as guard rings
D
G G
PMOS-FET NMOS-FET
n-well tie-down p-sub tie-down
S
Metal1Poly
Cont
Active
n+ (NSD)
p+ (PSD)
8
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Chapter 7: Addressing Reliability in Physical Design
n-well n-well
p-epi
VDD1 VDD2
High potentialPoly
GND
Parasitic NMOS channel
Poly
n-well
Base
p-sub or p-epi
GNDVDD
Low potential
Parasitic PMOS channel
STI (FOX) STI
Metal1 Metal1
ILOILO
(FOX)
9
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Chapter 7: Addressing Reliability in Physical Design
Parasiticp-channel
Intendedp-channel
Enlarging n-wellstops parasiticp-channel to p-sub
Metal1 forms thickerparasitic gate oxide(method 2)
NSD forms channelstopper (method 3)
Extension ofchannel stopper
p-sub
NwellPSDPoly
ActiveMetal1
ContactNSD
GS/B
D
10
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Chapter 7: Addressing Reliability in Physical Design
n-well
n-well
n-well
PSD-channel stop rings
n-well
Poly-channel stop rings
GND tie down (p-sub contact)VDD tie down (n-well contact)
Metal1 (parasitic gate)
Poly channel stops
No channelsParasiticchannels
Metal1
11
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Chapter 7: Addressing Reliability in Physical Design
Impact ionizationgenerates electron-hole-pairs
Source
Gate
High electric fieldin pinched-off regionproduces hot electronsElectric field
Substrate currentSpace-charge region
Drain
Channel Lower electric fieldin pinched-off region
Lightly doped drain (LDD)
DrainWith LDD
n-doped bulk siliconn- n+
p- p+ p-doped bulk silicon
Oxide (SiO2) Metal Poly
12
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Chapter 7: Addressing Reliability in Physical Design
L RC
1G
R CIC
Conductor
Oxide(s)
Substrate
VbVe
VR
R
I
13
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Chapter 7: Addressing Reliability in Physical Design
CplateCfringe Cfringe
ClatClat
C
Cvert
C
Substrate
Metal3
Metal2
Metal1
(a) (b) (c) (d) (e)
Shielded wire
SW SWSW
14
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Chapter 7: Addressing Reliability in Physical Design
t t
t
t
t
t
Source Receiver
Noise
t
t
15
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Chapter 7: Addressing Reliability in Physical Design
Touch
Accidental short
Protected circuit>1 kV Shunt path
>10 MVLightning rod
16
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Chapter 7: Addressing Reliability in Physical Design
Op
erat
ing
ran
geo
fvu
lner
able
dev
ice
Safe
ty m
argi
n
Des
tru
ctio
no
fvu
lner
able
dev
ice
Voltage
Imax
Current VDDESD design
window Vdes
Ron↓
Vt1Vh VBD
17
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Chapter 7: Addressing Reliability in Physical Design
Pj
VSS
VDD
ESD protection circuit
Integrated circuit (chip)
Accidentalshorts
DDi
DSi
DDj
DSj
DDSProtectedcircuit
PDPPPS
NDNPNS
Supplyclamp
Pi
Vzap
+
-
18
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Chapter 7: Addressing Reliability in Physical Design
Ground railVSS
Metal2
Bond pad
Supply railVDD
Metal2
Metal1
DS anode
DS cathode
DD cathode
DD anode
ESD currentESD current
ESD
cu
rren
t
ESD
cu
rren
t
ESD diode DS ESD diode DD
Vias and contacts
P-active“donut”in P-epi
N-active“donut”in N-well
P-activeN-active
PD, PP, PS modes
ND, NP, NS modes
Pad connection to IC core
Contacts only
19
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Chapter 7: Addressing Reliability in Physical Design
2-stage ESD protection Protected circuit
D1
Inputpad
D2
R
V1 V2
VRI1
I2 I≈0
VSS
…
Zener diode ggNMOS
Examples of ESD devices D1, D2:
Rbal
Q
Rsub
Inputpad
DS GB
QRsub
Rbal
20
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Chapter 7: Addressing Reliability in Physical Design
Metal1
Ground rail: VSS Supply rail: VDD
Bond pad
Primary ESD protection
device D1
(ggNMOS)
Metal2
Contacts only Metal1 = Bond pad
Contacts and vias Metal2 = VSS
Resistor R(poly)
SecondaryESD protectiondevice D2
(ggNMOS)
Ballasting resistor Rbal
10 vias
BSG
D
Smoothly bent edges
I1 I2
I1 + I2
Clampingvoltage V1
VR
Pad connection to IC core
21
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Chapter 7: Addressing Reliability in Physical Design
1 2 3
10 9 8 7
11
4
5
6
V1
12
G1 1 2 47
8
V1
10
G1
G2
V2
11 5 9G3
3
12
V3
6
Ground pad (VSS)
Ground rail
Power supply clamp
Power supply pad (VDD)
Power rail
ESD-diodes
Signal pads
Power
domain
2
Power
domain 1
Power
domain 3
Single power domain Multiple power domains
22
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Chapter 7: Addressing Reliability in Physical Design
Antenna
Metal 1
Poly
Thin gate oxide (GOX)
Gate
Antenna
Poly
Thin gate oxide (GOX)
GateInterconnect
FOX (STI)
Interconnect
Not processed yet
23
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Chapter 7: Addressing Reliability in Physical Design
(p)-substrate
(1) Poly etch
Poly silicon
Gate oxide (GOX)
Photo resist
RIE plasma
(2) Poly etch (3) Resist ashing (4) Resist ashing
Charges
24
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Chapter 7: Addressing Reliability in Physical Design
Substrate
Bulk
High surfacecharge density qGB
GOX
Gate
Low surfacecharge density qPS
Poly
STI (FOX)
Agate = w·lgate
Aant = w·lant
w
lgate
dFOX
dGOXCPS
CGB
V
2 4 8 16 32 64 128 256 512
2
4
8
16
32
64
128
256
α = Aant / Agate
V(α) / V(1)
β = 200
β = 100
β = 50
β = dFOX / dGOX
lant
Nearly linear !
Pant = 2(w+lant)
11
25
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Chapter 7: Addressing Reliability in Physical Design
Long poly antenna
Short poly antenna
Metal1 jumper
Long metal1 wire acting as antenna
Jumper in upper (top) metal layer
Long metal1 wire not acting as antenna
26
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Chapter 7: Addressing Reliability in Physical Design
NSD
(a)
Forward
biased Reverse biased(leakage current)
V
PSD N-well
Forward biased
PSD
(b)
+ _Charge
Antenna
27
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Chapter 7: Addressing Reliability in Physical Design
Interaction of electric field on metal ions
Force on metal ions (Cu+) resulting from momentum transfer from the conduction electrons
Anode
+Cathode
-E
Fwind Ffield<<
-Cu+
- -
-
28
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Chapter 7: Addressing Reliability in Physical Design
Line Depletion
Metal2 Cu
Metal1 Cu
Via DepletionTa/TaNliner layer(metal liner)
Low-kdielectric
SiN, NSiCcap layer
Void
Metal2 Cu
Metal1 Cu
Void
-
-
29
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Chapter 7: Addressing Reliability in Physical Design
Temperature
Vacancy
Atom
30
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Chapter 7: Addressing Reliability in Physical Design
Mechanical stress σ
Vacancy
Atom
Tensile stress
Compressive stress
31
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Chapter 7: Addressing Reliability in Physical Design
Vacancy
Atom
Tensile stress Compressive stress
32
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Chapter 7: Addressing Reliability in Physical Design
Vacancy
Atom
Tensile stress Compressive stress
Void nucleation (“crack”)eliminates tensile stress 33
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Chapter 7: Addressing Reliability in Physical Design 34
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Chapter 7: Addressing Reliability in Physical Design 35
– +
Void
Cap Layer
Liner Layer
Metal (Cu)Metallic Barrier (Liner)Dielectric Passivation (Cap Layer)
– +
Void
Via-below Via-above
--
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Chapter 7: Addressing Reliability in Physical Design
✔ ✔
min
max
Currentdensity
36
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Chapter 7: Addressing Reliability in Physical Design
min
max
Currentdensity
37
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Chapter 7: Addressing Reliability in Physical Design
RMST net topology Trunk net topology Current-optimizednet topology
38