Chapter 5 Embedded Core Test Fundamentals 1web.cecs.pdx.edu/~greenwd/ch05art.pdf · Design-for-Test...

Chapter 5 Embedded Core Test Fundamentals

1

Design-for-Test for Digital IC’s and Embedded Core Systems

Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved


Figure 5-1 Introduction to Embedded Core Test and Test Integration

Core 1

Embedded

JTAG Boundary Scan

PLL TAPMemory

Core 2

Core 3

TCU

EmbeddedMemory

Core 4 Core 5

GeneralLogic

Chip-Level

Memory Access


2



Figure 5-2 What is a CORE?

WHAT IS A CORE?

HDLModel with

No Test

HDLModel with

Modeled Test

RTLModel with

No Test

RTLModel with

Modeled Test

SOFT

Gate-LevelNetlist with

No Test

Gate-LevelNetlist with

Synthesized Test

Gate-LevelNetlist withInserted Test

Gate-LevelNetlist withMixed Test

FIRM

LayoutGDSII with

No Test

Layoutwith Test from

Synthesis

Layoutwith Test from

Gate-Level

Layoutwith Test

Optimization

HARD


3



Figure 5-3 Chip Designed with Core

Chip-Level

UDL Core

Wrapper

CTCU

JTAG Boundary Scan

PLL

TMode[3:0]

EmbeddedMemories

EmbeddedMemories

TAP

- A Core-Based Device May Include -

1. Core(s) with Test Wrapper + Embedded Memory Arrays2. Chip-Level User Defined Logic + Embedded Memory Arrays3. Chip-Level Test Selection and Control Logic4. Dedicated Chip-Level Test Pins5. Chip-Level Clock Generation and Clock Control Logic6. IEEE 1149.1 Controller and Boundary Scan Logic

12

3

4

5

6


4



Figure 5-4 Reuse Core Deliverables

1. The Core

2. The Specification or Data Sheet

A ReuseEmbeddable

Core

3. The Various Models

4. The Integration Guide

5. The Reuse Vectors

Business Deliverables


5



Figure 5-5 Core DFT Issues

CORE-BASED DESIGN DFT ISSUES

A KNOWNEXPECTEDRESPONSE

A KNOWNSTIMULUS

ACCESSTO THE

EMBEDDEDCORE

Chip-LevelDevice

• If the Core is HARD — DFT must exist beforedelivery — how is access provided at the chip level?

• If the Core is HARD — and delivered with pre-generatedvectors — how are vectors merged in the whole test program?

• If the Core is HARD — and part of the overall chip testenvironment — how is the core test scheduled?

• If the Core is HARD — and part of the overall chip testenvironment — what defaults are applied when not active?

• If the Core is SOFT — is the overall chip test environmentdeveloped as a Core and UDL or as a unified design?

• If the Core is HARD — what is the most economical andeffective test mix — Scan? LBIST? MBIST? Functional?

OtherChip-Level Logic

• If the Core operates at a different frequency from the pinI/O or other chip logic — how does this affect DFT and Test?


6



Figure 5-6 Core Development DFT Considerations

• DFT Drivers During Core Development

Target Market/business — Turnkey versus Customer Design

• Design For Reuse Considerations

Reference Clocks — Test and FunctionalTest Wrapper — Signal Reduction/No JTAG/No Bidi’s

• Core Test Architectures and Interfaces

Direct Access — Mux Out Core TerminalsAdd-On Test Wrapper — Virtual Test SocketInterface Share-Wrapper — Scanned Registered Core I/O

Dedicated Core Test Ports — Access Via IC Pins

A ReuseEmbeddable

Core

Target Cost-Performance Profile — Low to HighPotential Packages — Plastic versus CeramicPotential Pin Counts

At-Speed Scan Or Logic Built-in Self-test (LBIST)

Virtual Test Socket — Vector Reuse


7



Figure 5-7 DFT Core Interface Considerations

• Core DFT Interface Considerations

I/O port count less restrictive than IC pin count

Access to core test ports via IC pins (integration)

A Chip Package with44 Functional Signals

A ReUseEmbeddable

Core with60 Functional

Signals

Note — none of this is known a priori

- Dedicated test signals to place in test mode

- Number of test signals needed to test core

Impact of routing core signals to the chip edge

- Frequency requirements of test signals


8



Figure 5-8 DFT Core Interface Concerns

UDL LogicEmbedded

Core

D Q

DQ

D Q

DQ

UDLDomain

COREDomain

At the time of Core Development,the UDL logic is not availableand i’s configuration is not known

For example:- registered inputs or outputs- combinational logic- bidirectional signals or tristate busses

How are vectors generated for a HardCore before integration?

How are vectors delivered that canassess the signal timing or frequency?

How is test access planned to beprovided — through the UDL or directlyfrom the package pins?


9



Figure 5-9 DFT Core Interface Considerations

• Core DFT Interface Considerations

Wrapper as a virtual test socket (for ATPG)

A Chip Package with44 Functional Signals

Wrapper for interface signal reductionWrapper for frequency assessmentWrapper as frequency boundary

Note: bidirectional functional signals can’t

A ReuseEmbeddable

Core with60 Functional

Signals

Test Wrapper with 10 Test Signals

cross the boundary if wrapper or scan


10



Figure 5-10 Registered Isolation Test Wrapper

UDL LogicEmbeddedHard Core

“Land between the Lakes”The Isolation Test Wrapper

D Q

DQ

D Q D Q

DQ DQ

where the wrapper is the registeredcore functional I/F that is scan-inserted separately

D Q

D Q

D Q

UDL ScanDomain

CORE ScanDomain

Core-Wrapper ScanDomain

Note: Wrapper and core are on same clockand path delay is used to generate vectors


11



Figure 5-11 Slice Isolation Test Wrapper



D Q

DQ

D Q

D Q

DQ

DQ

where the wrapper is an added “slice”between the core functional I/F

and the UDL functional I/F

DQ

D Q

UDL ScanDomain

CORE ScanDomain

Wrapper ScanDomain

Wrapper and core are on different clocksand path delay is used to generate vectors


12



Figure 5-12 Slice Isolation Test Wrapper Cell



D Q

DQ

D Q

DQ

the wrapper is an added “slice”between the core functional I/F

and the UDL functional I/F

D Q

UDL ScanDomain

CORE ScanDomain

Wrapper ScanDomain

Wrapper and core are on different clocksand path delay is used to generate vectors

TR_SDI

D Q

Core_Test

TR_Mode

TR_SDO

TR_SE TR_CLK

System Clock


13



Figure 5-13 Core DFT Connections through the Test Wrapper



DQ DQ

D Q

D Q

UDL ScanDomain

CORE ScanDomain


Internal Scan In

DQInternal Scan Out

D QInternal BIST In

DQInternal BIST OutDirect Test

Signals goto Package

Pins

Wrapper Scan In

All Core Test Interface Signals pass through theTest Wrapper without being acted upon

All Core I/O are part of the Wrapper Scan ChainSo Total Core Test I/F is:

Internal ScanInternal MBISTWrapper Scan

DQ


14



Figure 5-14 Core DFT Connections with Test Mode Gating



DQ DQ

D QUDL ScanDomain

CORE ScanDomain


Test Mode Control

D QInternal BIST In

Internal Scan InDirect TestSignals Goto Package

Pins

Wrapper Scan In

All Core Test Interface Signals pass through theTest Wrapper and may be acted upon by a Test Mode

All Core I/O are part of the Wrapper Scan ChainSo Total Core Test I/F is:Gated Internal ScanGated Internal MBISTGated Wrapper Scan

DQ

Core TestController

D Q


15



Figure 5-15 Other Core Interface Signal Concerns

• DFT ConsiderationsCan’t Support Bidirectional Core Ports

Input and Reference Clocks

Test Wrapper CoreUDL

Wrapper Cell

A ReuseEmbeddableHard Core

with Pre-ExistingClock Trees

PLL Clock OutSignal(s)

BypassTest Clock

Mul/DivClocks

Can’t Usethe

WrapperCell


16



Figure 5-16 DFT Core Interface Frequency Considerations

• Core DFT Frequency Considerations

Wrapper as a multi-frequency ATPG test socket

A Chip Package witha 25 MHz Interface

Wrapper for frequency boundaryTest signals designed for low frequencyPackage interface designed for high frequency

Note: functional high/low frequency signals can

A ReuseEmbeddable

Core withFmax = 100MHz

Logic

Test Wrapper with 10 Test Signals

cross the wrapper—the test I/F is the concern


17



Figure 5-17 A Reuse Embedded Core’s DFT Features

• Core DFT Goals and Features

Reuse of Core Patterns Independent of Integration

Test Insulation from Customer Logic

Embedded Core I/O Timing Specifications with Wrapper

Minimize Test Logic Area Impact

Minimize Test Logic Performance Penalty

Full-Scan Single-Edge Triggered MUX DFFTristate Busses - Contention/Float PreventionNegedge Inputs and Outputs

Iddq—No Active Logic and Clock Stop Support

- Bitmap Characterization Support

A ReuseEmbeddable

Core withExisting DFT

and Test Features

A Test Wrapper

Embedded Memory Test by MBIST- Few Signals — High Coverage — Less Test Time

Structure by Stuck-At Scan

Frequency by At-Speed Scan (Path & Transition Delay)

- High Coverage — Fewer Vectors — Ease of Application

- Deterministic — Fewer Vectors — Ease of Application

DFT Scannability Logic

Internal Scan Data InInternal Scan EnableWrapper Scan Data InWrapper Scan EnableWrapper Test EnableMemBIST InvokeMemBIST RetentionMemBIST BitmapInternal Scan Data OutWrapper Scan Data OutMemBIST FailMemBIST DoneMemBIST Bitmap Out

The Core’s Test Port


18



Figure 5-18 Core Test Economics

• Core Economic Considerations

Core Test Program Time/Size/Complexity (Tester Cost)

Test Integration (Time-to-Market)

Core Area and Routing Impact (Silicon/Package Cost)

Core Power and Frequency Impact (Package/Pin Cost)

ChipTest

ProgramBudget(s)

Time

TesterMemory

and/or

Tota

l

Chip Parametrics

Memory Testing

Retention Testing

Chip Logic Testing

Embedded Core Testing

A ReuseEmbeddable

Core withExisting DFT

and Test Features

A Test Wrapper

Internal Scan Data InInternal Scan EnableWrapper Scan Data InWrapper Scan EnableWrapper Test EnableMemBIST InvokeMemBIST RetentionMemBIST BitmapInternal Scan Data OutWrapper Scan Data OutMemBIST FailMemBIST DoneMemBIST Bitmap Out

The Core’s Test Port


19



Figure 5-19 Chip with Core Test Architecture

Chip-Level

UDL Core

Wrapper

CTCU

JTAG Boundary Scan

PLL

TMode[3:0]

EmbeddedMemories

EmbeddedMemories

TAP

- A Core-Base Device May Include -

Core(s) with Test Wrapper and Embedded Memory ArraysChip-Level Non-Core Logic with Embedded Memory Arrays

Chip-Level Test Selection and Control LogicDedicated Chip-Level Test Pins

Chip-Level Clock Generation and Control LogicIEEE 1149.1 Controller and Boundary Scan Logic


20



Figure 5-20 Isolated Scan-Based Core-Testing

Chip-Level

UDL Core

CTCU

JTAG Boundary Scan

PLL TAP

Pre-ExistingVectors

Test Selection

Clock Bypass

Wrapper andCore Scan

Package PinConnections


21



Figure 5-21 Scan Testing the Non-Core Logic

Chip-Level

UDL

CTCU

JTAG Boundary Scan

PLL TAP

DevelopmentGenerated Vectors

Test Selection

Clock Bypass

Wrapper andUDL Scan



22

Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved

Figure 5-22 Scan Testing the Non-Core Logic

Chip-Level

UDL

CTCU

JTAG Boundary Scan

PLL TAP


I/O specification testing—bus_SETristate busses - contention/float prevention

Iddq—HighZ pinPin requirements—(open drains)

Test Selection

Clock Bypass

Wrapper andUDL Scan


Chapter 5 Embedded Core Test Fundamentals 23


Figure 5-23 Memory Testing the Device

Chip-Level

UDL Core

Wrapper

CTCU

JTAG Boundary Scan

PLL

EmbeddedMemories

EmbeddedMemories

TAP


Test Selection

Clock Bypass



Figure 5-24 DFT Integration Architecture

Core 1

Embedded

JTAG Boundary Scan

PLL TAPMemory

Core 2

Core 3

CTCU

EmbeddedMemory

Core 4 Core 5

GeneralLogic

Chip-Level

Memory Access

• Chip-level DFT integration considerations

2. Frequency/Data Rate of Test Vectors1. Power Rating during Test

each core/vector set must have:

3. Fault Coverage of the Test Vectors4. Required Test Architecture to Reuse Vectors5. ATPG Test Wrapper or Encrypted Sim Model6. The Vector Set’s Format7. The Vector Set Sizing



Figure 5-25 Test Program Components

Chip ParametricsChip Iddq (Merged)Core 1 Test ComponentsCore 2 Test ComponentsCore 3 Test ComponentsChip-Level MemoryChip-Level Analog

Core 1 ComponentsCore 1 IddqCore 1 ScanCore 1 Memory TestCore 1 Analog

# of Cores

TestTimein (s)

1 2 3 4



Figure 5-26 Selecting or Receiving a Core

• Driven by Fab and Integration Requirements

• Core DFT Specification Items

- Test Mix

- Style of Test

• Receiving Core DFT Specification

- Maximum Number of Integration Signals

- Maximum Vector Sizing

- Minimum Fault Coverage

- Clock Source

- Minimum-Maximum Test Frequency



Figure 5-27 Embedded Core DFT Summary

• Two Concerns: Reuse and Integration

• Reuse: Interface, Clocks, Test Features- number of dedicated test signal- size of test integration interface

• Core Test Driven by Cost-of-Test and TTM

- ability to test interface timing

- specifications and vectors based on clock-in- specifications and vectors based on clock-out- ability to stop clock for retention or Iddq

- no functional bidirectional ports

- number of clock domains- at-speed full scan- at-speed memory BIST- use of a scan test wrapper- self-defaulting safety logic

• Integration: Core Connections, Chip Test Modes- simple core integration- reuse of pre-existing vectors- application of test signal defaults- shared resources (pins and control logic)- shared testing (parallel scheduling)- chip level test controller

Chapter 5 Embedded Core Test Fundamentals 1web.cecs.pdx.edu/~greenwd/ch05art.pdf · Design-for-Test...

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