EE 335 : Advanced Microprocessor

ChapterChapter--55Logic Design with Behavioral Models of Logic Design with Behavioral Models of

Combinational and Sequential LogicCombinational and Sequential Logic

Ajay Kumar YadavAjay Kumar Yadav(Instructor)(Instructor)

Electrical & Computer EngineeringElectrical & Computer EngineeringTemple UniversityTemple University

Data Types for Behavioral Modeling:Data Types for Behavioral Modeling:

Data types are classified in two categories:Data types are classified in two categories:Nets (wire) : establish connectivity between Nets (wire) : establish connectivity between design objects.design objects.Register (reg) : similar to variable in ordinary Register (reg) : similar to variable in ordinary procedural language, stores the information procedural language, stores the information while the program executes.while the program executes.Integer : word length depends on the type of Integer : word length depends on the type of computer. computer.

Nets:Nets:

Net TypesNet Types

wirewire Establish connectivity, No Logical behavior or Establish connectivity, No Logical behavior or functionality implied.functionality implied.

tritri Establish Connectivity like wire, used to indicate Establish Connectivity like wire, used to indicate three stated in hardware.three stated in hardware.

wandwand Connected to the output of multiple primitives, Connected to the output of multiple primitives, implementation of wired AND. implementation of wired AND.

worwor Connected to the output of multiple primitives, Connected to the output of multiple primitives, implementation of wired OR.implementation of wired OR.

Register Variables:Register Variables:regreg : hardware storage element. Default size is single bit : hardware storage element. Default size is single bit and default value is “and default value is “xx”.”.integerinteger: supports numeric computation in procedural : supports numeric computation in procedural statements. Word length depends upon the host statements. Word length depends upon the host machine. Default initial value is “machine. Default initial value is “00”. Assigned value ”. Assigned value must be decimal equivalent.must be decimal equivalent.realreal: A 64 bit value stored in double precision. Default : A 64 bit value stored in double precision. Default initial value is “initial value is “0.00.0”. ”. $$realtobitsrealtobits and and $$bitstorealbitstoreal syntax syntax are used to convert data types to permit real data are used to convert data types to permit real data transfer.transfer.Constants: A constant is declared with the keyword Constants: A constant is declared with the keyword parameterparameter. Constant can be a integer, real number or . Constant can be a integer, real number or reg type.reg type.

Two Dimensional Array:Two Dimensional Array:

reg [31:0] memory [0:256]

Word size Memory size

User Defined Name

Two channel Mux with 32Two channel Mux with 32--bit Datapath:bit Datapath:

Propagation Delay & Continuous Propagation Delay & Continuous Assignments:Assignments:

Verilog Counterparts:Verilog Counterparts:

VerilogDescription

Logic Description

Circuit Schematic

StructuralModel

Truth Table User-DefinedPrimitives

Boolean Equations

ContinuousAssignments

Cyclic Behavioral Models:Cyclic Behavioral Models:

Model edge sensitive functionality (e.g. posedge or Model edge sensitive functionality (e.g. posedge or negedgenegedge of clock).of clock).Cyclic Behavior is abstract Cyclic Behavior is abstract –– do not use hardware to do not use hardware to specify signal values.specify signal values.Do not expire after the execution of last procedural Do not expire after the execution of last procedural statements.statements.Execution can be unconditional or can be governed by Execution can be unconditional or can be governed by an optional event control expression.an optional event control expression.Capable of modeling both edge sensitive and level Capable of modeling both edge sensitive and level sensitive behavior.sensitive behavior.

Continuous-assignment statement are limited to level sensitive modeling

Cyclic Behavior & Edge Detection:Cyclic Behavior & Edge Detection:

Always activate at the beginning of the simulation.Always activate at the beginning of the simulation.Delay control operator and event control operator Delay control operator and event control operator control the execution.(control the execution.(#,@#,@))posedgeposedge and and negedgenegedge are the two event control expressions are the two event control expressions used for rising edge and falling edge respectively.used for rising edge and falling edge respectively.After a complete execution of cyclic behavior, the After a complete execution of cyclic behavior, the computational activity flow return to the computational activity flow return to the alwaysalwayskeyword.keyword.If a procedural statement has both delay and event If a procedural statement has both delay and event control expression, the activity will wait for the control expression, the activity will wait for the indicated time and then test for event control indicated time and then test for event control expression. expression.

ContinuousContinuous--Assignment Models:Assignment Models:

Compare_32A A_gt_B

A_lt_BB A_eq_B

module compare_32 (A_gt_B, A_lt_B, A_eq_B, A, B) ;parameter size=32 ;input [size-1:0] A, B;output A_gt_B, A_lt_B, A_eq_B ;

assign A_gt_B = (A>B),A_lt_B= (A<B), A_eq_B = (A==B) ;

endmodule

Dataflow/RTL Models:Dataflow/RTL Models:

Describes concurrent operations on signals in a Describes concurrent operations on signals in a sequential machine. sequential machine. The computations are initiated at the active edge The computations are initiated at the active edge of clk and completed in a time to be stored in a of clk and completed in a time to be stored in a register at the next active edge.register at the next active edge.RTL model are written for a specific architecture RTL model are written for a specific architecture :that is, the registers, data paths and machine :that is, the registers, data paths and machine operations and their schedule are known a operations and their schedule are known a priori. priori.

Blocking and NonBlocking and Non--Blocking Operator:Blocking Operator:

Ordinary procedural assignment operator “Ordinary procedural assignment operator “==”, stores the ”, stores the value immediately after the statement execution and value immediately after the statement execution and before the next statement can execute. Also called as before the next statement can execute. Also called as Blocking assignment operator.Blocking assignment operator.

“If there is data dependencies among the variables, outcome may “If there is data dependencies among the variables, outcome may get get affected.”affected.”To avoid such cases NonTo avoid such cases Non--Blocking assignment “Blocking assignment “<=<=” ” operator is generally used. It effectively executes the operator is generally used. It effectively executes the statement concurrently rather than sequentially.statement concurrently rather than sequentially.

Example(4Example(4--bit serial shift register):bit serial shift register):module shiftreg_BA(A,E, clk, rst);

input E, clk, rst;output A;reg A, B, C, D;always @(posedge clk or posedge rst)begin

if (rst)begin A=0; B=0; C=0; D=0; end

else begin D=E; C=D; B=C; A=B; end

end

always @(posedge clk or posedge rst)begin

if (rst)begin A=0; B=0; C=0; D=0; end

else begin D<=E; C<=D; B<=C; A<=B; end

end

endmodule

Simulation Result:Simulation Result:

“Blocking Operator”

“Non-Blocking Operator”

AlgorithmAlgorithm--Based Models:Based Models:

Algorithms based models are abstract in nature.Algorithms based models are abstract in nature.It defines the sequence of procedural It defines the sequence of procedural assignment within a cyclic behaviour, the assignment within a cyclic behaviour, the execution of statement determines the storage execution of statement determines the storage variable and output of the machine.variable and output of the machine.Eliminates the need of a priori architecture.Eliminates the need of a priori architecture.Algorithm model execute sequentially, without Algorithm model execute sequentially, without an explicit architecture. an explicit architecture.

“Not all Algorithms can be implemented in hardware”

Linear Feedback Shift Register:Linear Feedback Shift Register:

Reset

RD S

Clk

RD S

Clk

RD S

Clk

RD S

Clk

+ + +

C1C3 C2

Y[4]Y[1] Y[2] Y[3]

Clock

• Used in data-compression circuits implementing a signature analysis technique called cyclic redundancy check.

• C1, C2, C3 are binary tap coefficients, which determine whether Y[N] is fed back to a given stage of the register.

•Vector of tap coefficients characterize polynomial of LFSR and its cyclic nature.

Verilog code of LFSR:Verilog code of LFSR:module LFSR (Y, clk, rst);

parameter length=8;parameter in_state =8'b10010001;parameter [1:length] tap=8'b11001111;input clk, rst;output [1:length] Y;reg [1:length] Y;

always @(posedge clk)begin

if(rst==0) Y<=in_state;else

begin Y[1]<=Y[8];Y[2]<=tap[7]?Y[1]^Y[8]:Y[1]; Y[3]<=tap[6]?Y[2]^Y[8]:Y[2];Y[4]<=tap[5]?Y[3]^Y[8]:Y[3];Y[5]<=tap[4]?Y[4]^Y[8]:Y[4];Y[6]<=tap[3]?Y[5]^Y[8]:Y[5];Y[7]<=tap[2]?Y[6]^Y[8]:Y[6];Y[8]<=tap[1]?Y[7]^Y[8]:Y[7];

endend

endmodule

Simulation result of LFSR:Simulation result of LFSR:

Digital Machines with Repetitive Algorithms:Digital Machines with Repetitive Algorithms:

*** Data movement in LFSR for multiple cycles ***

Loop Constructs in Verilog: Loop Constructs in Verilog: for loopfor loop::

for( initial_stat; control_exp; index _stat)for( initial_stat; control_exp; index _stat)repeat loop:repeat loop:

repeat ( N)repeat ( N)while loopwhile loop::

while (expression)while (expression)forever loop:forever loop:

causes unconditional repetitive execution of causes unconditional repetitive execution of statements, subject to the statements, subject to the disabledisable statement. statement.

*** repeat can also be terminated by a disable statement ***

Example for Example for forfor loop:loop:

*** Verilog code for multiple cycle in LFSR ***

Intellectual Property Reuse:Intellectual Property Reuse:

count =0;temp_reg = data; // storing the data word in temp register

while (temp_reg)begin

if (temp_reg [0] ) count =count+1;temp_reg = temp_reg >> 1;

end

while (temp_reg)begin

count =count + temp_reg[0];temp_reg = temp_reg >> 1;

end

*** while loop will execute till the time temp register is not equal to zero ***

Difference between Difference between foreverforever & & always always ::

alwaysalways declares a concurrent behaviour whereas declares a concurrent behaviour whereas foreverforever loop is a computational activity flow and used loop is a computational activity flow and used within the behaviour only.within the behaviour only.foreverforever loop can be nested whereas loop can be nested whereas alwaysalways cannot be cannot be nested.nested.foreverforever loop executes within a sequential activity flow, loop executes within a sequential activity flow, whereas whereas alwaysalways becomes active and execute at the becomes active and execute at the beginning of the simulation.beginning of the simulation.To stop the To stop the foreverforever loop loop disabledisable is required but is required but alwaysalwaysautomatically stops at the end of the simulation. automatically stops at the end of the simulation.

Example of Example of disabledisable construct :construct :output [3:0] index;input [15:0] word;input trigger;reg [3:0] index;

always @ (trigger)begin: search_1

index = 0;for ( index = 0; index <= 15; index = index+1 )

if ( word [index])disable search_1;

end

1. Execution of disable allows the simulator to come out of the loop.

2. If there is named block after the disable, it will prematurely terminate the named block of procedural statement

Tasks:Tasks:Declared within a module and referenced only from Declared within a module and referenced only from within a cyclic or single pass behavior.within a cyclic or single pass behavior.Assigned parameters are associated with the declared Assigned parameters are associated with the declared input and output variables of the input and output variables of the tasktask..Additional local variables can be declared within a Additional local variables can be declared within a tasktask..tasktask must be named and all the declarations are local to must be named and all the declarations are local to the the tasktask..All the arguments to the All the arguments to the tasktask are passed by a value are passed by a value ––not by a pointer to the value.not by a pointer to the value.tasktask may have event control operator but not delay may have event control operator but not delay control operator.control operator.

Example of Example of tasktask ::module task_a (out, sum, in, data_a, data_b, clk, rst);

output [3:0] sum;output out;input [3:0] data_a, data_b ;input clk, rst, in;reg sum, out;

always @ (posedge clk or posedge rst)begin

if (rst) {out,sum}<=0;elseAdd(out, sum, data_a, data_b, in);task add;

output [3:0] sum;output out;input [3:0] data_a, data_b;input in;

begin {out,sum}<=data_a + ( data_b + in); endendtask

endendmodule

Functions:Functions:functionsfunctions are declared within a parent module are declared within a parent module and can be referenced in any valid expression.and can be referenced in any valid expression.functionfunction returns a value at the function’s returns a value at the function’s identifier.identifier.functionfunction cannot invoke cannot invoke tasktask and may not and may not contain a timing controls. ( contain a timing controls. ( @, #, wait @, #, wait ))functionfunction can call other functions but not can call other functions but not recursively.recursively.It may contain a declaration of input and local It may contain a declaration of input and local variables, but may not have declared output. variables, but may not have declared output.

Example of Example of functionfunction ::

module word_align (word_out, word_in);output [7:0] word_out;input [7:0] word_in ;

assign word_out = align_word(word_in);

function [7:0] align_word;input [7:0] word_in;begin

align_word = word_in;if (align_word!=0)

while (align_word[7]= = 0 )align_word = align_word<<1;

endendfunctionendmodule

ASM Charts for Behavioral Modeling :ASM Charts for Behavioral Modeling :

Algorithmic state machine (ASM) charts are an Algorithmic state machine (ASM) charts are an abstraction of the functionality of a sequential abstraction of the functionality of a sequential machine.machine.Display the computational activity as well as the Display the computational activity as well as the sequential steps that occur under the influence of sequential steps that occur under the influence of the machine’s input.the machine’s input.An ASM chart is organized into blocks using An ASM chart is organized into blocks using three fundamental elements: state box, decision three fundamental elements: state box, decision box and conditional box. box and conditional box.

ASM Chart for a Vehicle Speed Controller :ASM Chart for a Vehicle Speed Controller :

Brake has Priority over Accelerator

ASMD Chart :ASMD Chart :

Two stage Pipeline Register

ASM charts for an UpASM charts for an Up--Down Counter :Down Counter :

Up- down Counter with and without the conditional output boxes

Barrel Shifter :Barrel Shifter :

Used in digital signal processors to avoid Used in digital signal processors to avoid overflow problems by scaling the input and overflow problems by scaling the input and output of a output of a datapathdatapath operation.operation.Shifting the word to the right effectively divide Shifting the word to the right effectively divide the word by a power of 2 whereas shifting to the the word by a power of 2 whereas shifting to the left multiplies the word by a power of 2. left multiplies the word by a power of 2. It can be implemented using the combinational It can be implemented using the combinational logic as well as registered logic.logic as well as registered logic.

88--bit Barrel Shifter with Registered Output :bit Barrel Shifter with Registered Output :

Example of 32Example of 32--Word Register File : Word Register File :

assign Data_Out_1=Reg_file[Read_Addr_1];assign Data_Out_2=Reg_file[Read_Addr_2];always @ (posedge clock)begin

if (Write_Enable)Reg_file[Write_Addr]<=Data_in;

endendmodule

Keypad Scanner and Encoder :Keypad Scanner and Encoder :

Keypad Code for Hexadecimal Scanner :Keypad Code for Hexadecimal Scanner :Key Row [3:0] Col [3:0] Code0 0001 0001 00001 0001 0010 00012 0001 0100 00103 0001 1000 00114 0010 0001 01005 0010 0010 01016 0010 0100 01107 0010 1000 0111

8 0100 0001 10009 0100 0010 1001A 0100 0100 1010B 0100 1000 1011C 1000 0001 1100D 1000 0010 1101E 1000 0100 1110F 1000 1000 1111

ASM Chart for Keypad :ASM Chart for Keypad :

Text Bench Model for HexText Bench Model for Hex--Keypad :Keypad :

SignalGeneratorfor Keys

Row_Signal Grayhill 072Hex Keypad

CodeGenerator

Row[0]

Row[1]

Row[2]

Row[3]

XKey

16

Code[3]

Code[2]

Code[1]

Code[0]

Valid

Col [3]Col [2]

Col [1]Col [0]

***www.grahill.com***

Summary :Summary :Data types are broadly classified as net and wire.Data types are broadly classified as net and wire.Different systems can be implemented using Cyclic Different systems can be implemented using Cyclic Behavioral, Dataflow/RTL and Architectural based Behavioral, Dataflow/RTL and Architectural based model.model.Different loop constructs which Verilog supports are: Different loop constructs which Verilog supports are: forfor, , whilewhile, , repeatrepeat and and foreverforever..Verilog supports two types of subprograms:Verilog supports two types of subprograms:

Task create a hierarchical organization of the procedural Task create a hierarchical organization of the procedural statements within a verilog behavior.statements within a verilog behavior.Function substitute for an expression.Function substitute for an expression.

ASM charts are abstraction of the functionality of a ASM charts are abstraction of the functionality of a sequential machine and are used to model the behavior sequential machine and are used to model the behavior of the system.of the system.