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CHAPTER 4: TRANSISTORS

(24 MARKS)

4.1 INTRODUCTION:

Transistor is an electronic component semiconductor, has ability to

control the effective resistance by controlling the main signal (voltage

and amperage) from a distance.

There are two types of transistors, namely a Bipolar junction transistor

or abbreviated by BJT, such as PNP and NPN, and Unipolar transistor

junction transistor or abbreviated by UJT, such as FET and MOSFET.

4.2 BIPOLAR JUNCTION TRANSISTOR:

A transistor consists of two P-N junctions formed by sandwiching either

P-type or N-type semiconductor between a pair of opposite types as shown in

fig. below

There are two types of BJT’S namely

P-N-P TRANSISTOR.

N-P-N TRANSISTOR.

EMITTER (E):

It is the region situated in one side of transistor. This region supplies

charge carriers to the other two regions. The emitter region is heavily dopped

region, & the resistivity is very low.

The emitter region is always forward biased w.r.t. Base.

BASE (B):

It is the middle region that forms two P-N junctions in the transistor. The

base region is thin as compared to emitter and collector region. And is lightly

dopped region.

COLLECTOR (C):

It is a region situated in the other side of transistor (i.e. the side opposite

to the emitter), which collects charge carriers. The doping level of collector is

moderate (i.e. higher than BASE & lesser than EMITTER region).

The collector region is always reverse biased.

N P N P

N P E

C E

C

B B

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BJT SYMBOLS:

REGIONS OF OPERATION:

Forward-active (or simply, active): The base–emitter junction is forward

biased and the base–collector junction is reverse biased.

Reverse-active (or inverse-active or inverted): By reversing the biasing

conditions of the forward-active region, a bipolar transistor goes into

reverse-active mode. In this mode, the emitter and collector regions switch

roles.

Saturation: With both junctions forward-biased, a BJT is in saturation

mode and facilitates high current conduction from the emitter to the collector

(or the other direction in the case of NPN, with negatively charged carriers

flowing from emitter to collector). This mode corresponds to a logical "on",

or a closed switch.

Cutoff: In cutoff, biasing conditions opposite of saturation (both

junctions reverse biased) are present. There is very little current, which

corresponds to a logical "off", or an open switch.

B-E Junction

Bias (NPN)

B-C Junction

Bias (NPN) Mode (NPN)

Forward Reverse Forward-active

Forward Forward Saturation

Reverse Reverse Cut-off

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CONFIGURATIONS OF TRANSISTORS:

A transistor may be connected in any one of three basic configurations:

common emitter (CE), common base (CB), and common collector (CC).

The term common is used to denote the element that is common to both input

and output circuits. Because the common element is often grounded, these

configurations are frequently referred to as grounded emitter, grounded base,

and grounded collector.

Each configuration, as you will see later, has particular characteristics that make

it suitable for specific applications. An easy way to identify a specific transistor

configuration is to follow three simple steps:

Identify the element (emitter, base, or collector) to which the input signal

is applied.

Identify the element (emitter, base, or collector) from which the output

signal is taken.

The remaining element is the common element, and gives the

configuration its name.

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C-E CONFIGURATION:

INPUT RESISTANCE (Ri): It is defined as the ratio of input voltage (VBE) to

input current (IB).

Ri = VBE/ IB

OUTPUT RESISTANCE (Ro): It is defined as the ratio of output voltage (VCE)

to output current (IC).

Ro = VCE/ IC

RELATION BETWEEN α & β :

There are two current amplification factors is α and β.

The alpha factor (α) is called current amplification factor and is the

ratio of collector current to emitter current.

The beta factor (β) is the current gain factor called transport factor of

a CE circuit and is defined as the ratio of collector current with base

current .

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The relationship between α and β.

BIASING OF TRANSISTOR:

Biasing is referred to providing passive components such as resistances or

capacitances or supply voltages etc. to provide proper operating characteristics

of the device (i.e. transistor)

The purpose of dc biasing is to obtain dc collector current at a certain dc

collector voltage. These value of current and voltage are expressed by operating

point or quiescent point or point. To obtain proper Q point, biasing circuits are

required.

An operating point specifies the collector current IC and collector emitter

voltage VCE that exist when no input signal is applied.

To study effects of biasing conditions on the performance of transistor, it is

necessary to draw dc load line on the output characteristics of the transistor. The

operating point helps to decide faithful amplification of input signal.

There are various types of biasing available, which are:

1. Fixed biased

2. Fixed biased with emitter feedback

3. Fixed biased with collector feedback

4. Voltage divider biasing

5. Emitter biasing

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THERMAL RUNAWAY:

Fixing of a suitable operating point is not sufficient in transistors. It is also to be

ensured that it remains fixed also. The transistor parameters are temperature

dependent and parameter such as β change from unit to unit are responsible for

Q point to shift.

Flow of current in collector circuit produces heat at the collector junction. This

increases the temperature. More minority carriers are generated in base

collection region (since more bonds are broken). The leakage

current ICBO increases. Since

The increases in ICBO will increase to increase, which in turn increases

the . This further raises the temperature of the collector-base junction and

whole cycle repeats again. Such cumulative increase in will ultimately shift

the operating point into the saturation region. This is very dangerous. The

excess heat at junction may even burn the transistor. This is known as thermal

runaway.

VOLTAGE DIVIDER BIASING:

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The voltage divider is formed using external resistor R1 and R2. The

voltage across R2 forward biases the emitter junction. By proper selection

of resistors R1 and R2, the operating point of the transistor can be made

independent of Ic.

In this circuit, the voltage divider holds the base voltage fixed

independent of base current provided the divider current is large

compared to the base current.

However, even with a fixed base voltage, collector current varies with

temperature (for example) so an emitter resistor is added to stabilize the

Q-point

Merits:

• Unlike above circuits, only one dc supply is necessary.

• Operating point is almost independent of IC variation.

• Operating point stabilized against shift in temperature.

4.3 FIELD EFFECT TRANSISTORS:

TYPES OF FET’S:

FIELD EFFECT

TRANSISTOR

JFET MOSFET

N- CHANNEL

P- CHANNEL

DEPLETION

TYPE

ENHANCEMENT

TYPE

N- CHANNEL

P- CHANNEL

N- CHANNEL

P- CHANNEL

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As already mentioned, JFETs are of two types viz N-channel JFETs and P-

channel JFETs.Generally N-channel JFETs are preferred. N-channel and P-

channel JFETs are shown in figures.

JFET-junction-field-effect-transistor

Basic Construction:

Its structure is quite simple. In an N-channel JFET an N-type silicon bar,

referred to as the channel, has two smaller pieces of P-type silicon

material diffused on the opposite sides of its middle part, forming P-N

junctions, as illustrated in fig.

The two P-N junctions forming diodes or gates are connected internally

and a common terminal, called the gate terminal, is brought out. Ohmic

contacts (direct electrical connections) are made at the two ends of the

channel—one lead is called the source terminal S and the other drain

terminal D.

The silicon bar behaves like a resistor between its two terminals D and S.

The gate terminal is analogous to the base of an ordinary transistor (BJT).

It is used to control the flow of current from source to drain. Thus, source

and drain terminals are analogous to emitter and collector terminals

respectively of a BJT.

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In figure the gate is P-region, while the source and the drain are N-

regions. Because of this, a JFET is similar to two diodes. The gate and the

source form one of the diodes, and the drain form the other diode.

These two diodes are usually referred as the gate-source diode and the

gate-drain diode. Since JFET is a silicon device, it takes only 0.7 volts for

forward bias to get significant current in either diode.

With the gate terminal not connected, and a potential applied (+ ve at the

drain and – ve at the source), a current called the drain current, ID flows

through the channel located between the two P-regions. This current

consists of only majority carriers-electrons in this case. P-channel JFET is

similar in construction to N-channel JFET except that P-type

semiconductor material is sandwiched between two N-type junctions. In

this case majority carriers are holes.

Standard Notations. Worth noting FET notations are as follows :

Source: The terminal, through which the majority carriers enter the channel, is

called the source terminal S and the conventional current entering the channel at

S is designated as Ig.

Drain: The terminal, through which the majority carriers leave the channel, is

called the drain terminal D and the conventional current leaving the channel at

D is designated as ID.

The drain-to-source voltage is called VDS, and is positive if D is more positive

than source S

Gate: There are two internally connected heavily doped impurity regions

formed by alloying, by diffusion, or by any other method available to create two

P-N junctions. These impurity regions are called the gate G. A voltage VGS is

applied between the gate and source in the direction to reverse-bias the P-N

junction. Conventional current entering the channel at G is designated as IG.

Channel: The region between the source and drain, sandwiched between the

two gates is called the channel and the majority carriers move from source to

drain through this channel.

Schematic Symbols of JFET:

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The schematic symbols for N-type and P-type JFETs are shown in figure

respectively. The vertical line in the symbol may be thought as channel and

source S and drain D connected to the line.

Note that the direction of the arrow at the gate indicates the direction in which

the gate current flows when the gate junction is forward biased. Thus for the N-

channel JFET, the arrow at the gate junction points into the device and in P-

channel JFET, it is away from the device.

Operation of JFET:

Let us consider an N-channel JFET for discussing its operation.

When neither any bias is applied to the gate (i.e. when VGS = 0) nor any voltage

to the drain w.r.t. source (i.e. when VDS = 0), the depletion regions around the P-

N junctions, are of equal thickness and symmetrical.

When positive voltage is applied to the drain terminal D w.r.t. source terminal S

without connecting gate terminal G to supply, the electrons (which are the

majority carriers) flow from terminal S to terminal D whereas conventional

drain current ID flows through the channel from D to S.

Due to flow of this current, there is uniform voltage drop across the channel

resistance as we move from terminal D to terminal S. This voltage drop reverse

biases the diode. The gate is more “negative” with respect to those points in the

channel which are nearer to D than to S.

Hence, depletion layers penetrate more deeply into the channel at points lying

closer to D than to S. Thus wedge-shaped depletion regions are formed, as

shown in figure. When Vds is applied,The size of the depletion layer formed

determines-the width of the channel and hence the magnitude of current

ID flowing through the channel.

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Layers get reduced causing decrease in resistance and, therefore, increase in

drain current ID. (The gate-source voltage VGS at which drain current ID is cut-

off completely (pinched off) is called the pinch-off voltage Vp.

It is also to be noted that the amount of reverse bias is not the same throughout

the length of the P-N junction. When the drain current flows through the

channel, there is a voltage drop along its length. The result is that the reverse

bias at the drain end is more than that at the source end making the width of

depletion layer more at the drain. To see how the width of the channel varies

with the variation in gate.

JFET CHARACTERISTICS:

COMPARISON OF BJT & JFET:

JFET’S IMPEDENCE IS HIGH COMPARED THEN BJT.

JFET IS VOLTAGE DRIVEN DEVICE WHILE AS BJT CURRENT

DRIVEN DEVICE.

BJT is a bipolar device involving both types of charge carriers, where as

FET is a unipolar device involving only one type of charge carrier.

FET has better temp stability as compared to NJT.

BJT is more temp sensitive than FET

BJT has better driving capability than FET and BJT also has high speed

switching compared to FET.

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MOSFET:

MOSFET Metal (or poly-silicon doped heavily to act like a metal)• Oxide

(SiO2, Acts as an insulator.) . Semiconductor (One can selectively change the

carrier type to n-type or p-type.) Field Effect (Device is controlled by an electric

field as opposed to current.) Transistor (Three terminal devices).

Based on the channel formed beneath the insulating layer, MOS transistors are

classified as N-channel transistor (NMOS) and P-channel transistor (PMOS). A

cross sectional views of both the transistors are shown.

Each transistor should have a source, drain, gate and a backgate usually known

as bulk terminal. In the case of an NMOS the source and gate are generated by

diffusing N type dopant to a P substrate, and vice versa for PMOS. The source

and drain of a MOS transistor are interchangeable and the carriers flow out of

the source and come into the drain.

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OPERATION:

Figure 3: The Structure of an Enhancement Type MOSFET and its

Operation

(a) When VGS (Gate-source voltage) is not supplied

(b) (b) When VGS (Gate-source voltage) is supplied

The basic operation of an NMOS transistor is explained below. There are

three regions of operation for a transistor.

o Cut off region (VGS < VTH)

o Triode region (VGS > VTH & VDS < VDSsat)

o Saturation region (VGS > VTH & VDS > VDSsat)

Initially consider the Transistor with VGS =0, i.e. with no gate to source

voltage is applied. So no current will flow from the source to drain. Also

a depletion region will form at the source – substrate, drain – substrate

junctions. When the VGS voltage is gradually increased below the

threshold voltage (VTH), the holes under the gate are repelled to produce a

depletion region, and it becomes continuous under the gate from source to

drain. The VGS is then increased above the threshold voltage i.e. VGS >

VTH. At this time the minority carriers (electrons) in the P sub crosses

depletion region and reaches under the gate. This process is called

inversion.

After the channel is established between the Source and the Drain, the

VDS(Drain to source voltage) is increased gradually from 0. When the

VDS become positive the Drain – Sub junction will get reverse biased and

the depletion region here get widened as the drain becomes more positive

with respect to the source.

Due to this lateral electric field, current flow starts from the source to

drain and the current flow increases with the increase in the VDS. Hence

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the potential at the source is less than that at the source the depletion

region widens near drain and the channel tapers here.

At the point when VDS=VDSsat, the channel just touches the drain and the

corresponding drain to source voltage is known as the pinch off voltage.

Above the saturation voltage the current flow gets constant. Carriers

move down the channel propelled by the relatively weak electric field

along it. When they reach the edge of the pinched-off region, they are

sucked across the depletion region by the strong electric field.

The voltage drop across the channel does not increase as the drain voltage

is increased; instead the pinched-off region widens. Thus, the drain

current reaches a limit and ceases to increase.

The advantages of the lateral MOSFET are:

1. Low gate signal power requirement. No gate current can flow into the gate

after the small gate oxide capacitance has been charged.

2. Fast switching speeds because electrons can start to flow from drain to source

as soon as the channel opens. The channel depth is proportional to the gate

voltage and pinches closed as soon as the gate voltage is removed, so there is no

storage time effect as occurs in bipolar transistors.

The major disadvantages of MOSFET are:

1. High resistance channels. In normal operation, the source is electrically

connected to the substrate. With no gate bias, the depletion region extends out

from the drain in a pseudo-hemispherical shape. The channel length L cannot be

made shorter than the minimum depletion width required to support the rated

voltage of the device.

2. Channel resistance may be decreased by creating wider channels but this is

costly since it uses up valuable silicon real estate. It also slows down the

switching speed of the device by increasing its gate capacitance.