Chapter 4

Memory

Memory Hierarchies Some fundamental and enduring properties of hardware and

software: Fast storage technologies cost more per byte and have less

capacity. The gap between CPU and main memory speed is widening. Well-written programs tend to exhibit good locality.

These fundamental properties complement each other

beautifully.

They suggest an approach for organizing memory and storage systems known as a memory hierarchy.

Characteristics Memory

Cost Capacity Access Time

How can we have a good design of

memory????

An Example Memory Hierarchy registers

on-chip L1 cache (SRAM)

main memory (DRAM)

local secondary storage (local disks)

Larger, slower, and cheaper (per byte) storage devices

remote secondary storage (distributed file systems, Web servers)

Local disks hold files retrieved from disks on remote network servers.

Main memory holds disk blocks retrieved from local disks.

off-chip L2 cache (SRAM)

L1 cache holds cache lines retrieved from the L2 cache memory.

CPU registers hold words retrieved from L1 cache.

L2 cache holds cache lines retrieved from main memory.

L0:

L1:

L2:

L3:

L4:

L5:

Smaller, faster, and costlier (per byte) storage devices

Caches Cache: A smaller, faster storage device that acts as a staging

area for a subset of the data in a larger, slower device. Fundamental idea of a memory hierarchy:

For each k, the faster, smaller device at level k serves as a cache for the larger, slower device at level k+1.

Why do memory hierarchies work? Programs tend to access the data at level k more often than

they access the data at level k+1. Thus, the storage at level k+1 can be slower, and thus

larger and cheaper per bit. Net effect: A large pool of memory that costs as much as

the cheap storage near the bottom, but that serves data to programs at the rate of the fast storage near the top.

Semiconductor Memory Types

Semiconductor Memory

RAM Misnamed as all semiconductor

memory is random access Read/Write Volatile Temporary storage Static or dynamic

Memory Cell Operation

The select terminal ,selects a memory cell for a read or write operation The control terminal indicates read or write For writing the other terminal provides an electrical signal that sets the state of the cell to 1 or 0

Dynamic RAM Bits stored as charge in capacitors Charges leak Need refreshing even when powered Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Main memory Essentially analogue

Level of charge determines value

Dynamic RAM Structure

DRAM Operation Address line active when bit read or written

Transistor switch closed (current flows) Write

Voltage to bit line High for 1 low for 0

Then signal address line Transfers charge to capacitor

Read Address line selected

transistor turns on Charge from capacitor fed via bit line to sense amplifier

Compares with reference value to determine 0 or 1 Capacitor charge must be restored

Static RAM Bits stored as on/off switches No charges to leak No refreshing needed when powered More complex construction Larger per bit More expensive Does not need refresh circuits Faster Cache Digital

Uses flip-flops

Stating RAM Structure

Static RAM Operation

Transistor arrangement gives stable logic state State 1

C1 high, C2 low T1 T4 off, T2 T3 on

State 0 C2 high, C1 low T2 T3 off, T1 T4 on

Address line transistors T5 T6 is switch Write – apply value to B & compliment to B Read – value is on line B

SRAM v DRAM Both volatile

Power needed to preserve data Dynamic cell

Simpler to build, smaller More dense Less expensive Needs refresh Larger memory units

Static Faster Cache

Read Only Memory (ROM)

Permanent storage Nonvolatile No power source needed to maintain

the bit values in memory

Types of ROM Written during manufacture

Very expensive for small runs Programmable (once)

PROM Needs special equipment to program

Read “mostly” Erasable Programmable (EPROM)

Erased by UV Storage Cells must be erased before write operation

Electrically Erasable (EEPROM) Takes much longer to write than read Can be written into any time without erasing prior contents

Flash memory Erase whole memory electrically

Typical 16 Mb DRAM (4M x 4)

Packaging

Error Correction

Hard Failure Permanent defect, so that memory cell or

cells affected cannot reliably store data. Soft Error

Random, non-destructive No permanent damage to memory

Detected using Hamming error correcting code

Error Correcting Code Function

Error correcting code function

When data are to be read into the memory A calculation depicted as a function f is performed on the

data to produce a code Both the code and data are stored if an M bit word of data to be stored, and the code is of

length K bits, then the actual size of the stored word is M+K bits

Types of External Memory Magnetic Disk

RAID Removable

Optical CD-ROM CD-Recordable (CD-R) CD-R/W DVD

Magnetic Tape

Magnetic Disk

Disk substrate coated with magnetizable material (iron oxide…rust)

Substrate used to be aluminium Now glass

Improved surface uniformity Increases reliability

Reduction in surface defects Reduced read/write errors

Lower flight heights (See later) Better stiffness Better shock/damage resistance

Read and Write Mechanisms Recording and retrieval via conductive coil called a head May be single read/write head or separate ones During read/write, head is stationary, platter rotates Write

Current through coil produces magnetic field Pulses sent to head Magnetic pattern recorded on surface below

Read (traditional) Magnetic field moving relative to coil produces current Coil is the same for read and write

Read (contemporary) Separate read head, close to write head Partially shielded magneto resistive (MR) sensor Electrical resistance depends on direction of magnetic field High frequency operation

Higher storage density and speed

Data Organization and Formatting

Concentric rings or tracks Gaps between tracks Reduce gap to increase capacity Same number of bits per track (variable packing

density) Constant angular velocity

Tracks divided into sectors Minimum block size is one sector May have more than one sector per block

Disk Data Layout

Disk Layout Methods Diagram

Fixed/Movable Head Disk

Fixed head One read write head per track Heads mounted on fixed ridged arm

Movable head One read write head per side Mounted on a movable arm

Removable or Not

Removable disk Can be removed from drive and replaced

with another disk Provides unlimited storage capacity Easy data transfer between systems

Non removable disk Permanently mounted in the drive

Multiple Platter

One head per side Heads are joined and aligned Aligned tracks on each platter form

cylinders Data is striped by cylinder

reduces head movement Increases speed (transfer rate)

Multiple Platters

Examples of Caching in the Hierarchy

Hardware 0 On-Chip TLB Address translations

TLB

Web browser

10,000,000 Local disk Web pages Browser cache

Web cache

Network buffer cache

Buffer cache

Virtual Memory L2 cache L1 cache

Registers

Cache Type

Web pages

Parts of files

Parts of files

4-KB page 32-byte block 32-byte block

4-byte word

What Cached

Web proxy server

1,000,000,000 Remote server disks

OS 100 Main memory

Hardware 1 On-Chip L1 Hardware 10 Off-Chip L2

AFS/NFS client

10,000,000 Local disk

Hardware+OS

100 Main memory

Compiler 0 CPU registers

Managed By Latency (cycles)

Where Cached

Replacement Algorithm

• When there is a page fault, the referenced page must be loaded.

• If there is no available frame in memory, then one page is selected for replacement

• If the selected page has been modified, it must be copied back to disk (swapped out)

• A page replacement algorithm is said to satisfy the inclusion property or is called a stack algorithm if the set of pages in a k-frame memory is always a subset of the pages in a (k + 1) frame memory.

Replacement Algorithm

• 4 type replacement algorithm 1. LRU (Least Recently Used) 2. FIFO (First In First Out) 3. LFU (Least Frequently Used) 4. Random