Name of presentation

Prepared by Azhani Hashim

THE WIRE1INTRODUCTIONThe wiring of todays integrated circuits forms a complex geometry that introduces capacitive, resistive and inductive parasitics.The effects of those parasitics to the circuit behaviour are:An increase in propagation delay resulting a drop in performance.An impact on the energy dissipation and the power distribution.An introduction of extra noise sources which affects the reliability of the circuit.

INTERCONNECT PARAMETERSCapacitanceThe capacitance depends on the wire functions such as shape, environment, distance to substrate and distance to surrounding wires.A simple rectangular wire placed above the semiconductor substrate. If the width of the wire is larger than the insulating material, it may be assumed that the electrical field lines are orthogonal to the capacitor plates. Therefore, the capacitance can be modeled by parallel-plate capacitor model.CAPACITANCEthe total capacitance of the wire:

permittivity of dielectric layerthickness of dielectric layer

permittivity5

CAPACITANCE (cont.)the total capacitance of the wire:

permittivity of dielectric layerthickness of dielectric layer

permitivity of free spacePermittivity = The ability of a substance to store electrical energy in an electric field. permittivity is a measure of how an electric field affects, and is affected by, a dielectric medium.A dielectric material is a substance that is a poor conductor of electricity, but an efficient supporter of electrostatic field s. If the flow of current between opposite electric charge poles is kept to a minimum while the electrostatic lines of flux are not impeded or interrupted, an electrostatic field can store energy.7CAPACITANCE (cont.)The capacitance between the side-walls of the wires and the substrate called the fringing capacitance.

CAPACITANCE (cont.)Therefore,

CAPACITANCE OF METAL WIREExample 4.1Consider an aluminium wire of 10cm long and 1m wide, routed on the first Aluminium layer.

Pico 10-12 Femto 10-15 Atto 10-18 Zepto 10-21 Yocto 10-24

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CAPACITANCE OF METAL WIRE (cont.)Example 4.1 (cont.)Suppose now that a second wire is routed alongside the first one, separated by only a minimum allowed distance. The inter wire capacitance is

INTERCONNECT PARAMETERSRESISTANCEThe resistance of a wire is proportional to its length, L and inversely proportional to its cross-section A.

- rho13RESISTANCE (cont.)If H is a constant for a given technology, Eq. 4.3 can be written as :

Rs is sheet resistance (/s) : Ohm per square

RESISTANCE (cont.)Polycide-gate MOSFET

Silicide is a compound material formed by using silicon and a refractory metal (a class of metals that are extraordinarily resistant to heat and wear. Ex = (niobium and molybdenum, tantalum, tungsten, and rhenium). The resistivity eight times lower that polysilicon.

RESISTANCE (cont.)Polycide-gate MOSFET (cont)

Polycide consist of lower level of polysilicon and upper coating of silicide.Good adherence and coverage from poly and high conductance from silicide.

RESISTANCE (cont.)Example 4.2Consider the aluminimum wire is 10cm long and 1m wide is routed on the first Aluminium layer. Assuming a sheet resistance for Al1 is 0.075/s.

RESISTANCE (cont.)Skin effectHappen in very high frequency circuit.High frequency currents tend to flow primarily on the surface of a conductor with the current density falling off exponentially with depth into the conductor.

skin depth is defined as the depth where the current falls off to a value of e-1 of its nominal value. the permeability of the surrounding dielectric (typicallyequal to the permeability of free space, or = 4 x 10-7 H/m).Permeability = The state or quality of a material or membrane that causes it to allow liquids or gases to pass through it.A quantity measuring the influence of a substance on the magnetic flux in the region it occupies.In electromagnetism, permeability is the measure of the ability of a material to support the formation of a magnetic field within itself. In other words, it is the degree of magnetization that a material obtains in response to an applied magnetic field.18RESISTANCE (cont.)Skin effect

INTERCONNECT PARAMETERSINDUCTANCEIntegrated circuit designer tend to dismiss inductance especially on the first decade of integrated digital circuit design.With the adoption of low-resistive interconnect material, increase of switching frequencies to super GHz range, inductance start to play a role even on a chip.The capacitance and the inductance of a wire are related by :

epsilon20INDUCTANCE (cont.)

INDUCTANCEExample 4.4 (cont)

WIRE MODELThe wire models can be described as:The Ideal WireThe Lumped ModelThe Lumped RC ModelDistributed RC ModelTHE IDEAL WIREWire occur a simple lines with no attached parameters or parasitics.Wires have no impact on the electrical behaviour of the circuit.Voltage change at one end of wire propagates immediately to its other ends.Same voltage present at every segment of the wire at the every point of time = equipotential region.

THE LUMPED MODELThe circuit parasitic of a wire are distributed along its length and are not lumped into a single position. Ex. Capacitance parasitic.

However, if only a single parasitic component is dominant. Or when looking at only one aspect of the circuit behaviour, it is often useful to lump the different fractions into a single circuit element.

THE LUMPED MODEL (cont.)As long as the resistive component of the wire is small and the switching frequencies are in low to medium range, it is meaningful to consider only the capacitive component of the wire.This capacitive lumped model is simple, effective and is the model of choice for the analysis of most interconnect wires.

THE LUMPED RC MODELOn-chip metal wires of over a few mm length have a significant resistance. Therefore, the lumped-capacitor model is no longer adequate, a resistive-capacitive model has to be adopted.First approach:Lumps the total wire resistance of each wire segment into one single R.Combines the global capacitance into a single C.Called the Lumped RC Model. But pessimistic and inaccurate for long interconnect wire.DISTRIBUTED RC MODELSeconds approach:The Distributed RC ModelComplex and no closed form solution exist.Common practice is to reduce the circuit to an RC network.Ex : RC-TreeThe properties of RC-Tree / Tree Structured RC network:The network has a single input node.All the capacitors are between a node and the ground.The network does not contain any resistive loops (makes it as tree)DISTRIBUTED RC MODEL (cont.)RC-tree

Path resistance Rii is the total resistance along the path.

DISTRIBUTED RC MODEL (cont.)RC-tree

Shared path resistance Rik is the resistance shared among the paths from the root node s to nodes k and i.

DISTRIBUTED RC MODEL (cont.)RC-tree

The Elmore delay at node i is then given by the following expression:

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