VLSI Arithmetic Adders Prof. Vojin G. Oklobdzija University of California .
Chapter 4 – Arithmetic Functions and CircuitsFunctions and Circuitshoangtrang/lecture...
Transcript of Chapter 4 – Arithmetic Functions and CircuitsFunctions and Circuitshoangtrang/lecture...
Computer Eng 1 (ECE290)
Chapter 4 – Arithmetic Functions and CircuitsFunctions and Circuits
HOANG Trang
Reference: © 2008 Pearson Education IncReference: © 2008 Pearson Education, Inc.
Lecture note of Prof.Donna J.Brown
Overview
Binary adders• Half and full adders• Ripple carry and carry lookahead adders
Binary subtraction Binary adder-subtractors
• Signed binary numbersSi d bi dditi d bt ti• Signed binary addition and subtraction
• Overflow
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 2
HalfHalf--AdderAdder
Simple Binary Addition
0 + 0 = 00 + 0 = 0
0 + 1 = 10 + 1 = 1
Zero plus zero equals zeroZero plus zero equals zero
Zero plus one equals oneZero plus one equals one0 1 10 1 1
1 + 0 = 11 + 0 = 1
1 + 1 = 101 + 1 = 10
Zero plus one equals oneZero plus one equals one
One plus zero equals oneOne plus zero equals one
One plus one equals zero with a carryOne plus one equals zero with a carry1 + 1 = 101 + 1 = 10 One plus one equals zero with a carry One plus one equals zero with a carry of oneof one
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 3
HalfHalf--Adder Adder
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 4
Five Implementations: Half-Adder
We can derive following sets of equations for a half-ddadder:
YXCYXYXS)a(
)YX(CC)YX(S)d(
)(S)c(YXC
)YX()YX(S)b(C
YXC
YXCYXS)e(
)(
(a), (b), and (e) are SOP, POS, and XOR i i f S
YXC)(S)c( YXC
implementations for S. In (c), the C function is used as a term in the AND-
NOR implementation of S, and in (d), the function isC
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 5
NOR implementation of S, and in (d), the function is used in a POS term for S.
C
Implementations: Half-Adder
The most common half adder implementation is: (e) X
Y S
YXCYXS
Y
C
A NAND only implementation is:
YXC
C
)(CC)YX(S
)YX( X
C
S)( )(
YCMOS
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 6
NAND gate: behaviorial, transistor, layout
O <= NOT ( A1 AND B1);
B l E ti M kT i t
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Boolean Equation MaskTransistor
FullFull--AdderAdder
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FullFull--AdderAdder
Full adder from two halfFull adder from two half--adder circuitsadder circuits
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Adder: behavior, netlist, transistor, layout
Behavioral model Structural model
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28 transitors for 1 Full Adder
Parallel Binary AddersParallel Binary Adders
TwoTwo--bit parallel binary adderbit parallel binary adder
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Parallel Binary AddersParallel Binary Adders
FourFour--bit parallel binary adderbit parallel binary adder
iteractive
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 12
iteractive
4-bit Ripple-Carry Binary Adder
A four-bit Ripple Carry Adder made from four pp y1-bit Full Adders:
B3 A 3 B2 A 2 B1 A 1 B0 A 03 3
FA
2 2
FA
1
CC3 C2 C1
1
FA
0 0
FAFA FA
SC
C0
S S S
FA FA
S3C4 S2 S1 S0
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 13
Unsigned Subtraction
Algorithm:• M (minuend) – N (subtrahend) (n-bit number)( ) ( ) ( )• M N: no end borrow, and the result is a non-
negative number and correct.• N > M: end borrow occursand the difference M N + 2n
and a minus sign is appended to the resultand a minus sign is appended to the result.
Examples: 0 1 1001 01000111 0111 0111 01110010 1101
10000
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 14
1101() 0011
Unsigned Subtraction (continued)
The subtraction (2n N): is the 2’s complement f Nof N
To do both unsigned addition and unsigned subtraction requires:
A B
subtraction requires: Quite complex! G l Sh d i l Binary adder Binary subtractorBorrow
Goal: Shared simplerlogic for both additionand subtraction
Binary adder Binary subtractor
Selectiveand subtraction=> Introduce complements
as an approach
Selective2's complementerComplement
0 1Subtract/Add
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 15
as an approachQuadruple 2-to-1
multiplexer
Result
SSubtract/Add
Sign-magnitude representation
Leftmost bit is sign bit:
0 iti0 positive
1 negative
Example:
Ex: 6-bit representation (n=6) Disadvantages of sign-magnitude:1. Hard to do arithmetic (addition is hard)2. Two representation of 0: +0 and -0p
+13: 001101
-13: 101101
Largest number: 011111 (+31) (2n-1)
n
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 16
Smallest number: 111111 (-31) -(2n-1)
4-bit sign-magnitude representation
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 17
4-bit 2’s complement representation
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4-bit representation
Problem:0: 2 representations0: 2 representations
NICE
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 19
3-bit representation
n=3
Number Sign -Mag. 1's Comp. 2's Comp.+3 011 011 0113 011 011 011+2 010 010 010+1 001 001 001+0 000 000 000+0 000 000 000– 0 100 111 —– 1 101 110 111– 2 110 101 110– 3 111 100 101
4 100
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– 4 — — 100
2’s Complement Representation: X-> -X?
Given: an n-bit number X in 2’s complement form Goal: Representation –X in 2’s complement form?Example: n=5; X=01101 (2’s complement form)
Method 1: take the 1’s complement of X and ADD 1
X= 0110110010
+13
+ 110011 -13
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 21
2’s Complement Representation: X-> -X?
Method 2: compute: 2n -X100000 - 0110110011
+131310011 -13
Method 3: complement all bits to the left of the least i ifi t 1 (l i th bit h d)significant 1 (leaving other bits unchanged)X=01101 (+13) => -X=10011 (-13)X=10100 ( 12) => X=01100 (+12)X=10100 (-12) => -X=01100 (+12)
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 22
2’s Complement Representation: X-> -X?
Method 4: The n-bit 2’s complement representation is i ht d d ith l ft t bit f i ht 2n-1a weighted code with leftmost bit of weight - 2
X=1010 => X=-8+2=-6
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 23
2’s Complement Addition/Subtraction
Given numbers X and Y in 2’s complement form1. To ADD : Y+X: do ordinary binary
2. To SUBSTRACT: Y-X: compute (-X) and ADD Y+ (-X)10110 (-10)
- 10011 (-13)
10110
+01101
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100011 (3)
2’s Complement Adder/Subtractor
How to design?+ before we design, the Adder/Subtractor before we design, the Adder/Subtractor-> check that: we can design each seperatelyDesign Adder:g
How to design?
Design Substractor Answer: black box: would be like a nice girl. Oh, NO!
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 25
2’s Complement Adder/Subtractor
Subtraction can be done by addition of the 2's Complement. 1. Complement each bit (1's Complement.)1. Complement each bit (1 s Complement.)2. Add 1 to the result.
For k = 1, subtract,the 2’s complementof B is formed by usingXORs to form the 1’s k
B3 A3 B2 A2 B1 A1 B0 A0
XORs to form the 1 scomp and adding the 1applied to C0.
For k = 0, add, B ispassed throughunchanged
FA FA FA FAC3
S2 S1 S0S3C4
C2 C1 C0
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 26
u c a ged
Overflow Detection
Overflow occurs if n + 1 bits are required to contain the result from an n-bit addition or subtraction
n=5 bit: -16 -> 15
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 27
Overflow Detection: when it occurs?
Intuition (clearly) that:Overflow can occur for:
• Addition of two operands with the same signp gAdd 2 positive and get a negativeAdd 2 negative and get a positiveg g p• Subtraction of operands with different signsIdeal: simple implementationIdeal: simple implementationCn XOR Cn-1 = 1
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Overflow Detection: when it occurs?
Consider all possibility
floverflow
Cn XOR Cn-1
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Overflow Detection: when it occurs?
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An Arithmetic Unit (AU)
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A Logic Unit (LU)
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An Arithmetic/Logic Unit (ALU) (very popular in micro-Controller, computer, processor)p p )
HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 33