Chapter 3 Microprocessor Architecture and Microcomputer...

Rahul PatelMicroprocessor & Interfacing (140701) 11

Chapter 3Microprocessor Architecture and

Microcomputer Systems

byRahul Patel,

Assistant Professor, EC Dept.,Sankalchand Patel College of Engg., Visnagar


Points to be Discussed• Microprocessor Architecture• Operations Performed by Microprocessor

– Microprocessor initiated operations– Internal operations – Externally initiated operations

• Memory and its Classification• Input and Output Devices• Memory Interfacing with 8085 (Memory Address-

mapping)


Microprocessor Architecture• The microprocessor can be programmed to

perform functions on given data by writing specific instructions into its memory.– The microprocessor reads one instruction at a

time, matches it with its instruction set, and performs the data manipulation specified.

– The result is either stored back into memory or displayed on an output device.


Operation Types in a Microprocessor• All of the operations of the microprocessor can

be classified into one of three types:– Microprocessor Initiated Operations– Internal Operations– Peripheral Initiated Operations


Microprocessor Initiated Operations• These are operations that the microprocessor

itself starts.• These are usually one of 4 operations:

– Memory Read– Memory Write– I/O Read (Get data from an input device)– I/O write (Send data to an output device)


Microprocessor Initiated Operations• It is important to note that the microprocessor

treats memory and I/O devices the same way. – Input and output devices simply look like memory

locations to the microprocessor.• For example, the keyboard may look like memory

address A3F2H. To get what key is being pressed, the microprocessor simply reads the data at location A3F2H.

– The communication process between the microprocessor and peripheral devices consist of the following three steps:

– Identify the address. (Address Bus)– Transfer the binary information. (Data Bus)– Provide the right timing signals. (Control Bus)


Microprocessor Initiated Operations

8085 Bus Structure


Internal Operations• The 8085 can perform a number of internal operations

such as: – storing data– Arithmetic & Logic operations– Testing for condition– Sequence the execution of instructions– Store data in STACK memory

• To perform these operations, the microprocessor needs an internal architecture similar to that shown:

Accumulator FlagsB CD EH L

Program Counter (PC) Stack Pointer (SP)

DataAddress 816


Internal Operations (Read operation)

Memory Read Operation


– To read the contents of a memory location, the following steps take place:

• The microprocessor places the 16-bit address of the memory location on the address bus.

• The microprocessor activates a control signal called “memory read” which enables the memory chip.

• The memory decodes the address and identifies the right location.

• The memory places the contents on the data bus. • The microprocessor reads the value of the data bus after

a certain amount of time.

Internal Operations (Read operation)


Externally Initiated Operations• External devices can initiate (start) one of the 4

following operations:– Reset

• All operations are stopped and the program counter is reset to 0000H and program execution begins again.

– Interrupt• The microprocessor’s operations are interrupted and the

microprocessor executes what is called a “service routine”.

• This routine “handles” the interrupt (perform the necessary operations) and then the microprocessor return to its previous operation and continue it.


Externally Initiated Operations– Ready

• The 8085 has a pin called READY. As long as the READY pin is low, the 8085 will be in a wait state.

• This pin is used by external devices to stop the 8085,until they catch up.

– i.e. to synchronize slower peripherals with the microprocessor.

– Hold• The 8085 has a pin called HOLD. This pin is used by

external devices to gain control of the busses.• When the HOLD signal is activated by an external

device, the 8085 stops executing instructions and stops using the busses.

• This would allow external devices to control the information on the busses. Example DMA (Direct Memory Access) data transfer.


The Design and Operation of Memory• Memory in a microprocessor system is where

information (data and instructions) is kept. It can be classified into two main types:

• Prime (Main) memory (RAM and ROM) • Storage memory (Disks , CD ROMs, etc.)

– The simple view of RAM is that it is made up of registers that are made up of flip-flops (or memory elements).

• The number of flip-flops in a “memory register” determines the size of the memory word.

– ROM on the other hand uses diodes instead of the flip-flops to permanently hold the information.


Memory Classification


Input and Output (I/O) Devices• I/O devices are the means through which

microprocessor communicates with the outside world.

• Input devices are keyboard, A/D converter, etc.• Output devices are LEDs, printers, etc.• Methods by which I/O devices can be identified

are:– Peripheral-Mapped I/O (8-bit address)– Memory-Mapped I/O (16-bit address)


Peripheral-Mapped I/O (8-bit address)• Microprocessor uses 8-bit address to identify input or

output device.• Also known as I/O-mapped I/O.• Data transfer is through specific Input (IN) and Output

(OUT) instructions.• This address space is known as I/O space, separate

from memory space, which has 16-bit address.• Microprocessor can identify 256 (28) input as well as

output devices.• The input and output devices are differentiated by

control signals.– I/O Read à Input device– I/O Write à Output device.


Peripheral-Mapped I/O (8-bit address)


Memory-Mapped I/O (16-bit address)• Microprocessor uses 16-bit address to identify

input or output device.• Microprocessor uses same control signal

(Memory Read and Write) and instructions, as used for accessing memory.– i.e. I/O device is treated as a memory register.

• I/O devices and memory shares the same 64K range.


Tri-State Buffers• An important circuit element that is used

extensively in memory.• This buffer is a logic circuit that has three states:

– Logic 0, logic1, and high impedance.– When this circuit is in high impedance mode it

looks as if it is disconnected from the output completely.


The Tri-State Buffer• This circuit has two inputs and one output.

– The first input behaves like the normal input for the circuit.

– The second input is an “enable”.• If it is set high, the output follows the proper circuit

behavior.• If it is set low, the output looks like a wire connected to

nothing (High impedance state).

Input Output

Enable

Input Output

Enable

OR


The Basic Memory Element• The basic memory element is similar to a D latch.• This latch has an input where the data comes in.

It has an enable input and an output on which data comes out.

QD

EN

Data Input Data Output

Enable


The Basic Memory Element• However, this is not safe.

– Data is always present on the input and the stored bit is always available at Dout line.

– To avoid unintentional change in the input and control the availability of the output, tri-state buffers are added at the input and output of the latch.

QD

EN

Data Input Data Output

Enable

WR RD


The Basic Memory Element• The WR signal controls the input buffer.

– The bar over WR means that this is an active low signal.

– So, if WR is 0, the input data reaches the latch input.

– If WR is 1, the input of the latch looks like a wire connected to nothing (High Impedance)

• The RD signal controls the output in a similar manner.


A Memory “Register”• If we take four of these latches and connect them

together, we would have a 4-bit memory register

WR

RD

EN

Q

D

EN

Q

D

EN

Q

D

EN

Q

D

EN

I0 I1 I2 I3

O0 O1 O2 O3


– Expanding on this scheme to add more memory registers we get the diagram to the right.

A group of memory registers

D

EN

Q D

EN

Q D

EN

Q D

EN

Q

D

EN

Q D

EN

Q D

EN

Q D

EN

Q

D

EN

Q D

EN

Q D

EN

Q D

EN

Q

D

EN

Q D

EN

Q D

EN

Q D

EN

Q

D0 D1 D2 D3

D0 D1 D2 D3

oooo

oooo

WR

RD

Register - 0

Register - 2

Register - 3

Register - 1

En0

En1

En2

En3


A group of Memory Registers

– If we represent each memory location (Register) as a block we get the following

Input Buffers

Output Buffers

Memory Reg. 0

Memory Reg. 1

Memory Reg. 2

Memory Reg. 3

I0 I1 I2 I3

O0 O1 O2 O3

WR

EN0

EN1

EN2

EN3

RD


The Enable Inputs• How do we produce these enable line?

– Requirement: We can’t have more than one of these enables active at the same time.

– Solution: A decoder (e.g. 2 X 4)– To operate a decoder (e.g. 2 X 4) we require two

input line. These inputs lines are address linesfor memory.

• i.e. Address lines of microprocessor (any line A0 to A15)


The Design of a Memory Chip– So, the previous diagram would now look like the

following:

Input Buffers

Output Buffers

Memory Reg. 0

Memory Reg. 1

Memory Reg. 2

Memory Reg. 3

I0 I1 I2 I3

O0 O1 O2 O3

WR

RD

Address

Decoder

A1

A0


The Design of a Memory Chip• Using the RD and WR controls we can

determine the direction of flow either into or out of memory. Then using the appropriate Enable input we enable an individual memory register.

• What we have just designed is a memory with 4 locations and each location has 4 bits. This memory would be called 4 X 4 [Number of location X number of bits per location].


The Design of a Memory Chip• Since we have tri-state buffers on both the inputs

and outputs of the flip flops, we can actually use one set of pins only.– The chip would now look like this:

Input Buffers

Output Buffers

Memory Reg. 0

Memory Reg. 1

Memory Reg. 2

Memory Reg. 3

WR

RD

Address

Decoder

A1

A0

D0

D1

D2

D3

D0

D1

D2

D3

A1

A0

RD WR

4 X 4


4 X 8 memory Two 4 X 4 = 4 X 8 memory

Memory Chip Combination


How to deal with more than one chip?• Aim: To design 8 X 8 memory from two 4 X 8

memory chip.• Solution:


RAM and ROM Memory

RAM ROM


Accessing Information in Memory• For the microprocessor to access (Read or Write)

information in memory (RAM or ROM), it needs to do the following:– Identify the memory location ( Determined by the

number of registers in a chip)• Equation: 2n >= Number of registers

» Where n = number of address lines.• Of 16 address lines, n lines must connected to memory

chip.– Select the right memory chip (use rest of the

address lines to provide ).– Provide necessary control signal (Read / Write).– Access the data (using the data bus).

CS


Questions• Q 1. How much address lines are required for the

memory chip having – 256 registers.– 1024 registers.– 16384 registers.– 120 registers.

• Q 2. What is the size of the memory in terms of bits of – 256 bytes– 512 X 4– 64KB


Question• When will CS be activated (CS = 0) in the below

figures?

CS

A10

A11

A12

A13A14

A15

Fig. 1

CS

A10

A11

A12A13A14

A15

Fig. 2

Solution (Fig. 1) :

A15 – A10 = 001000

Solution (Fig. 2) :

A15 – A10 = 001001


Questions• Q 3. What is the

address range for the 256 byte memory shown?


Solution of Q 3


Questions• Q 4. What is the

address range for the 256 byte memory shown?

• Solution: -A15=1A14 – A8 = 0

i.e. A15 – A8 = 80HA7 – A0 = from all 0’s to all 1’s = 00H – FFH

Finally from 8000H to 80FFH.


• Q 5. What is the address range for the 1KB memory shown?

Questions


Solution of Q 5


Questions• Calculate the number of memory chips needed to

design 8KB memory if the memory chip is 1024 X 1 ? • If the memory chip size is 2048 X 8 bits, how many

chips are required to make up 16K-bytes of memory ? • If the memory chip size is 1024 X 4 bits, how many

chips are required to make up 2KB of memory ?• How many bits are stored by a 256 X 4 memory chip?

Can this chip be specified as 128-byte memory ?

1 à 64 chips

2 à 8 chips

3 à 4 chips

Solution :

4 à 1024 bits, yes


Decoding using Decoder • What is the address range for below fig. ?


Solution• Referring to the previous fig.

– A15 – A12 must be 0000 to generate Chip Select (CS) signal.

– The address lines A0 – A11 can have all logic combinations from all 0’s to all 1’s.

– Hence the address range is 0000H – 0FFFHA15 A14 A13 A12 A11A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1

Chip Enable

Register Select

0 0 0 0 0 0 0 0 0 0 0 0.....

......


Question • Address range ?


Solution

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 1

1 1 1 1 1 1 1 1 1 1 1

Chip Enable

Register Select

0 0 0 0 0 0 0 0 0 0 0.....

......

Address Range: 8800H – 8FFFH


Question• Address Range for ROM & RAM ?


Solution• ROM : 0000H – 0FFFH• RAM : 2000H – 27FFH (A11 = 0)

OR2800H – 2FFFH (A11 = 1)


Questions• The memory map of 4KB memory chip begins at

2000H. Specify the last address of the chip ? • For a 1KB memory with ending address FBFFH,

specify the starting address ? • For a 8KB memory with ending address FFFFH,

specify the starting address ?

1 à 2FFFH

2 à F800H

3 à E000H

Solution :


Thank youAny Quarries?

Chapter 3 Microprocessor Architecture and Microcomputer...

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