27

Chapter 3

Fabrication Process for Surface Micro machined Metallic Structures

This chapter covers major unit processes used for the fabrication of MEMS devices. The

main focus is on the fabrication of reliable RF MEMS devices using surface

micromachining. The unit processes that are of prime concern are polysilicon deposition,

diffusion, metal deposition and etching, photoresist coating and patterning, lift-off,

electroplating and release of photoresist/metal sacrificial layers. The major challenges

toward reliable switch fabrication/commercialization are structural deformation/ out of

plane buckling after sacrificial layer release. Reasons for device buckling are built-in

residual stress which is developed in the structure during metal deposition and difference

in thermal expansion coefficient of stacked layers. The issue of out-of plane

deformation/buckling is addressed in this chapter using optimised process of metal

deposition by electroplating and sacrificial layer release techniques.

3.1 Fabrication processes for RF MEMS devices

To understand the effect of fabrication process parameters on the structural reliability,

various fabrication iterations on RF MEMS switches (capacitive and ohmic), Test

structures, Beam array, Torsional Mirrors, SP4T(single pole four throw) and Inductors

are carried out. All the fabrication processes are implemented on 2” silicon wafer. The

fabrication process included the following steps:

a. Oxidation – thermal oxidation (field oxide) for initial one-micron thick layer.

b. LPCVD and PECVD – polysilicon electrode deposition, actuation electrode

insulation and dielectric layer for capacitive switches.

c. Diffusion - for low resistivity polysilicon ‘dc bias lines’, actuation pads and

resistor for ohmic contact switches.

d. Sputter deposition (dc and rf sputtering) and E-beam – Au, Cr and Ti for seed

layers and adhesion promoter for gold, Ti, TiN, Al-Si for underpass area (metal

stack) and Ni for contact pads.

e. Lithography – nine lithography steps involving the use of three type of photoresist

ranging in thickness from 1 – 10 microns.

f. Reactive ion etching for SiO2 and polysilicon etching.

g. Electroplating - for structural layer deposition, using lift–off and etching

techniques.

28

h. Plasma Ashing – for thick hard baked photo resist sacrificial layer removal.

i. Critical point drying – for low temperature removal of sacrificial layer.

Among the above mentioned processes, the main processes those need optimisations are:

1. Polysilicon deposition and doping.

2. Metal (Cr, Au, Ti, TiN, Al) deposition, etching and lift off.

3. Photolithography optimisation for three different photoresist.

4. Electroplating process optimisation.

5. Sacrificial layer removal using plasma ashing and CPD.

Figure 3.1 shows the 9 level mask layout of the devices to be fabricated [1]. The

fabrication process is based on the IC fabrication techniques using surface

micromachining and gold electroplating. The general process compatibility issues,

material selection, thermal annealing during different processes, etc. decides the

overall performance of the fabricated device. Figure 3.2 shows the schematic of the

fabrication steps for RF MEMS Ohmic switch and details are explained in this

section.

Figure 3.1: Complete layout with marking of position on specific devices.

STS Ohmic

Switch

Meander

Ohmic

Switch

STS

Ohmic

Switch

Meander

Ohmic

Switch

Bridge

Test

Structure

Bridge

Test

Structure

Bridge

Test

Structure

Bridge

Test

Structure

Bridge

Test

Structure

SP4T

Switch

SP4T

Meander

Ohmic

Switch

STS Capactive

Switch

CPW

Torsionl mirror

Test

Structures

Test

Structures

SP4T

CPW

Self Actuated

Capactive Switch

CPW

S

P

D

T

Inductor

Torsion

mirror

AM(L) AM(R)

COMPLETE

LAYOUT

29

A low-loss, 2", p-type, <100>, 5 KΩ silicon wafer is used as substrate for device

fabrication. The wafer is cleaned using four different cleaning steps in succession.

• Degreasing: Removes organic and oily contaminants from the surface.

• RCA 1, RCA2: Removes organic and metallic contaminants from the wafer surface.

• Piranha Cleaning: Removes heavy metal particles from the wafer surface.

• HF Dip: HF dip removes native oxide from the wafer surface formed during piranha

cleaning.

An insulation layer of 1000 nm of silicon dioxide is grown over silicon surface using

thermal oxidation. The thickness obtained in the case of dry oxidation is limited to few

nm only; a combination of dry-wet-dry oxidation is used to obtain larger oxide thickness.

The oxidation parameters for 1 µm silicon oxide are as follows:

• Furnace temperature in 3 zones: 846ºC, 1050ºC, 821ºC.

• N2 flow rate for purging: 85cc/min for 3 hours, saturate furnace temperature.

• O2 flow rate for dry oxidation: 35cc/min for 15 minutes

• O2 flow rate for wet oxidation: 20cc/min for 155 minutes

• O2 flow rate for dry oxidation: 35cc/min for 15 minutes

3.1.1 Polysilicon deposition and doping

The actuation pads, resistor for ohmic contact switches and the DC bias lines for the

switching structures are patterned in polysilicon. A polysilicon layer of 0.6 µm thickness

is obtained using LPCVD techniques and the process parameters are shown in table 3.1.

Since undoped polysilicon has low electrical conductivity, it can’t be used as metal lines

for DC biasing. The conductivity of polysilicon layer is enhanced by phosphorus

diffusion at high temperatures followed by annealing. The same polysilicon layer is also

used to make biasing resistors for ohmic contact switches which requires a precise value

of sheet resistance (240Ω/□). Table 3.2 gives the summary of experiments conducted to

obtain desired sheet resistance value for the polysilicon. Diffusion process is optimized

by multiple iterations until a repeated value for sheet resistance is obtained. Table 3.3

shows the results of optimized phosphorus doping recipe used for fabrication process.

Phosphorous doping is carried out for 7.5 minutes at 950°C and 15 minutes at 900°C, to

obtain a sheet resistivity of nearly 240Ω/□.

30

Figure 3.2: Fabrication process flow for RF MEMS Ohmic switch.

Table 3.1: Polysilicon Deposition Process

S.No. Polysilicon Process Steps

1 Temp. 6250C 6300C 6200C

. 1st Zone 2nd Zone 3rd Zone

2 Gas Flow: Silane (SiH4)

3 Flow Rate: 50 cc/min (38.4%)

4 Process Time: 29 minutes

5 Pressure: 0.240 Torr

6 Thickness: 6000Å

31

Table 3.2: Polysilicon sheet resistance optimization

Table 3.3: Polysilicon optimized doping recipes

First level lithography is used to define polysilicon actuation electrodes and interconnect

lines for the RF MEMS switch. The reactive ion etching (RIE) of polysilicon is followed

by the photoresist removal in acetone, piranha cleaning and dip in dilute HF. Figure 3.3

shows the first level mask layout, optical images of patterned actuation electrodes and

process cross section view. An over etching polysilicon is observed after the optical

inspection of defined patterns. Over etching of polysilicon can result in change in

geometry, leading to deviation of final switch performance from the designed results. For

example, over etching of actuation electrodes would result in small actuation area and

hence increase in actuation voltage. The next step is the deposition of 350 nm of silicon

dioxide layer using PECVD process. For 350 nm of SiO2 deposition, silane SiH4 (5.4cc),

Nitric oxide N2O (100%) and Nitrogen (31%) are reacted in a plasma chamber at 300ºC

for 14 minutes. This isolation layer prevents the electrical short between the movable

bridge and the actuation electrodes.

Second level lithography defines the contact holes in the SiO2 layer. The contact holes are

used for interconnection between polysilicon lines and metal lines. These metal lines are

connected to metal pads for biasing voltage. Reactive ion etching (RIE) technique is used

Step W#S1 W#S2 W#S3 W#S4 W#S5

Time 25 min 15 min 7.5 min 7 min 5 min

Temperature 9500C 9500C 9500C 9500C 9500C

Anneal Temp. 10000C 10000C 10000C 10000C 10000C

Anneal Time (min) 20+10 (O2 +N2) 20+15 (O2+N2) 10 (N2) 10 (N2) 10 (N2)

SHEET RESISTANCE MEASUREMENT

Before Annealing (i) 28.8Ω/□

(ii) 28.9 Ω/□

45.3 Ω/□

44.8 Ω/□

164Ω/□

165Ω/□

191.3Ω/□

200.0 Ω/□

301 Ω/□

350 Ω/□

After Annealing (i) 38.2 Ω/□

(ii) 37.2 Ω/□

(iii) 38.0 Ω/□

76 Ω/□

78 Ω/□

76 Ω/□

237 Ω/□

248 Ω/□

258 Ω/□

260 Ω/□

266 Ω/□

274 Ω/□

400 Ω/□

420 Ω/□

489 Ω/□

Step W#A1 W#S3

Time (min) 15 (with POCl3) + 10(without POCl3) 7.5(with POCl3)

Temperature 9000C 9500C

Annealing Temp 10000C 10000C

Annealing Time (min) 5 (O2)+ 10 (wet) + 5 (O2) + 5 (N2) 5 (N2)

Sheet resistance measurement

Before Annealing 135± 10 Ω/□ 160± 5 Ω/□

After Annealing 220 ± 10 Ω/□ 240 ± 10 Ω/□

32

to open the contact holes in SiO2 layer followed by photoresist removal. Figure 3.4 shows

mask layout, optical micrographs of the contact holes openings in the oxide layer and

cross section view after second level of lithography.

(a) (b) (c) (d)

Figure 3.3: (a) Mask layout (b) Optical micrographs of patterned photo resist on

polysilicon electrodes and polysilicon connection pads. (c) Optical micrographs of

patterned electrodes after RIE and (d) cross section view of pattern layer.

3.2 Multilayer metal (underpass area) deposition, etching and Lift off

The part of the transmission line under the bridge is fabricated using a multi-layered stack

of Ti/TiN/Al/Ti/TiN. The stacked multilayer provides good adhesion, smooth contact

surface and low resistivity path for signal transmission. The important steps are:

Pre deposition metal clean dip in 5% HF solution for 2 - 3 seconds.

Sputter deposition of Ti / TiN / Al / Ti / TiN, for deposition time 6 min / 10

min / 14 min / 12 min / 16 min respectively, resulting in thickness for Ti ≈ 34

nm, TiN ≈ 80 nm, Al ≈ 400 nm.

Patterning of multilayer metal (lithography 3): Positive photoresist (S1813) is

coated at a speed of 4500rpm, RAMP 8000, for 30 seconds and prebaked for

25 minutes at 90⁰C. The PR is exposed for 5 seconds (intensity 8 - 9 mW/cm2)

SiO2

Polysilicon

Si

33

followed by developing time of 60 seconds. The post bake step is at 120⁰C for

30 minutes.

Figure 3.4: (a) Mask layout of polysilicon electrodes covered with PECVD silicon

dioxide. (b) Optical micrographs zoomed view of contact holes, opened in SiO2 layer. (c)

Cross section view of pattern layer.

3.2.1 Etching of metallic layer

The multilayer metal etching is one of the most important steps in fabrication and is

performed in following steps:

TiN Etching (Type TiN 22-7): TiN etchant is used at temperature 20⁰C, for 25

seconds. The etchant composition is HF + Nitric Acid – a proprietary composition

of the vendor (Transene). Although the etchant should etch TiN only, it is

observed that TiN and Ti both layers are etched out for the time and temperature

combination shown above. The problem is solved by adopting the lift off

techniques mentioned in next section. Although this increases the process

complexity, but the reliability is better.

Ti Etching (Type TFTN): In order to remove any traces of Ti left from the

previous step ‘Transene Ti etchant’ is used at recommended temperature of 70⁰C,

(a) (b) (c)

34

for 40 seconds.

Au Etching (Type TFA): Etch rate of Au etchant is 28Å/sec at 250C. The

temperature of Au etchant is kept at 25ºC and etching time is approximately 70 -

75 seconds, 8 - 10 seconds of ultrasonic vibrations in small steps (2 seconds each)

is required to remove Au seed layer from perforations.Wafer is rinsed in DI water

after etching.

Cr Etching (Type TFD): Etch rate of Cr is 25 Å/sec at 40oC, the solution consist

of sulfuric acid and nitric acid. Cr etchant is kept at 40ºC and etching time is

approximately 20 seconds with one second of ultrasonic vibrations after each five

5 seconds. Over-etching is desirable to ensure removal of Cr seed layer from

perforations. After Cr seed layer etching using Transene etchant (TFD), wafer

surface retains contaminants. To avoid this contamination, wafers is dipped in 2%

H2SO4 solution for 2 - 3 seconds immediately after Cr etching followed by 5 min

rinsing in DI water.

Al Etching (Type F): Etch rate of Al etchant is 100Å/sec @ 50oC. The etchant

constituted of phosphoric acid and acetic acid .Wafer is rinsed in DI water after

etching.

3.2.2. Lift off process

The lift off process is used as an alternate to metal etching and pattern metal at desired

area [2]. In this case lithography of desired pattern is followed by metallisation as shown

in schematic of lift off process (figure 3.5). The following steps are considered during lift

off:

Thickness of photoresist must be more than 2-3 times of metal thickness.

Metal deposition should be carried out using E-Beam.

Sputtering can be used for metal deposition with low power (400W) and

minimum distance between electrodes.

Sample should place in acetone for 30 minutes.

Sometimes manual cleaning of the substrate with clean room wipes helps

to remove photoresist residue after acetone dip.

35

Figure 3.5: Fabrication process step for lift off.

The total thickness of the multilayer stack is matched with the thickness of actuation

electrodes (600nm). The height difference between the underpass and the actuation

electrodes would lead to a complex and non-uniform bending during actuation.

During the second run of fabrication only aluminium metal of thickness 600nm is used as

underpass layer, due to unavailability of multi-layer metal stack. The Al is deposit at two

different RF power 400 and 600W, at base pressure 5x 10-3

torr for 20 minutes. The high

RF power (600W) and distance between electrode results in photoresist (PR) burning on

the lift off sample as shown in SEM micrographs (figure 3.6). This PR burning is avoided

by using low RF power of 400W and E-beam for metal deposition. The third lithography

step defines the underpass area of the transmission line in aluminium and the contact pads

on the polysilicon connection lines, mask layout and respective optical micrograph after

Al pattern is shown in figure 3.7.

The deposition and patterning of underpass area is followed by the 100nm of PECVD

SiO2 deposition, which acts as a dielectric layer for the capacitive type switch. The down

state capacitance of the capacitive switch depends on thickness, surface roughness and

dielectric properties of this layer. The fourth lithography defines via holes through which

underpass area gets connected to the input and output transmission ports in thick gold.

Figure 3.8 shows mask layout and optical micrograph of fabricated structures with via

holes opening in oxide layer over central overlap area and zoomed view of polysilicon

line, connection pads and underpass bump area.

PR profile for Lift-off

Metal deposition from E-beam or sputtering

Metal pattern after lift off

36

Figure 3.6: Photoresist burning after Al metallisation.

Figure 3.7: (a) Mask layout of polysilicon electrodes covered with PECVD silicon

dioxide, metal on underpass and contact pad. (b) Optical micrographs of fabricated

underpass metal contact area, poly resistor with contact pad and ground line.

In the next step an additional Cr (30 nm)/Au (150 nm) metal layer is sputter deposited

using lift off process over the underpass area oxide layer to form a floating capacitor. The

photoresist mould is defined as a result of fifth level of lithography for the lift off process.

This fabrication step is only useful or dedicated to capacitive switches. This floating layer

helps in improving the down state capacitance of the switch and hence the capacitance

ratio. During the switch actuation, the movable beam comes in contact with this floating

metal layer and connects the floating capacitor to ground, thus achieving the maximum

down state capacitance.

Al

Al+PR

Al

Al+PR

(a) (b)

Al (600nm)

37

Figure 3.8: (a) Mask layout, (b) optical micrograph of fabricated structures with via

holes opening in oxide layer over the central overlap area and (c) zoomed view of via

holes with polysilicon line, connection pads and underpass bump area.

3.3 Photoresist Optimization

The thickness variations for defining the complete bridge ranges from 1 to10 microns and

requires three different kinds of photo resists. The normal pattern definition such as

polysilicon, contact holes (SiO2), metal and via holes is achieved by using high resolution

resist (S1813) where thickness ranges from 0.5 - 1.5 microns. The spacer layer HIPR

6517 (high resolution positive photoresist) is optimized to achieve the thickness ranges

from 2-4 microns. The spacer layer PR also needs to be stabilized by baking at high

temperatures and large number optimization experiments are conducted to characterize

the profile of baked layer. The formation of bridge using electroplating requires photo

resist thickness in the range of 3-5 microns and capable of withstanding the subsequent

electroplating environment for longer durations. For this purpose appropriate resist (AZ

9260, AZ P4620) and developer (AZ 400K) is used. Figure 3.9 shows the various resist

details with typical profile requirement specific to applications [2]. Table 3.4 shows the

methods and process required for photoresist to achieve the desire profile.

(a) (b) (c)

38

(a) S 1813,1818 (1-2 m) (b) HiPR 6517 (2-4m) (c) AZ 4620,9260 (4-10m)

Figure 3.9: Positive photoresist typical profiles.

Table 3.4: Methods for positive photoresist to achieve desire profile

3.3.1 Photolithogrphy surface preparation

Photoresist adhesion to typical wafer surface such as SiO2 and metals is critical to

faithfully replicating the photoresist pattern in etching process. There are several factors

which can interfere with photoresist adhesion [3]:

If the base solvent has a higher degree of interaction with the wafer surface than

the photoresist base resin, the solvent can push the resin away from wafer surface.

Later during soft bake the solvent may evaporate, but the resin may be constrained

by the photoresist film from the resulting gaps. This issue is addressed by good

photoresist formulations [4].

The resin-resin interaction can be stronger than the resin-substrate interface

interaction, particularly if the base solvent is badly matched to the resin. The resin

will then form tight coils to minimize its energy, lowering its interaction with the

substrate. The intrinsic interaction of the resin with the wafer surface is however

the most important factor in adhesion and once again this addressed during PR

formulation [4].

Surface contamination particularly due to moisture. Water has a very high affinity

for SiO2. Moisture interaction with SiO2 is a particular problem because SiO2

readily becomes hydrated due to humidity. Surface moisture may take the form of

Required Process, Applications Photoresist Thickness Methods/ Process

Normal, general S 1813,1818 1-2 m Moderate dose

Moderate develop time

Spacer, anchor posts

HiPR 6517 2-4m Low dose

Developer dominant

Lift-off, e-plating

AZ 4620,9260 4-10m High dose

low dependence on developer

Si-Substrate

Si-Substrate

Si-Substrate

39

adsorbed surface moisture or chemically bonded OH-Silanol group. Surface

moisture is reduced by bake at less than 100C, but silanol groups require a much

higher temperature bake immediately before photoresist coating.

In order to minimize moisture effects on the PR adhesion, a variety of surface pre-

treatment techniques are used. A liquid "adhesion promoter", such as

"hexamethyldisilazane" (HMDS), is applied to promote adhesion of the

photoresist to the wafer. The phrase "adhesion promoter" is a misnomer, as the

surface layer of silicon dioxide on the wafer reacts with the agent to form

Methylated Silicon-hydroxide, a highly water repellent layer. This water repellent

layer prevents the aqueous developer from penetrating between the photoresist

layer and the wafer's surface, thus preventing lifting of small photoresist structures

in the (developing) pattern.

Photoresist Coating

During spin coating, the centrifugal force of the substrate spinning with several 1000

rounds per minute (rpm) distributes few ml of resist over the substrate. The resist film

thickness attained by spin coating represents the equilibration between centrifugal force

and solvent evaporation, both increasing with spin speed. Figure 3.10 shows the

photoresist spin coat cycle and Headway PMW 32 coating unit used during PR

processing.

Influences on the resist film thickness

The resist film thickness given for a certain spin speed holds for sufficiently long spin

times, when the resist spin-off is completed. As shown in the figure 3.11, the spin times

required to attain the final film thickness increases with the resist viscosity. Low spin

speeds also increase the time for a constant resist film thickness. This time dependency

not only allows the film thickness to be adjusted for spin speed, but also the spin time.

However, this is only a reasonable procedure for attaining thin and thick films. For thin

films (approx. < 10 μm), the spin times is long for more reproducible results. The

photoresist spin speed curve is an essential tool for setting the spin speed to obtain the

desired resist thickness (figure 3.11). The final resist thickness varies as one over the

square root of the spin speed and is roughly proportional to the liquid photoresist

viscosity [2, 4].

40

Figure 3.10: (a) Simple photoresist spin coat cycle and (b) Spin coater unit.

Figure 3.11: Effect of spin speed on PR film thickness [4]

Hot Plate vs. Oven baking

Hotplates have several advantages over convection type ovens [5]:

Decreased bake time

Increased reproducibility

Better film quality.

In conventional ovens formation of different temperature zones, is a problem and can

severely affect film quality and reproducibility. In an oven the heating rate of a substrate

depends not only on the heated air flow past a substrate but also on its proximity to other

cold substrates. Thus the heating rate for each substrate in a cassette of substrates is less

than if each substrate is baked alone. Substrates near the ends of a cassette heat faster than

the substrates in the middle, thus producing a non-uniform heating. Particle generation

also occurs within a standard oven. In a forced-air, convection oven, substrates are

Spin Time

Ramp

Spread

time

Time

Spin

spee

d

Resist

Dispensed

41

commonly exposed to a flow of particle laden air for at least 30 minutes. The PR film is

very susceptible to these particles.

Disadvantage of conventional ovens over hot plate

In normal oven baking results from baking substrates from the "outside in". Since heat is

applied to the outer surface of the film first, a skin forms on the surface of the film thus

trapping solvents. Upon vaporizing, these solvents form blisters or bubbles which results

in adhesion loss or even bulk film failure. This problem prevails in processes involving

thick film resins.

No skin effect occurs on a hotplate since hotplate baking heats the substrate from the

bottom up. This "inside out" approach offers advantages for thick films since solvents in

the film nearest the substrate are baked off before the film surface seals over. A well

designed hotplate insures uniform baking across the substrate. Since the substrate

intimately contacts a surface of a known constant temperature. Bake times is measured in

seconds, rather than minutes or hours, as in conventional ovens (figure 3.12). Reduced

vulnerability to particulate contamination is a major advantage of hotplate baking. Only

condition is ambient clean room air passes over the substrate. In general positive photo

resist baked for 30 minutes at 90°C in conventional ovens while 30 seconds at 115°C on

hot plate.

Edge Bead: Especially in the case of coating thick resist films (HiPR 6517, AZ9260 and

AZ P4620), edge bead is formed which may cause sticking to the mask as well as an

undesired proximity gap during exposure (with a reduced lateral resolution as a

consequence). In case no automatic edge bead removal is possible, initial stages solution

to avoid/lower the edge bead are:

An elevated spin-speed for a shorter time.

A ‘spin-off’ of the edge bead by abruptly increasing the spin speed at a

certain stage of spin coating.

A multiple coating with an elevated spin speed for each coating cycle.

For thick or solvent rich resist films, a delay between coating and soft

bake prevents the edge bead growing during soft bake due to the thermally

reduced viscosity. The delay time depends on the resist film thickness and

is shortened by applying moderate temperatures.

42

Edged substrates: manual cleaning of the substrate from the edge bead

with clean room wipes. Exposure and development of the edge bead is also

possible using a ring mask.

Figure 3.12: Typical profile of various baking methods [5].

3.3.1.1 Recipe for resist S1813

Resist S1813 allows thicknesses from 1.2 to 2.0 µm. The spin speed is adjusted for each

recipe so that the desired thickness is obtained. The positive photoresist S1813 is used in

wide variety of process flow to perform wet etch, dry etch and even lift-off processes. In

present process S1813 is used for polysilicon electrode patterning, contact and via hole

opening, metal etching and lift off. The process parameters for S 1813 are shown in table

3.5. The effect of exposure time (3,6 and 9 seconds) is observed using Focus Ion Beam

(FIB) SEM cross section micrographs shown in figure 3.13 (a-c), the wall angles become

smaller as exposed areas grow with increased dose.

Table 3.5: Process parameter for S 1813

Coat 4500 rpm for 30 sec

Soft bake 90C for 25 min. conventional oven

Expose 6-7 sec

Develop 1 min.

Wall angle 75

Line width 2.5μm

Conventional Oven IR Hot plate

30

32

4

3

3

2

1

2

2

Pre bake time (minutes)

150

32

100

32

50

32

25

32

Tem

p. (0

C)

43

Figure 3.13: S 1813 (a) exposure 3 sec. (b) exposure 6 sec. (c) exposure 9 sec.

3.3.2 Spacer layer photoresist optimisation

Sacrificial layer (spacer payer) for fabrication of suspended membrane is deposited and

patterned using positive photoresist. The use of material as a sacrificial layer depends on

the application, e.g. the temperature range in the following processing steps, the chemical

treatments followed after this step and surface profile after lithography. A variety of

metals, dielectrics and photoresists have been reported as sacrificial layers [6-9].

However, in the present case HiPR 6517 positive photoresist is used as it provides desired

contour by controlling using pre bake and post bake temperatures. After high temperature

baking at 180-200ºC PR turns into hard plastic layer and withstand in harsh environment.

The photoresist HiPR in general is used to obtain a thickness of 2.2 μm without prebaking

and without problem of edge beads. However, a thickness of 3.6 μm after post baking is

required for MEMS switches to achieve a gap height of 3 μm from the transmission line.

Thus, the photoresist coating process is optimized and includes the following steps (figure

3.14):

Step 1: Acceleration, filling and thickness decision,

Step 2: Edge bead removal,

Step 3: Deceleration.

Figure 3.14 shows the timeline graph for the photoresist coating to achieve the desired

thickness. Optimised recipe for the HiPR 6517 is shown in table 3.6, using the same

recipe optical micrograph of the fabricated structure with profile measurement is shown

in figure 3.15 (a, b). Surface profiler measurement of spacer layer before and after the

baking of photoresist is shown in figure 3.16. The overall thickness of 0.5 micron reduced

after baking at 1800C as depicts from figure 3.16. Cross section views of structure are

helpful to find the resist angel, next paragraph gives the details and requirement of resist

angel tuning.

(a) (b) (c)

44

Figure 3.14: Spin coating programme for HiPR 6517HC photoresist

Table 3.6: Optimised Recipe for HiPR 6517

Coating Step Step 1 Step2 Step3 Exp.

time

(Sec)

Dev.

time

(Sec)

Thickness (µm)

Before

Bake

After

Bake

Speed (RPM)

Ramp (RPM/Sec)

Time(sec)

800

4000

25

2600

4000

1

0

500

0

20 60 4.1 3.5

Figure 3.15: (a) Optical micrographs after spacer layer and (b) surface profiler

measurement (Dectek 6M).

Figure 3.16: Surface profiler measurement of spacer layer thickness (a) after deposition

4.1 µm and (b) after baking 1800C for ½ hour 3.5 µm.

Sp

eed

(R

PM

) Time (sec)

Step 2 Step 3 Step 1

Direction of

profile scan

Spacer layer thickness 3.5-3.6µm

(a) (b)

(a) (b)

45

Figure 3.17: Cross section profile of HiPR 6517 using Focused Ion Beam (FIB) SEM

(CeNSE IISc Bangalore).

Figure 3.18: Spacer layer profile control with exposure time.

Resist angle tuning

The mechanical reliability of MEMS switch depends on the quality of anchor posts, as

major failure in MEMS switches occurred at anchor points during switching. For reliable

operation the anchor thickness is comparable to the bridge thickness [6-9]. The resist

angle is fewer than 450 at the (steepest) position of the anchor. If we have a steeper angle,

more than 450, the metal thickness of the anchor is significantly thinner than the rest of

the bridge. Figure 3.17(a-c) shows cross section view of spacer layer near the anchor post

is measured using Focused Ion Beam (FIB) SEM. The resist slope angel of HiPR 6517 is

less than 450, the angel is tuned with exposure, developing and baking time [6]. The

figure 3.18 shows the structures (alignment mark, spacer layer pattern) (a) after 15

seconds and (b) 30 seconds of exposure time. The variation of the resist angle with time

and temperature is seen from the SEM cross section images shown in figure 3.19 (a, b).

(a) (b) (c)

Bridge

Anchor

Spacer layer profile

<450

(a) After15seconds of exposure (b) After 30seconds of exposure

46

For comparison the SEM images for HIPR 6517 have been scaled to the same

magnification and compared. It can be easily seen that the resist angles decreased with

both baking temperature and baking time. The spacer layer profile is optimised and

following section covered the thick resist recipes optimisation used for electroplating.

Figure 3.19: The SEM images for HIPR 6517 resist (a) Baking time 25min. at120oC (b)

Baking time 25min. at1850C.

3.3.3 Thick resist optimisation

For the suspended bridge fabrication a photoresist mould is formed using AZ P4620

positive photoresist. For this step, the required resist thickness is 5 – 5.5µm. The AZ

P4620 photoresist can be used for coatings up to 20 µm in a single step [3]. For 5 µm of

thickness, the resist is coated at very high RPM (6000 RPM, 20000 RPM/sec) arising

problem of uniform filling of photoresist on wafer. Generally, there are two ways to attain

resist film thicknesses of 10 μm via spin coating: either by reducing the spin speed, or by

reducing the spin time. Low spin speeds, however, cause a pronounced edge bead and

sometimes even prevent the resist from tearing off the substrate with a non-reproducible

resist film thickness as a consequence. Thus, spin coater is programmed to coat the wafer

in two steps. In first step photoresist is spread on the wafer uniformly and second step

decides the thickness of the photoresist. Multi step spin coating programme as shown in

figure 3.20 is used for edge bead removal. Prebaking is also a crucial step in AZ P4620

lithography as oven baking causes cracks in photoresist film. The cracking of photoresist

during prebake in oven occurs due to early drying of photoresist surface layer. As

thickness is high, the solvent in bulk photoresist is trapped due to surface layer drying.

The release of this solvent from surface causes cracks in photoresist. Therefore, prebaking

in oven is done by providing temperature ramp. The cracking problem is solved by

prebaking the photoresist on hot plate as discussed above in section 3.3.1. On hot plate,

(a) (b)

47

heating or drying of photoresist starts from the bottom surface and edges of the

photoresist, thus avoiding cracks. Also, AZ P4620 is highly sensitive to atmospheric

conditions, such as: humidity, temperature and time between consecutive steps during

lithography, e.g. a delay between prebaking and exposure can change the exposure dose

and developing time. In that case AZ 9260 is good choice for process repeatability, this

resist is pretty stable than AZ P4620. The process steps for AZ P4620 photoresist for 5-

5.5 µm are:

HMDS coating at a spin speed of 4500 RPM, 8000RPM/sec RAMP for 30

seconds and oven baking at 90ºC for 5 minutes.

Photoresist is coated using two step recipes shown in table 3.7.

After coating, prebaking of photoresist for 35 seconds at 60ºC on hot plate is

followed by lithography exposure time of 5 seconds and a developing time of

80 seconds.

In some cases, delay between prebaking and exposure changes the exposure

dose and developing time. This result in some PR traces, these PR traces is

resolved by using O2 plasma ashing.

Table 3.7: Recipe of AZ P4620 photoresist for 5µm

Coating Step Step 1 Step 2

Spin Speed (RPM) 400 6000

RAMP (RPM/min) 20000 20000

Time (sec) 5 15

Figure 3.20: Multi-step spin coating program for minimizing the edge bead.

t 1 t 2 t 3 t 4 t 5

Speed (RPM)

Time (sec)

Step 1 Step 2 Step 3

Sp

eed

(R

PM

)

48

Table 3.8: Recipe of AZ P4620 photoresist for 10 µm

Coating Step Step 1 Step 2

Spin Speed (RPM) 500 2500

RAMP (RPM/min) 300 300

Time (sec) 20 10

The optimized recipe for AZ P4620 photoresist for 10-11 µm is:

Photoresist is coated using recipe shown in table 3.8.

After coating, prebaking of photoresist for 55 seconds at 60ºC on hot plate is

followed by lithography exposure time 16.5 seconds and a developing time of

130 seconds on SiO2 substrate.

Exposure time reduce to 14 seconds on gold substrate.

As mentioned above AZ P4260 is highly sensitive resist. Thus, new resist AZ 9260 is

procured and recipes are optimised for thickness ranges from 5 - 10 micron. The AZ 9260

is a thick photoresist with high viscosity and transparency. It is optimized to fabricate

mould for electroplating bridge and reinforcing in MEMS switch with stability and

repeatability. The photoresist (AZ 9260) is spin in three steps as shown in table 3.9. The

foregoing recipe (Table 3.9) is used to obtain films of varied thickness. The second step

mainly decides the thickness of the film. During this step, almost all of the solvent is

evaporated and a solid film is formed. The third step does not affect the thickness; it only

accelerates the solvent evaporation. The ramp plays a significant role in deciding the

uniformity of the deposited film.

Table 3.9: Coating recipe for AZ 9260 photoresist for thickness optimisation

Process Step 1 Step 2 Step 3

Spin Speed (RPM) 300 Speed varied* 0

RAMP(RPM/min) 5000 5000 1000

Time (sec) 5 15 0

* Speed varied from 1000-6000 with a step of 500

Two iterations are performed to analyse the effect of the ramp on uniformity as shown in

figure 3.21. First iteration is accomplished at lower ramp (300rpm/sec) and other at

higher ramp (5000rpm/sec). The 3D surface profiles of photoresist uniformity are shown

49

in figure 3.21 for lower and higher ramp respectively. The standard deviation for lower

and higher ramp is 0.8500 and 0.0933 respectively. It is observed that ramp affects the

uniformity and for deposit a uniform layer higher ramp is required.

After coating prebake is given for 15 sec at 60ºC (hotplate). The exposure time is 20sec

and photoresist is developed using a potassium-based alkaline developer (Hoechst,

AZ400K), diluted by 1:4 in deionized (DI) water. The developing time is 130 sec. Effect

of spin speed on the photoresist thickness is illustrated in figure 3.22. Post baking is not

required for this photoresist. Figure 3.23 shows the SEM micrographs of fabricated AZ

mould and perforation. Photoresist profile is observed using tilted view of the

micrographs. After the optimisation of photoresist process next step is deposit metal as

structural layer. The electroplating process for metal deposition is optimised in next

section.

Figure 3.21: Effect of ramp on uniformity of photoresist AZ 9260.

0 1000 2000 3000 4000 5000 6000

4

6

8

10

12

Th

ick

ne

ss

(u

m)

Spin speed (rpm)

Ramp=5000 rpm/sec

Figure 3.22: Spin speed vs. thickness of AZ 9260.

Wafer 1, ramp=300 rpm/sec Wafer 5, ramp=5000 rpm/sec

50

Figure 3.23: SEM micrographs of AZ mould and perforation.

3.4 Electrochemical Deposition

Electrochemical deposition involves the reduction of metal ions from aqueous,

organic, or fused-salt electrolytes. The reduction of metal ions Mz+

in aqueous solution

is represented by

Mz+

(metal ion in solution) + z e− (electrons) → M (metal deposit)

Two processes are used to provide the electrons for the reduction reaction: (1)

electroplating (or electroforming), where an external power supply provides the

electrons, (2) electroless deposition, where a reducing agent provides the electrons [10,

11]. In MEMS electrochemical deposition is commonly used to deposit surface

coatings, or in the case of electroforming, for producing an entire microstructure or

device. In electroforming, micro structured moulds of different materials (e.g.,

polymers/resist, silicon) are electrochemically filled with metals such as gold, nickel

and copper.

3.4.1 Electroplating

The material properties of electroplated metal is strongly governed by electrolyte

chemistry (type and concentration of ions, pH of solution and additives), physical

parameters ( temperature, current, fluid), and the property of the substrate (surface

quality, shape). The electroplating process is optimized depending on the shape of the

desired microstructures and metal to be deposited. The basics of electrochemical

deposition are found in several excellent books [10 - 14] and are summarized in this

section.

51

3.4.1.1 Electrochemical Reactions

The general setup and operation of an electrochemical deposition cell are shown in

figure 3.24. Two electrodes are immersed into an electrolyte. By applying an electric

current, reduction (electron intake) occurs at cathode, and oxidation (electron liberation)

occurs at anode. Metal ions are released at anode via oxidation and adsorbed at cathode

via reduction. Substrate is used as cathode so that metal ion is reduced to form a solid

metallic layer. The anode is dissolved so that concentration of electrolyte is maintained

during electroplating. The two partial reactions are expressed by the following equations.

Figure 3.24: Schematic of a general electrochemical deposition cell.

Reduction (cathode): Mz+ + z e− → M Deposition of metal

Oxidation (anode): M → Mz+ + z e− Dissolution of metal (for a soluble anode)

The steady oxidation of the anode (a metal to be deposited) ensures a constant

replenishment of metal ions in the electrolyte. Sometimes inert anode such as platinized

mesh is also used. In that case, replenishment of electrolyte is made by manual addition

of metal salts into plating bath. The theoretical mass of metal deposited at cathode

( ) is governed using Faraday’s law as

⁄ (3.1)

Where, M = Molar mass the deposited metal;

I = Current,

t = Time

z = Valency

F = Faraday constant (96500 C).

52

Decomposition of water leads to some additional reactions at anode and cathodes.

Oxidation of water leads to production of oxygen gas at anode and reduction of water

leads to release of hydrogen gas at the cathode. Total overall current is distributed among

these different reactions. The percentage of the total current associated with the reduction

of metal is defined as the cathodic current efficiency γ, and is calculated by the ratio of

the deposited effective mass meff to the theoretical mass mtheo

⁄ (3.2)

If production of hydrogen gas is not suppressed at cathode, it leads to reduction in

current efficiency.

3.4.1.2 Deposition Process

In the bulk electrolyte, cations are enclosed in a complex shell. This complex shell

consists of water molecules (hydration shell) or other complexing agents such as

sulfite or cyanide. Before applying a current, the ion concentration is homogeneous at the

electrode surface and in the bulk solution. When a current is applied, metal ion is

consumed at the electrode and a depletion region so created extends farther away into the

bulk as the deposition proceeds.

Movement of the complex metal ions in the electrolyte solution is governed by three

different mass transport mechanisms: migration, convection, and diffusion. In most of the

deposition processes, the conductivity of the electrolyte is relatively high and applied

potentials are moderate. Thus most of the electrical field drops across the electrical

double layer in front of the electrode and field -induced migration is minimal. Therefore

the predominant transport mechanism is convection (due to stirring or agitation of

electrolyte) and diffusion with former dominating in the bulk and later at electrode

surface. Figure 3.25 illustrated the overall deposition process.

In summary, the reduction of the metal ions at the cathode is divided into four parts: (1)

diffusion of the solvated or complexed metal ions from the bulk to the electrode

surface, (2) dehydration and transport of the cations through the electric double layer,

(3) cationic reaction at the solution–solid interface (ion uptake and electron transfer),

and (4) surface migration and incorporation of the adsorbed metal atoms into the lattice

[11].

53

Figure 3.25: Schematic diagram of the electrochemical deposition process.

Figure 3.26: Concentration of metal ions as a function of distance from the cathode

(a) for direct current and (b) for pulse current plating [14].

In case of pulse-plating, the pulse current density is limited by the depletion of ions in

the pulsation layer, whereas the average current density is limited by the concentration

gradient in the outer stationary d i f f u s i o n layer [14]. Thus two diffusion layers are

defined: a pulsation layer in the immediate vicinity of the cathode and a stationary layer

up to the point where the mass transfer is controlled by convection (figure 3.26).

The final step in the formation of a crystalline metal deposit is the incorporation of the

adatoms into the lattice. The adatoms are preferentially incorporated at active lattice

sites such as grain boundaries, imperfections, or pre-existing built-up adatom clusters on

the surface. If the adsorption of an adatom ensued away from an energetically stable

Alignment H2O molecules Removal of H2O Hydrated metal ion

+ - +

(4)

(2) (3) (1)

+ +

+ cation

- electron

water molecules or

complexing agent

Bulk Solution Diffusion layer Electric

double layer Cathode

(a) (b)

54

position, surface diffusion may transport the adatom to another active lattice site on the

surface. The process of either building new grains (nucleation) or contributing to the

growth of existing grains is define the formation of metal deposits in electroplating [10].

3.4.2 Electroplating Process Parameter

The parameters generally controlling the composition, structure and properties of the

deposit are briefly reviewed in following section.

3.4.2.1 Conditions affecting the structure and properties

The environment in the immediate vicinity of the cathode influences the characteristics

of electrodeposited metals. Electrodeposits are crystalline in nature and the form of

deposit mainly depends on two factors: (a) Rate of formation of the crystal nuclei at

cathode by ion discharge and (b) rate of nuclei growth into larger crystals. When

condition favours the rapid formation of fresh nuclei near cathode surface, the layer

consists of small, fine-grained crystals leading to a smooth and hard deposit. On the

other hand, if the circumstances favour rapid increase in nuclei size, the deposited layer

consists of large crystals which are rough in appearance. Many parameters do influence

the formation of crystal nuclei and its size. Some of them are considered in this study.

Current Density: At low current densities, discharge of metal ions occurs at a slow rate

allowing for sufficient crystal-nuclei growth time. Consequently the formation of fresh

nuclei is unnecessary. The deposits obtained at low current density exhibit a coarse

crystalline structure. At increased current density, the rate of discharge of the ions is

large, and fresh nuclei tend to form and the deposited layer consists of smaller crystals.

Thus increase in current within certain limits yield deposits that are fine grained.

However, there is a limit to this improvement because at very high current densities the

crystals tend to grow at cathode towards that regions where the solution is more

concentrated, thereby creating trees or nodules in the film [13].

Electrolyte composition: This includes the compounds supplying the metal ions (to be

deposited) and the supporting ions. The basic functions of the supporting ions or

compounds are to stabilize the electrolyte, improve solution conductivity, prevent

excessive polarization and passivation (especially anodic), and provide compatibility

with the desired plating conditions. Supporting ions or conducting salts reduce the

current shared by the metallic ions or complexes, making convection (agitation) a more

significant factor.

55

Temperature: Increasing the temperature of electrolyte promotes the diffusion of ions

to the cathode preventing impoverishment which can lead to a rough deposit. It also

increases the rate of growth of the crystal nuclei leading to a coarser deposit. Maintaining

the bath at moderate temperatures, first effect dominates and the quality of deposit

improves. However quality of deposit deteriorates at higher bath temperatures.

Impurities: Electroplated films contain various types of inclusions/impurities. The

sources of these impurities are from one or more of the followings: added chemicals

(brighteners, levellers), particles (for composite films), cathodic products (complex metal

ions), hydroxides of metal to be deposited, and bubbles (hydrogen gas, etc.). Excessive

amount of additives in the electrolyte may cause a brittle deposit leading to break at

crystal interface.

pH: pH of the bath influences the discharge of hydrogen ions, causing the solution at

cathode layer to become alkaline and precipitate hydroxides or basic salts. The inclusion

of a significant amount of these compounds makes the resulting deposit exhibit a fine

grain structure.

3.4.2.2 Current Waveform

Direct current is the preferred mode of current supply for electroplating, a variety of

current modulations techniques also exists viz. triangular, saw-tooth and rectangular

shaped waveforms. Rectangular waveforms are further divided into two variants:

unipolar and bipolar. Table 3.11 illustrates the current waveforms of direct current,

pulse forward current, and pulse reverse current. Different current modulation scheme

affects the plating mechanism differently and thus the chemical and microstructural

properties of the deposited layer can be controlled by varying modulation parameters

[14]. The current waveform for pulsed electrodeposition (forward current) consists of

cathodic pulses (tc), separated by a current pause (tp). Pulse reverse electrodeposition

consists of a cathodic pulse (tc) followed by an anodic pulse (ta), where the current is

reversed for a short time. In addition, a pulse pause (tp) is also used. During the

cathodic pulse, metal ions are deposited on the cathode surface and loosely bound ions

are removed from plating sites during anodic cycle. In pulse plating, mean current density

(im) is defined by amplitude and duration of the various pulses. A pulse waveform having

the same mean current density as that of a direct current has larger peak amplitude.

The advantages of pulse plating over DC plating have been studied extensively. Various

56

metal alloy compositions have been optimized for morphology, magnetic properties, or

mechanical properties [15-17]. Pulse reverse electroplating of copper is used in printed

circuit boards (PCBs) manufacturing to obtain uniform via and trench filling.

3.4.2.4 Theory and types of pulse supply

Current is toggled between ON and OFF state during pulsed plating. During ON period,

the concentration of metal ions next to the cathode surface is depleted and a layer rich in

water molecules is left. During OFF period, metal ions from bulk solution diffuses into

the layer next to the cathode and the cycle repeats itself. During OFF period, desorption

of gas bubbles and impurities occur at cathode.

Pulse plating is being used in real-to-reel selective plating, in automatic tab platters, on

barrel lines, in still plating, electroforming, anodizing, electro-cleaning, electro-polishing

and machining and, recently has been adapted by the semiconductor bump and wafer

plating technologies [18-20]. Pulse power supply have following advantages: increased

plating speed, improved distribution, lower deposit stress, finer grain structure, increased

ductility, improved adhesion, increased micro-throwing power, reduced hydrogen

embrittlement, and decreased need for additives [18].

3.4.4. Electroplating equipment

Various equipment are used for electroplating, ranging from simple to very complex. For

laboratory use, the setup is simple, as shown in figure 3.27. The setup consists of

power supply, hotplate, glass beaker and oscilloscope. Beaker contains the electrolyte

and rotating magnetic stirrer. The temperature of bath is maintained at a specified

constant temperature using the hotplate. A metal plate or platinized titanium mesh is

used as the anode. The power supply is equipped with a pulse module to enable pulse

plating when desired. An oscilloscope may also be used to monitor the applied pulses.

One such custom design electroplating station build in CEERI is shown in figures 3.28.

It can hold a large volume of electrolyte and has monitors for liquid (electrolyte) level

display, pH, and additives, as well as a continuous filtration of electrolyte and a

dummy plating cell for cleaning of the electrolyte. Filtration rids the electrolyte of

particles, which are interfering with the deposit. For large-scale manufacturing,

continuous filtering, salt replenishment, and pH maintenance are important issues.

Also, some baths may generate gaseous by products, so exhaust of these gases are also

considered.

57

Table 3.10: Current waveforms for direct current, forward current, and pulsed reverse

plating

3.4.5 Electrodeposition of gold for MEMS

A gold film is a widely used material for many MEMS devices because of its excellent

stability, low electrical resistivity and high reflectivity for infrared rays [21, 22]. The

application field of the gold film includes low loss RF-MEMS, high performance

electromagnetic, and MEMS mirror with high driving current, high reflective Optical

MEMS device, biocompatible package, etc. In these devices, the gold film has been

deposited by vacuum evaporation, sputtering, electroless or electroplating using surface

activation process or seed layer [21]. Comparing to vacuum evaporation and sputtering,

Current waveform Mean current

im i

im ic c

c + p

im ic c − ia a c + a + p

Direct current

i m

Curr

ent

Den

sity

i

Time t

i c

tc tp i m

Curr

ent

Den

sity

i

Time t

Forward current i m

i c

ta

i a

tc tp

Curr

ent

Den

sity

i

Time t

Pulsed current

58

the gold electroplating process was suitable for deposition on silicon three-dimensional

structure, because it can cover hidden planes conformally. The advantages of both

deposition technologies are in table 3.11.

Figure 3.27: Schematic of a laboratory scale electroplating unit.

3.4.5.1 Comparison of gold electrolyte

Comparison of gold electrolyte is shown in table 3.12. The mostly used electrolyte

electronics industry are cyanide based. But due to the toxicity of the free cyanide formed

during electrolysis, sulfite-based gold processes are the traditional alternative for wafer

applications. However, sulfite-based processes have suffered from issues with solution

stability and the necessity for annealing to achieve the desired deposit hardness.

The gold (I) cyanide complex Au(CN)2- has a stability constant of 1039

, which makes the

solution very stable, and shifts the standard reduction potential of gold (I) from 1.71V to

–0.61V (SHE) [23]. However, in recent years, the health and safety concerns regarding

the use of cyanide have overwhelmed the benefits it brings. In addition, cyanide

containing solutions are incompatible with positive photoresists used in the

microelectronics industry because they attack the interface between the resist film and the

(1) 50°C

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

Cathode: Wafer

Temperature

Anode: e.g., Titanium

filled with metal

Inert gas inlet

Glass

Magnetic stir

Hotplate/stirring

Power

Pulse module

Oscilloscope

(10)

59

substrate, lifting the resist and depositing extraneous gold under the resist. Therefore, the

demand for cyanide-free gold electroplating processes has increased significantly.

Figure 3.28: Photograph of a custom design electroplating system for 2-4” wafer,

electroplating unit for use in a cleanroom (a) Wafer holder j ig with platinized mesh

(b) plating facility for cleanroom (c) Dynatronix pulse power supply.

Table 3.11: Advantages of both deposition technologies

Vacuum Deposition Electroplating Aqueous Deposition

Close tolerances Lower costs

Wide choice of substrates Thicker coatings

Wide choice of coatings Coating complex shapes

Control and modification of deposit properties

Control of residual stress

The gold sulfite complex Au (SO3)2 3-

is the most common alternative to cyanide. This

complex has a stability constant of 1010

, much less than that of the gold cyanide complex.

(b) (a)

(c)

60

Consequently, it is susceptible to disproportionation resulting in the formation of Au (III)

and metallic gold, especially at pH less than 7, where sulfite protonates to form bisulfite.

Therefore, stability is always an issue for sulfite-based gold electroplating solutions, and

stabilizing additives are usually necessary. Gold (I) thiosulfate complex Au (S2O3)2 3-

is

another alternative to cyanide. Its stability constant (1028

) is between cyanide and sulfite

complexes and it is stable in weakly acidic solutions. However, thiosulfate ions

themselves are not stable without the presence of free sulfite. They undergo

disproportionation and produce sulfite ions and free sulfur, which precipitates. Recently,

gold plating solutions containing both sulfite and thiosulfate have also been reported.

Table 3.12: Comparison of gold electrolyte

3.4.6 Gold electroplating experiments

Initially, experiments are carried out for characterization of the electroplating process to

achieve an optimum deposition rate and surface roughness. In the present study, a sulfite

based solution TSG-250TM (Transene, USA) is used for gold electroplating due to its

compatibility with a positive tone photoresist. Process flow decided for the gold film

evaluation is illustrated in figure 3.31.The starting substrate is a chromium/gold (30/200

nm) thin seed layer on top of a Si/SiO2 wafer. Subsequently, the photoresist is patterned

on the seed layer which is used as the cathode during the electroplating process while a

platinized mesh electrode is used as the anode.

Cyanide Based

Cyanide Au(CN)2-

Non-Cyanide Based

Sulfite Au (SO3)2 3-

thiosulfateAu(S2O3)2 3-

Toxic Non Toxic

Better for health and safety

concerns

Non Toxic

Better for health and safety

concerns

Incompatibility with

positive photoresists (attack

the interface between the

resist film and the

substrate)

Compatible With Photoresists Compatible With Photoresists

stability constant of 1039 stability constant of

1010(solution instability require

annealing for deposit hardness)

stability constant 1028

(instability of thiosulfate in

the absence of free sulfite)

SHE 1.71V to –0.61V

pH >7 pH less than 7 stable in weakly acidic

Sulfite protonates form bisulfite

cause instability

Sulfite ions and free sulfur

Recently both sulfite and thiosulfate Plating sol. used

61

Figure 3.29: Process flow used for electroplated Au evaluation.

During the electroplating process, an anode/cathode surface area ratio of 1:1 is used with

a distance of 3 cm between the electrodes. Electroplating is carried out at different current

densities from 1mA cm−2

to 7mA cm−2

for a fixed duration of 10 min at a temperature of

60 0C. The deposition rate and mean surface roughness (Ra) of the electroplated gold are

measured using a Dektak6M profilometer and AFM. The final process parameter is fixed

to deposit gold thickness of ∼2μm at current density of 3.5 mA cm−2

and temperature 600

C for 10min. The measured thickness of electroplated gold on metallic structures of

various devices showed an average deviation of ±0.1 μm. The current density of 3.5

mAcm−2

is selected to obtain an electroplated layer with reduced stress and uniform

deposition [24-28]. Stress is characterized using surface profiler by curvature

measurement method and later using commercial stress measurement system (FSM).

Seed layer formation using

sputtering/evaporation

Cleaning of Wafer Degreasing,

RCA, Piranha and HF dip

Electroplating of Gold for MEMS

mechanical structures

Bath selection - Non Cyanide

DC Rectifier Pulse Rectifier

Constant Current source

Low stress deposit metallic structure with

minimum grain size and low roughness

Characterise: Deposit thickness, surface

roughness, grain size, resistivity using surface

profiler, SEM,AFM,XRD and four point probe.

Parameters Varied: current density, temperature

of electrolyte, plating Time (deposit thickness of

gold), Duty Cycle

62

Finally, the Cr/Au seed layer used for the plating process is removed in their

corresponding etching solutions to get the desired metallic structure.

3.4.6.1 Gold film evaluation

Nucleation of plated gold layer is observed after plating of 10 seconds with other

parameters fixed as mentioned in section 3.4.6. Figures 3.30 depicts the SEM

micrographs during nucleation, the average grain size varies from 20-70nm. Figure 3.31

(a) shows the deposition rate of the electroplated gold for different current density values

using DC plating. The deposition rate is higher for higher current density, and hence the

thickness of the plated gold increases with current density for a fixed time (10min.).

Figure 3.31 (b) shows the RMS surface roughness and grain size for different current

densities. It has been observed from figure 3.31 (b) that the roughness and grain size

value increases with current density and deposition time [24, 25]. This is due to depletion

of gold molecules in the electroplating solution with time. Thus, subsequent addition of

the electrolyte during the electroplating process is necessary to maintain the pH value of

the plating solution constant and also to reduce the surface roughness.

In order to apply the gold plating to MEMS application it is important to evaluate the film

characteristics. An internal stress, grain size and a root-mean-square roughness with AFM

images of surface morphology versus plating current density for DC and versus duty

cycle for pulse plating is shown in figures 3.32 and 3.33. By measuring a curvature of the

gold plated silicon specimen, the internal stress is calculated in the gold film using

Stoney’s equation. As shown in the figure 3.31, internal stress of the gold film is below

70 MPa for pulse plating and 117MPa for DC plating, and it slightly decreases as the

plating current increases [25]. Figure 3.31 (b) shows low tensile stress values (35-85

MPa) that are practically independent of film thickness in the 0.4-2µm range. This is due

to the dominant contribution of the intrinsic tensile coalescence component. Increasing

the density of current from 2 to 6 mA cm-2

or the temperature of the bath from 40 to

70°C, results in higher tensile stress. The grain size in the electrodeposits varies with

current density as shown in figure 3.33(b) (from 20 to 70nm at 60°C with increasing

current density from 2 to 5 mA cm-2

).The surface morphology of gold film is measured

by AFM. At low current density plating, the plated surface looks rather sparse than at

high current density. The AFM micrographs of DC and pulse plating gold of 2µm

thickness are shown in figure 3.34. Figure 3.35 (a) shows the SEM micrographs of 2µm

plated gold surface topography at Si substrate and 3.35 (b-d) plated gold test structures.

63

Figure 3.30: SEM micrographs average grain size varies from 20-70nm.

Figure 3.31: (a) Thickness versus current density and (b) RMS surface roughness and

grain size versus current density of the DC gold electroplating process.

Figure 3.32: (a) Stress versus current density for DC Plating and (b) Stress versus duty

cycle for pulse plating of gold.

0 1 2 3 4 5 6 7 8

0

1

2

3

4

5

Th

ick

ne

ss

(u

m)

Current Density (mA/cm2)

Measured Thickness

Theoretical Thickness

2 3 4 5 6

20

40

60

80

Current Density (mA/cm2)

Gra

in S

ize

(n

m)

40

50

60

70

80

90

100

110

120

Ro

ug

hn

es

s (

nm

)

64

Figure 3.33: Grain size and roughness with surface morphology vs. Pulse duty cycle.

Figure 3.34: AFM micrographs of (a, b) DC plating 2D and 3D topography and (c, d)

after Pulse plating.

(a) (b)

(d) (c)

65

Figure 3.35: SEM Micrographs of electroplated gold structures.

X-Ray Diffraction (XRD) analysis

X-Ray diffraction is a principal method for determining structure of condensed matter on

the atomic scale, including the lattice parameter and microstructure of alloy films. The

wavelength range employed for X-Ray diffraction varies from 0.01 to 10 nm, which is of

the order of the distance between molecules and crystal lattice constants. By comparing x-

ray data with the well-established reference data sources, one can obtain a detailed

crystallography and compositional profile. A simple approach to x-ray diffraction from a

crystal is to treat it as interference of rays scattered by a multitude of equidistant lattice

planes. When the path difference between the scattered waves is an integer multiple times

the wavelength λ, there is a maximum in the intensity and constructive interference,

described by Bragg’s law:

nλ = 2d sinθ (3.3)

where λ is the incident ray wavelength, θ is the angle between incident ray and the

scattering lattice planes, d is the distance between two lattice planes, n is an integer, and

2dsinθ is the path difference between the incoming and the scattered ray. If the unit cell

structure of crystal is known, with Miller indices (h, k, l), the lattice parameter, is defined

by equation 3.4 from the distance between atomic planes d as below:

Cantilever

Bridge test structure

Plated Au surface topography at Si substrate

Guckel Ring

(a) (b)

(c) (d)

66

√ + + √ (3.4)

From the theory discussed above, the individual peaks of reflected x-ray intensity provide

information about elemental species and micro-structures of the samples studied. By

comparing the measured data to those of well-calibrated data, the chemical composition

and structure of the films can be profiled. In addition to the chemical information

obtained from the X-Ray diffraction spectra, we can also estimate the grain particle

diameters from the Debye-Scherrer relation.

The XRD data is used for grain size measurement for plated layer. According to Scherer’s

equation grain size is measured. The governing equations are as follows:

Crystalline Size

(3.5)

Microstrain

(3.6)

Estimation of number of crystallites

(3.7)

Where λ: X-ray wavelength (1.54178Å), B is the full width at half maximum, θ Bragg’s

angle, t film thickness and K constant average value (0.9). Figure 3.36(a) shows XRD

peak for 2μm thick plated gold film after deposition and 3.36 (b) shows after annealing

at 1500C. XRD peak are used to find out grain size using equation 3.5 and crystalline

orientation of Au deposit layer. Grain sizes are verified using AFM data. Finer grain

size and reduced roughness deposit using pulse power supply also measured using AFM

and XRD as shown in figure 3.33. The extracted parameters of electroplated gold for

minimum residual stress, fine grain size and roughness are finalized. The resultant

optimized plating recipes are used for fabricating single clamped cantilever structures as

well as RF MEMS switches.

Figure 3.36: (a) XRD patterns of plated Au film before and (b) After annealing at a

temperature of 1500C

67

Nano indentation of plated layer

The Nano indentation is used to measure Hardness (H), Young’s Modulus (E) and the

stiffness of plated and oxide layer on silicon substrate. The extracted Young’s modulus is

used in next chapter for extracting residual stress from test structures. Measured data of

indentation is depicted in table 3.13, two samples are used, one is silicon oxide of 1µm

and another is plated gold of 2µm thickness. Figure 3.37 shows the plated surface before

and after the indentation.

Table 3.13: Nano indentation measurement on silicon and gold surface

Wafer #AO3 (Silicon dioxide)

Er (GPa) Standard

Deviation

( GPa)

H (GPa) Standard

Deviation (

GPa)

Stiffness

(mN/nm)

Standard

Deviation

(mN/nm)

166.02 10.72 10.28 1.44 58.61 3.62

Wafer # FDCO1 (DC plating Au 2μm on Si)

120.58 13.6 1.17 0.15 125.26 15.45

Figure 3.37: Gold surface before and after Nano indentation.

Copper (Cu) plating experiments for via filling

The via filling of silicon cavity is required for packaging of RF MEMS devices. Cu

electroplating is used for via filling. Experiments are conducted to fix the process

parameter for Cu plating. Copper film is electroplated on gold seed layer for via filling

using different current densities varying from 10mA/cm2to 70mA/cm

2 at constant

temperature (40°C) [29]. The table 3.14 shows SEM micrographs of the Cu plated

samples with resistivity at different current densities (CD). Silicon cavity is created using

TMAH (Tetra Methyl Ammonium Hydroxide) etching. Figure 3.38 (a) shows SEM

(a) Before indentation (b) After indentation

Indentation points

68

micrographs of the silicon cavities before Cu plating and (b) single silicon cavity during

Cu electroplating.

Table 3.14: SEM micrographs of the Cu plated samples with resistivity [29]

Figure 3.38: SEM micrographs of (a) silicon cavities and (b) silicon cavity during Cu

filling [29].

69

3.4.7 Summary of electroplating experiments

1. DC plating optimum current density is 3.5mA/cm2 at temp. 60°C.

2. Roughness and grain size are increase with current density.

3. Residual stress of gold in DC plating at current densities (3.5 mA/cm2) was found

100-120MPa. Whereas, residual stress in pulse plating is reduced to 35-60MPa at

duty cycle 5-15%.

4. Grain size as well as surface roughness decreases 10 times (6 -10nm) using pulse

power supply.

5. Reduced grain size results bigger grain boundaries hence resistivity decrease.

6. Grain size measurements using XRD and AFM are closely matched.

7. Young’s modulus measured for 2µm plated gold using Nano indentation is

99.3GPa, whereas hardness is 1.17GPa.

8. Copper plating parameters for via filling applications are fixed.

3.5 Sacrificial Layer removal using Plasma ashing and CPD

In order to control the in-built stress in electroplated structures, it is desirable to realize

the metallic structure in two steps. In the first one bridge membrane and CPW are formed

with thickness up-to 1.5 μm. In the second step the suspended bridge can be reinforced

selectively to reduce the in-built stress. In this step, seventh lithography defines the mould

for electroplating using AZ 9260. At this stage the spacer (HiPR 6517) pedestal is

covered with the Cr/Au seed layer. Though the required bridge thickness is only 2 μm, a

resist thickness greater than 5 μm is required. After pattering mould in AZ 9260, the

electroplating of 2 μm thickness is deposit using above optimised process parameters.

After the wet removal of electroplating mould in acetone, Au/Cr seed layer is etched in

commercially available Au and Cr etchants. The etching of Au seed layer from undesired

areas also etches the electroplated Au surface from bridge and CPW. Accordingly the

electroplated Au thickness should be more than the desired bridge thickness. In present

case, 1.5 μm of bridge thickness is desired; whereas, electroplating has been done to

deposit 2 μm thick gold layer. After Au seed layer etching, remaining bridge thickness is

1.5 - 1.6 μm. This step is followed by Cr seed layer etching. The etchant used for this step

is highly selective and does not affect or etch other layers. Slight over-etching is desirable

to ensure removal of Cr seed layer from perforations.

Final ashing of HiPR hard baked positive photoresist, which is used as a sacrificial layer,

is carried out in oxygen plasma stripper (dry release) to prevent stiction of the suspended

70

membrane and Critical Point Drying (CPD) wet release. The final release step is the most

critical step in a switch fabrication process, step by step details of each releasing methods

are covered in the following section.

3.5.1 Dry Release method (Plasma Ashing)

Ashing is the process of dry removal of photoresist by generating mono-atomic reactive

species at high RF power. Oxygen and fluorine are the most common reactive species.

The reactive species combine with the photoresist to form ash which is removed using a

vacuum pump. The basic ashing reaction of oxygen-based plasma with photoresist

polymers is [30]:

+ i + + (3.8)

The initial experiments for removal of hard baked PR (HiPR6517) were carried out in

simple ashing equipment (laboratory made) typically used for removal of minor PR traces

before metallization. After a prolonged ashing cycle in oxygen plasma (approximately 7

hours) at 80 watts of RF power, the PR under the bridges are found intact whereas other

directly exposed areas are clean and free from PR residue. The residue remaining under

the metallic structures is attributed to the slow lateral etch rate of oxygen plasma. The PR

removal in a ‘Drytek megastrip 6 HF’ plasma wafer asher is also observed to be slow and

non-uniform, as the oxygen plasma (at 900watts) is inefficient in removing the hard crust

of the PR baked at 1800C. For the crust removal, a combination of oxygen and CF4 is

supplied to the plasma chamber in a ratio of 35:1.

Figure 3.39: (a) Ohmic switch before release (b) After 50 minute exposure to O2 + CF4

plasma [31].

(a)

Metallic bridge Sacrificial layer

HIPR 6517 Metallic bridge etching

(b)

71

Fluorine ions are reported [30] to react with the top surface to form CF3- which acts as a

catalyst for faster removal of hardened PR. However, longer exposure (40-50 minutes) to

fluorine plasma damages the Au structural layers as shown in figure 3.39. Figure 3.39 (a)

and (b) show the bridge of ohmic switch before ashing and after 50 minutes of ashing in

O2 + CF4 plasma. The crust removal process is optimized using combination of O2+ CF4

plasma exposure for 3 minutes followed by oxygen plasma for 90 minutes with 10

minutes on-off cycle. The on-off cycle is required to maintain the processing temperature

below a threshold level so that the effects like thin film delamination due to thermal

expansion coefficient mismatch, and unwanted dopant diffusion can be avoided. State of

art ashing system maintains low substrate temperature by circulating chilled water or

maintaining liquid nitrogen ambient around the plasma chamber. Figure 3.40 shows the

optical micrographs of PR residue (Au beam removed manually) during and after the

ashing.

Process parameters of dry release: In this section, the effects of reactive ion etching (RIE)

process parameters on the lateral etching rate of the sacrificial photoresist during the dry

releasing process are presented. The vertical etch rate of the photoresist varies between

230 and 350nm/min and is faster than the lateral etching rate 38-77nm/min. Therefore,

the total release time is mainly determined by the lateral etching of the sacrificial

photoresist layer. In the ashing process the chamber pressure is maintained at 400 mTorr

with 900watts of RF power as shown in table 3.16.

Figure 3.40: Optical micrographs after (a) 15 minutes (b) 45 minutes and (c) 90 minutes

of ashing [31].

(a)

Au layer

Clean surface inside

perforation

Remaining

Photoresist

under the

lifted bridge

Perforated Au metallic

bridge layer

(b)

Remaining

Spacer PR

beneath the

lifted bridge

during ashing

Perforated metallic

bridge layer

(c) Clean surface

after ashing of

spacer layer

Metallic bridge

structural layer

72

The vertical etch rate affects, after 15 minutes of ashing are visible in figure 3.40(a), the

PR directly exposed to plasma is removed whereas, spacer layer under the bridge remains

intact. The lateral etch rate affects, after 45 minutes of ashing are shown in figure 3.40(b).

Due to lower lateral etch rate the surface is fully clean only after 90 minutes as shown in

figure 3.40(c). SEM micrograph of successfully released RF MEMS ohmic switch using

optimized plasma ashing is shown in figure 3.41.

3.5.2 Wet release processes

3.5.2.1 Air Dry

Etching of photoresist (sacrificial layer) has been done in mild piranha solution

(H2SO4:H2O2::10:1) kept at 50-70°C. It is followed by DI water rinse for 3-4 times. The

wafer is then immersed in acetone, methanol, and isopropanol (IPA) for 5minutes each

respectively. IPA immersed wafer is kept at a small inclination in a petridish. Afterwards,

the wafer is dried in an oven at temperature of 120°C. Most of the structures are found

stuck to the wafer (typically the central part of the structure) and curled up at corners, as

shown in Figure 3.42 (a-b). The wet release method (drying in hot air) though cost

effective and simpler, can reproduce high-k (stiffness) structures (> 20Nm) only. The

method is found unsuitable for releasing the low stiffness metallic structures (0.05-

15N/m) without stiction and deformation [32, 33].

Figure 3.41: RF MEMS ohmic switch after plasma ashing.

Anchor

Anchor

RF

input

RF

output

Suspension

spring

Actuation

electrode

Suspended

Perforated bridge

73

Figure 3.42: (a-b) MEMS switches stucked to substrate and curled up at corners.

3.5.2.2 Critical Point Drying (CPD) release

As mentioned above the sacrificial layer is hard baked (1800C) positive photoresist (PR)

having a plastic like structure. The sacrificial PR layer removal is carried out using mild

piranha H2SO4 (10): H2O2 (1) solution while maintaining its temperature between 50-

700C. Wafers are held vertically in a beaker as shown in figure 3.43 and dipped for 2- 3

minutes in mild piranha to release the photoresist. After spacer layer etching samples are

rinsed with DI water. This rinsing step is crucial, because micro machined structures are

in hanging stage at this point of time. Samples are subsequently transferred into CPD

chamber filled with isopropanol (IPA). The next section gives the detail of working

principle and process of CPD [34].

Figure 3.43: Vertical held wafer in beaker with SEM of lifted structures.

(a) (b)

Au beam stick to

Si-surface Lifted beam

Lifted beam

Lifted Structure

Wafer dipping direction

74

Working principle of CPD

Various mechanisms (see figure 3.44) have been used to alleviate sticking in MEMS by

reducing the surface tension of the final rinse solution. For example, IPA, which has a

lower surface tension, is applied after the final water rinse to displace the water. A unique

way to reduce surface tension is critical point drying. This technique takes advantage of

the vanishing surface tension of a supercritical liquid. The method is explained in detail

below. This study indicated that by CPD technology gave superior and consistent results

compared to air dry (evaporation) or sublimation drying. The results from other methods

are mediocre and the by-products in sublimation drying were toxic and environmentally

hazardous. No such by-products were present in supercritical CO2 drying, but the setup

was rather complicated. The methods investigated by these researchers are also

summarized in a pressure temperature phase diagram in figure 3.45, which outlines the

various paths that are followed to minimize stiction [34-38]. In CPD process, the wafers

immersed in IPA are brought into a pressure vessel at room temperature. Liquid CO2 is

then used to replace the IPA during a rinse cycle. IPA is highly miscible with liquid CO2.

Next, the temperature of liquid CO2 is raised above its critical point. The pressure vessel

is then vented at constant temperature at T > Tcr and the CO2 escapes as a gas. A liquid to

solid interface is never formed during the process, hence surface tension is completely

suppressed and structure released successfully [37].

Figure 3.44: Pressure temperature phase diagram.

75

Experimental description of CPD equipment

Critical point drying mechanism is one of the most efficient and economical methods for

removal the sacrificial layers used in conjunction with wet etching methods. The basic

mechanism involves the use of wet chemistry to dissolve the sacrificial (photoresist,

metal or dielectric) layer and transfer of the process wafer to CPD equipment for drying

the liquids without any change in the volume. The extraction of IPA from micro

machined samples are performed in a CPD, rated at 2000psi maximum allowable working

pressure, which is depicted schematically in figure 3.45 along with chamber details. The

CO2 source gas is supplied by cylinders of technical grade CO2 which is delivered

through a regulator, to a pneumatic compressor. The compressor allows for pressurization

above the critical point for CO2. The gas flows through a 0.5 micron sintered stainless

steel filter, into a temperature-controlled extraction vessel. Temperature control is

provided by a constant temperature circulating bath which flows heat transfer fluid

through a water jacket surrounding the outer wall of the vessel. After leaving the

extraction vessel, the CO2 flows through a high pressure metering valve through which

the pressure is reduced. The metering valve is warmed with heat tape to prevent clogging

the valve with dry ice that might otherwise be formed due to Joule-Thomson cooling

upon expansion of the gas. The pressure is reduced into a temperature controlled 500 ml

vessel held at 0oC. Isopropanol (IPA) is not as soluble in gaseous CO2 as in CPD, so the

solvent condenses and can be trapped in the separator vessel. Finally, the gas is vented

out of the laboratory through a suction duct. System pressure is monitored and controlled

with a modular pressure controller with analog read-out which controls the pneumatic

compressor to maintain the desired system pressure. Over-pressure protection is provided

by a 2000 psi burst disc. All tubing is 1/4 inch O.D. (0.065” wall thickness) 316 stainless

steel tubing.

The extraction vessel is made of Teflon material. The vessel is supported horizontally. To

minimize excess vessel volume and to support the silicon wafer pieces being extracted;

one hard Teflon half-cylinders are machined to effectively fill the entire vessel volume.

At the intersection of the half-cylinders, a channel is machined to allow for CO2 flow over

the samples. On the bottom half-cylinder on which the wafer pieces rest, a deep trough is

milled to serve as a reservoir for the IPA. With the Teflon cylinder vessel inserts

installed, the large vessel is reduced to an effective volume of about 200 ml. This

arrangement forces CO2 to flow in more direct contact with the isopropanol being

extracted from the micro machined samples.

76

Figure 3.45: Critical point dryer (CPD) System.

Process flow in CPD: There are five mode of operation on CPD are as follows, the

schematic of the system is shown in figure 3.46. Cool: The process mode in which

coolant material is used to reduce the initial chamber temperature. Fill: During this mode

LCO2 is filled inside the chamber through fine nozzle in Teflon vessel. Purge: The flow

rate with which material IPA is replaced by LCO2. Always maintain fill rate greater than

purge rate. If purge rate greater than fill rate, the liquid level in the process chamber will

gradually drop below the level of sample. Therefore it is important to maintain grater fill

flow rate in the chamber than purge flow rate leaving the chamber. This will insure that

sample is always covering with liquid during purge. Heat: During this mode temperature

of the chamber increase along with pressure. This stage is continue until it reaches critical

point in temperature (310C) as well as pressure (1072psi) scale on measuring gauge.

Table 3.15 illustrate the change in temperature and pressure with time during critical

point. Bleed: a stage at which LCO2 and remaining IPA residual drain out after attaining

critical point. Vent: The stage at which pressure reduces to atmosphere and temperature

reduce to room temperature, sample is clean and dry.

Critical Point Dryer- CPD

Process

Chamber

Pressure

gauge

Temperature

gauge

CO2 Cylinder

Exhaust duct Filter

77

Figure 3.46: CPD schematic for process flow.

Table 3.15: Change in pressure and temperature during critical point

Critical Point passage Heat Pressure Reduction

Time

(Minute)

Pressure

(PSI)

Temperature

(ºC)

Pressure

(PSI)

Temperature

(ºC)

0 800 6 1460 34

2 1300 20 1180 36

4 1460 28 1140 37

6 1480 32 1060 39

8 1450 33 900 39

10 1460 34 710 38

12 500 38

14 380 39

Figure 3.47 (a)-(d) shows SEM micrographs of cantilever array, beams, switch and test

structure released using CPD. The abnormally high vertical deformation of structures is

attributed to the placement strategy (in vertical direction) of wafers while dissolving the

PR and rinsing. The vigorous chemical reaction and turbulence caused during rinsing lifts

the structures upwards if held vertically (figure 3.43).

Figure 3.47: (a-d) Micrographs of CPD released structures when wafer held vertically.

Cool Fill Purge Heat Bleed Vent

(c) (d)

(a) (b)

Cantilever array Beam array

MEMS switch curl bridge

MEMS Test

structure

curling due to vertical release

78

Improved CPD release method

The improvement in wet etching process is carried out by placing wafer in horizontal boat

during rinsing and etching. Placing the wafers in horizontal direction and gentle stirring

shows a drastic improvement. The method is found suitable for all types of micro

machined structures. The microstructures are an assortment of RF MEMS switches,

single pole double throw (SPDT), single pole four throw (SP4T), MEMS Test structure,

cantilever and bridge test structures [39]. Figure 3.48 (a,b) shows successfully released

RF MEMS ohmic switch and Au cantilever array extracted using CPD method which are

free standing with minimal deformation in case of longer cantilever.

3.5.3 Summary of releasing methods

CPD is demonstrated to release low stiffness metallic microstructures without stiction and

deformation. In contrast, approximately 90% of the air dried samples are stuck as shown

in figure 3.42. The air drying method resulted in surface stiction in the MEMS switches.

For some supercritically extracted samples, fabrication problems observed during etching

of vertically held wafers are resolved. Metallic structures are also released using modified

plasma ashing (CF4+O2) without any stiction problem. Some of the structures have

deformation due to rise in temperature of plasma asher. However intermittent plasma

ashing using a 10 minutes on-off cycle, to maintain temperature inside the asher

approximately at 800C, improves the planarity of structures. The structures released with

wet etching using CPD, are free from stiction and buckling as shown in figure 3.48. Table

3.16 summarizes the procedure and process parameters for all the releasing methods with

a comparison of their merits and demerits.

Table 3.16: Comparative summary of release methods

Release Methods Plasma Ashing Supercritical CPD drying Air Drying

Procedure

Parameters

O2

[100%]

CF4 [20%] + O2[80%]

(2-3min), O2[100%]

Mild piranha + DI water +

IPA

Mild piranha +

DI water + IPA

RF Power (watt) 80 900 N/A N/A

Chamber pressure (torr) 0.112 0.4 N/A N/A

Maximum temp. (0C) 60 80 0 N/A

Melting Temp. (0C) N/A N/A -56.4 [2] -97.5 [2]

Boiling Temp. (0C) N/A N/A -78.3 [2] 64.7 [2]

Surface tension (mN/m) N/A N/A 1.16 [2] 22.65

Process time (min.) 410 3+87 30 60

Advantage Compatible with IC processing Stiction free, No photoresist

residue, less process time

Simple

Disadvantage Complex recipes, residual stress,

time consuming

Wet chemistry control Mediocre results

79

Dry release using plasma ashing typically results in damage to metallic structures or

stress related deformation due to rise in temperature (>800C). Plasma ashing with10

minutes on-off cycle is found appropriate to release structures without deformation. CPD

being a low temperature (31.10C) process is more suitable for compliant structures

without any deformation due to residual stress.

Figure 3.48: (a, b) RF MEMS Ohmic switch and cantilever array released using CPD.

3.6 Conclusions

Fabrication process for suspended metallic structures without any deformation or

buckling is presented. The out of plan deformation in microstructures are attributed to

residual stress of metallic layer. The metallic layer is deposited using electroplating

process. Electroplating process is improved using pulse power supply and fine grained (5-

8 nm), reduced stress (30-70 MPa) and uniform thickness layer is deposited. Photoresists

(S 1813, HiPR 6517, AZ 4620 and 9260) profiles and recipes for various thicknesses (1-

10µm) are optimised. The suspended microstructures are released using plasma ashing

(dry release) and CPD (wet release) techniques. Both releasing process are optimised for

minimum structural deformation. The improved processes (electroplating and releasing

using CPD) results in minimum deformation of 4-5µm in the micro machined structures.

Free standing

moveable beam

without deformation

Contact bumps

(a) (b)

Suspension

spring

80

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