Chapter 18: Programmable DSPspeople.ece.umn.edu/users/parhi/SLIDES/chap18.pdf · Chap. 18 8 Main...
Transcript of Chapter 18: Programmable DSPspeople.ece.umn.edu/users/parhi/SLIDES/chap18.pdf · Chap. 18 8 Main...
Chap. 18 2
DSP ApplicationsDSP applications are often real timebut with a wide variety of sample rates
• High rates– Radar– Video
• Medium rates– Audio– Speech
• Low rates– Weather– Finance
Chap. 18 3
...with different demands on
• numeric representation
– float or fixed
– and nmber of bits
• Throughput/speed
• Power/energy dissipation
• Cost
Chap. 18 4
DSP features
D D Dx(n)
h0 h3h2h1
y(n)
Fast Multiply/Accumulate (MAC)• FIR• FFT• etc.
• Multiple Access Memories
• Specialized addressing modes
• Specialized execution control (loops)
• Specialized interfaces, e.g. AD/DA
Chap. 18 5
Addressing Modes• Implied addressing
P=X*Y; operation sets location• Immediate data
AX0=1234• Memory direct
R1=Mem[101]• Register direct
sub R1, R2• Register indirect
A0=A0+ *R5• Register indirect with increment/decrement
A0=A0+ *R5++A0=A0+ *R5--
Chap. 18 6
Standard DSP AlternativesPCs or Workstations
• Non-real time• low requirements
General purpose microprocessors• slower for DSP applications• might be one µproc. there anyway
Custom• perfomance• low cost at volume• High development cost
Chap. 18 7
Standard Processors vs. Special Purpose
Algorithm
SpecialPurpose
Standard Processor Processor Cores
Domain SpecificProcessors
etc.• Programmable• Low Design cost• Standard Interface• Good supply of tools
• High Calculation Capacity• Low Power• User defined Interface• Variable Wordlength• Low Price at Volume
Chap. 18 8
MainMEM
Conflicting req.• Throughput• Flexibility• Power Consumption• Time to market
ProcessorCore
ASIC
ASICMainMEM
Dist.MEM
Local bussesand
Distributedmemory
to decrease data transfers
MIPS intensivealgorithms indedicated HW
to increasethroughput and
save power
Flexibility byusing programmable
processor core
Architectural Partitioning
ProcessorCore
Chap. 18 9
Fixed point DSPMotorola DSP56000x
X0X1Y0Y1
ShifterALU
A (56)B (56)
Shifter/Limiter
2424
2424
24
24
24 24
56
56
5656
56
OperandRegisters
Accumulators
• Usually DSP has single cyclemultiplier, may be pipelined
• Double wordlength out
+ guard bits
• scaling
• Altenative is multwith reducedwordlength output,e.g. 24
Chap. 18 11
Memory Structures, Harvard
Addresss bus 2
Data bus 2
Processor Core
Memory A
Addresss bus 2
Data bus 2
Memory B
Original Harvard• one data• one program
Chap. 18 16
Processor ArchitecturesSIMD –
Single Instruction Multiple Data
Program
Processor Processor Processor Processor
Chap. 18 17
Processor ArchitecturesMIMD –
Multiple Instruction Multiple Data
Processor Processor Processor Processor
Program Program Program Program
Chap. 18 18
Processor ArchitecturesVLIW –
Very Long Instruction Words
FunctionalUnit
VLIW Instruction
Control Unit
FunctionalUnit
FunctionalUnit
FunctionalUnit
Chap. 18 19
Split Processors
Functional unitscan be split intosubmodules, e.g.for images (8bits)TI320C80,1 RISC4 x 32bit DSP whichcan be split into8bit modules
Chap. 18 21
Low Power MMACMultiplier Multiple Accumulator
V. Sundararajan and K.K. Parhi, "ANovel Multiply Multiple AccumulatorComponent for Low Power PDSPDesign", Proc. of 2000 IEEE Int. Conf.on Acoustics, Speech and SignalProcessing, Vol. 6, pp. 3247-3250,Istanbul, June 2000