Chapter 13 Output Stages and Power Amplifiers
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Transcript of Chapter 13 Output Stages and Power Amplifiers
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Chapter 13 Output Stages and Power Amplifiers
13.1 General Considerations 13.2 Emitter Follower as Power Amplifier 13.3 Push-Pull Stage 13.4 Improved Push-Pull Stage 13.5 Large-Signal Considerations 13.6 Short Circuit Protection 13.7 Heat Dissipation 13.8 Efficiency 13.9 Power Amplifier Classes
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Why Power Amplifiers?
Drive a load with high power.
Cell phone needs 1W of power at the antenna.
Audio system needs tens to hundreds Watts of power.
Ordinary Voltage/Current amplifiers are not equipped for such applications
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Chapter Outline
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Power Amplifier Characteristics
Experiences small load resistance.
Delivers large current levels.
Requires large voltage swings.
Draws a large amount of power from supply.
Dissipates a large amount of power, therefore gets “hot”.
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Power Amplifier Performance Metrics
Linearity
Power Efficiency
Voltage Rating
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Emitter Follower Large-Signal Behavior I
As Vin increases Vout also follows and Q1 provides more current.
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Emitter Follower Large-Signal Behavior II
However as Vin decreases, Vout also decreases, shutting off Q1
and resulting in a constant Vout.
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Example: Emitter Follower
11
ln
0.5 211
outin T out
L S
in out
VV V I V
R I
V V V mV
11 1
1 1
ln
0.01 390
Cin T C L
S
C in
IV V I I R
I
I I V mV
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Linearity of an Emitter Follower
As Vin decreases the output waveform will be clipped, introducing nonlinearity in I/O characteristics.
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Push-Pull Stage
As Vin increases, Q1 is on and pushes a current into RL.
As Vin decreases, Q2 is on and pulls a current out of RL.
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I/O Characteristics for Large Vin
For positive Vin, Q1 shifts the output down and for negative Vin, Q2 shifts the output up.
Vout=Vin-VBE1 for large +Vin
Vout=Vin+|VBE2| for large -Vin
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Overall I/O Characteristics of Push-Pull Stage
However, for small Vin, there is a dead zone (both Q1 and Q2 are off) in the I/O characteristic, resulting in gross nonlinearity.
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Small-Signal Gain of Push-Pull Stage
The push-pull stage exhibits a gain that tends to unity when either Q1 or Q2 is on.
When Vin is very small, the gain drops to zero.
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Sinusoidal Response of Push-Pull Stage
For large Vin, the output follows the input with a fixed DC offset, however as Vin becomes small the output drops to zero and causes “Crossover Distortion.”
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Improved Push-Pull Stage
With a battery of VB inserted between the bases of Q1 and Q2, the dead zone is eliminated.
VB=VBE1+|VBE2|
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Implementation of VB
Since VB=VBE1+|VBE2|, a natural choice would be two diodes in series.
I1 in figure (b) is used to bias the diodes and Q1.16CH 13 Output Stages and Power Amplifiers
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Example: Current Flow I
1 1 2in B BI I I I
Iin
If Vout=0 & β1=β2>>1=> IB1=IB2
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Example: Current Flow II
VD1≈VBE → Vout≈Vin
If I1=I2 & IB1≈IB2
→ Iin=0 when Vout=0
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Addition of CE Stage
A CE stage (Q4) is added to provide voltage gain from the input to the bases of Q1 and Q2.
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Bias Point Analysis
For bias point analysis, the circuit can be simplified to the one on the right, which resembles a current mirror.
The relationship of IC1 and IQ3 is shown above.
VA=0 Vout=0
IC1=[IS,Q1/IS,D1]×[IC3]
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Small-Signal Analysis
Assuming 2rD is small and (gm1+gm2)RL is much greater than 1, the circuit has a voltage gain shown above.
AV=-gm4(rπ1||r π2)(gm1+gm2)RL
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Output Resistance Analysis
3 4
1 2 1 2 1 2
||1
( )( || )O O
outm m m m
r rR
g g g g r r
If β is low, the second term of the output resistance will rise, which will be problematic when driving a small resistance.
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Example: Biasing
CE AV=5Output Stage AV=0.8
RL=8Ωβnpn= 2βpnp=100
IC1≈IC2
1 2
11 2
1 2
1 2
3 4
1
2
4
6.5
|| 133
195
m m
m m
C C
C C
g g
g g
I I mA
r r
I I A
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Problem of Base Current
195 µA of base current in Q1 can only support 19.5 mA of collector current, insufficient for high current operation (hundreds of mA).
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Modification of the PNP Emitter Follower
Instead of having a single PNP as the emitter-follower, it is now combined with an NPN (Q2), providing a lower output resistance.
2 3
1
1outm
Rg
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Example: Input Resistance
3
2 3
3 2 3
11
1
( 1)
Lin in in
Lm
in L
Ri v v
r Rg
r R r
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Additional Bias Current
I1 is added to the base of Q2 to provide an additional bias current to Q3 so the capacitance at the base of Q2 can be charged/discharged quickly.
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Example: Minimum Vin
Min Vin≈0Vout≈|VEB2|
Min Vin≈VBE2
Vout≈|VEB3|+VBE2
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HiFi Design
Using negative feedback, linearity is improved, providing higher fidelity.
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Short-Circuit Protection
Qs and r are used to “steal” some base current away from Q1 when the output is accidentally shorted to ground, preventing short-circuit damage.
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Emitter Follower Power Rating
1 2P
av CCV
P I V
Maximum power dissipated across Q1 occurs in the absence of a signal.
,max 1av CCP TV
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Example: Power Dissipation
1 10
1 1
1sin
T
I p EE
I EE
P I V t V dtT
P I V
Avg Power Dissipated in I1
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Push-Pull Stage Power Rating
4CCP P
avL
VV VP
R
2
,max 2CC
avL
VP
R
Maximum power occurs between Vp=0 and 4Vcc/π.
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Example: Push-Pull Pav
4CCP P
avL
VV VP
R
If Vp = 4VCC/π → Pav=0
Impossible since Vp cannot goabove supply (VCC)
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Heat Sink
Heat sink, provides large surface area to dissipate heat from the chip.
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Thermal Runaway Mitigation
1 21 2
, 1 , 2 , 1 , 2
C CD D
S D S D S Q S Q
I II I
I I I I
Using diode biasing prevents thermal runaway since the currents in Q1 and Q2 will track those of D1 and D2 as long as theie Is’s track with temperature.
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Efficiency
out
out ckt
P
P P
Efficiency is defined as the average power delivered to the load divided by the power drawn from the supply
Emitter Follower Push-Pull Stage
2
21
2
2 2 2
4
P LEF
P L CC P
PEF
CC
V R
V R I V V
V
V
I1=VP/RL
2
21
2
2 2 / 4
4
P LPP
P L CC P
PP P CC
V R
V R I V V
V V
I1=VP/RL
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Example: Efficiency
Emitter FollowerVP=VCC/2
1
15
Push-PullI1=(VP/RL)/β
1
4P
CC P
V
V V
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Power Amplifier Classes
Class A: High linearity, low efficiency
Class B: High efficiency, low linearity
Class AB: Compromise between Class A and B
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Chapter 14 Analog Filters
14.1 General Considerations 14.2 First-Order Filters 14.3 Second-Order Filters 14.4 Active Filters 14.5 Approximation of Filter Response
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Outline of the Chapter
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Why We Need Filters
In order to eliminate the unwanted interference that accompanies a signal, a filter is needed.
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Filter Characteristics
Ideally, a filter needs to have a flat pass band and a sharp roll-off in its transition band.
Realistically, it has a rippling pass/stop band and a transition band.
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Example: Filter I
Design goal: Signal to Interference ratio of 15 dB
Solution: A filter with stop band of 40 dB
Given: Adjacent channel Interference is 25 dB above the signal
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Example: Filter II
Given: Adjacent channel Interference is 40 dB above the signal
Design goal: Signal to Interference ratio of 20 dB
Solution: A filter with stop band of 60 dB at 60 Hz
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Example: Filter III
A bandpass filter around 1.5 GHz is needed to reject the adjacent Cellular and PCS signals.
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Classification of Filters I
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Classification of Filters II
Continuous-time Discrete-time
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Classification of Filters III
Passive Active
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Summary of Filter Classifications
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Filter Transfer Function
Filter a) has a transfer function with -20dB/dec roll-off Filter b) has a transfer function with -40dB/dec roll-off, better
selectivity.
A B
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General Transfer Function
Pn =n’th pole
Zm=m’th zero
1 2
1 2
( ) m
m
s Z s Z s ZH s
s P s P s P
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Pole-Zero Diagram
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Position of the Poles
Poles on the RHPUnstable (no good)
Poles on the jω axisOscillatory(no good)
Poles on the LHPDecaying
(good)
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Imaginary Zero
Imaginary zero is used to create a null at certain frequency.
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Sensitivity
PC
dP dCS
P C
Sensitivity measures the variation of a filter parameter due to variation of a filter component.
P=Parameter
C=Component
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Example: Sensitivity
1
1
/1
0
1
1
1
0
0
12
11
0
110
RS
R
dRd
CRdR
d
CR
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First-Order Filters
1
1
( )s z
H ss p
First-order filters are represented by the transfer function shown above.
Low/high pass filters can be realized by changing the relative positions of poles and zeros.
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Example: First-Order Filter I
R2C2 < R1C1R2C2 > R1C1
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Example: First-Order Filter II
R2C2 < R1C1R2C2 > R1C1 60CH 14 Analog Filters
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Second-Order Filters
2
2 2( )
nn
s sH s
s sQ
1,2 2
11
2 4n
np jQ Q
Second-order filters are characterized by the “biquadratic” equation with two complex poles shown above.
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Second-Order Low-Pass Filter
22
222 2
( )n
n
H j
Q
α=β=0
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Example: Second-Order LPF
2
2
3
/ 1 1/(4 ) 3
1 1/(2 )n n
Q
Q Q
Q
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Second-Order High-Pass Filter
2
2 2( )
nn
sH s
s sQ
β=γ=0
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Second-Order Band-Pass Filter
2 2( )
nn
sH s
s sQ
α=γ=0
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Example: -3-dB Bandwidth
1 12 2
1 1 1 1 1
R L sZ
R L C s L s R
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LC Realization of Second-Order Filters
11 2
1 1 1
L sZ
L C s
An LC tank realizes a second-order band-pass filter with two imaginary poles at ±j/(L1C1)1/2 , which implies infinite impedance at ω=1/(L1C1)1/2.
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Example: Tank
ω=0, the inductor acts as a short. ω=∞, the capacitor acts as a short.
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RLC Realization of Second-Order Filters
1 12 2
1 1 1 1 1
R L sZ
R L C s L s R
11,2 2
1 1 1 11 1
1 11
2 4
Lp j
R C R CL C
With a resistor, the poles are no longer pure imaginary which implies there will be no infinite impedance at any ω.
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Voltage Divider Using General Impedances
( )out P
in S P
V Zs
V Z Z
Low-pass High-pass Band-pass
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Low-pass Filter Implementation with Voltage Divider
12
1 1 1 1 1
out
in
V Rs
V R C L s L s R
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Example: Frequency Peaking
12
1 1 1 1 1
out
in
V Rs
V R C L s L s R
1
2Q Peaking exists
Voltage gain larger than unity
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Low Pass Circuit Comparison
The circuit on the left has a sharper roll-off at high frequency than the circuit on the right.
Good Bad
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High-pass Filter Implementation with Voltage Divider
2
1 1 12
1 1 1 1 1
out
in
V L C R ss
V R C L s L s R
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Band-pass Filter Implementation with Voltage Divider
2
12
1 1 1 1 1
out
in
V L ss
V R C L s L s R
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Sallen and Key (SK) Filter: Low-Pass
2
1 2 1 2 1 2 2
1
1out
in
Vs
V R R C C s R R C s
11 2
1 2 2
1 CQ R R
R R C
1 2 1 2
1n
R R C C
Sallen and Key filters are examples of active filters. This particular filter implements a low-pass, second-order transfer function.
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Sallen and Key (SK) Filter: Band-pass
3
4
2 31 2 1 2 1 2 2 2 1 1
4
1
1
out
in
R
V Rs
V RR R C C s R C R C R C s
R
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Example: SK Filter Poles
R1=R2
C1=C2
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Sensitivity in Band-Pass SK Filter
1 2 1 2
1
2n n n n
R R C CS S S S
1 2
2 2
1 1
1
2Q QR R
R CS S Q
R C
1 2
2 2 1 2
1 1 2 1
1
2Q QC C
R C R CS S Q
R C R C
1 1
2 2
QK
R CS QK
R C K=1+R3/R4
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Example: SK Filter Sensitivity I
1 2
1 2
1 1
2 31 2
2 3
3
Q QR R
Q QC C
QK
S SK
S SK
KS
K
1 2
1 2
R R R
C C C
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Example: SK Filter Sensitivity II
2
2
Q
K
1
1
2 2
1 1
1 1
2 2
31
4
1 5
8 4
8
1.5
QR
QC
QK
R CS
R C
R CS
R C
S
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Integrator-Based Biquads
2
2 2
out
ninn
V ss
V s sQ
2
2
1.n n
out in out outV s V s V s V sQ s s
It is possible to use integrators to implement biquadratic transfer functions.
The block-diagram above illustrates how. 82CH 14 Analog Filters
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KHN Biquads
2
2
1.n n
out in out outV s V s V s V sQ s s
5 6
4 5 3
1R R
R R R
4
4 5 1 1
1.n R
Q R R R C
2 6
3 1 2 1 2
1.n
R
R R R C C
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Versatility of KHN Biquads
2
2 2
out
ninn
V ss
V s sQ
High-Pass
2
2 2 1 1
1.X
ninn
V ss
V R C ss sQ
Band-Pass
2
22 2 1 2 1 2
1.Y
ninn
V ss
V R R C C ss sQ
Low-Pass
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Sensitivity in KHN Biquads
1 2 1 2 4 5 3 6, , , , , , , 0.5n
R R C C R R R RS 1 2 1 2, , , 0.5Q
R R C CS
3 6
3 6 2 2,
5 3 6 1 1
4
2 1
QR R
R R R CQS
R R R R CR
4 5
5,
4 5
1QR R
RS
R R
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Tow-Thomas Biquad
3 42
1 2 3 4 1 2 2 4 2 3
1.Y
in
R RV
V R R R R C C s R R C s R
2 3 4 2
21 2 3 4 1 2 2 4 2 3
.out
in
V R R R C s
V R R R R C C s R R C s R
Band-Pass Low-Pass
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Example: Tow-Thomas Biquad
2 4 1 2
1n
R R C C
Adjusted by R2 or R4
2 4 2
3 1
1 R R CQ
R C
Adjusted by R3
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Differential Tow-Thomas Biquads
By using differential integrators, the inverting stage is eliminated.
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Simulated Inductor (SI)
1 35
2 4in
Z ZZ Z
Z Z
It is possible to simulate the behavior of an inductor by using active circuits in feedback with properly chosen passive elements.
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Example: Simulated Inductor I
By proper choices of Z1-Z4, Zin has become an impedance that increases with frequency, simulating inductive effect.
2in X YZ R R Cs
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Example: Simulated Inductor II
1 2 3
4
2
1Y
in X Y
Z Z Z R
ZCs
Z R R Cs
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High-Pass Filter with SI
With the inductor simulated at the output, the transfer function resembles a second-order high-pass filter.
2
12
1 1 1 1 1
out
in
V L ss
V R C L s L s R
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Example: High-Pass Filter with SI
4 1 Yout
X
RV V
R
Node 4 is also an output node
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Low-Pass Filter with Super Capacitor
1
1inX
ZCs R Cs
2 21 1 1
1
1out in
in in X
V Z
V Z R R R C s R Cs
Low-Pass
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Example: Poor Low Pass Filter
4 2out XV V R Cs
Node 4 is no longer a scaled version of the Vout. Therefore the output can only be sensed at node 1, suffering from a high impedance.
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Frequency Response Template
With all the specifications on pass/stop band ripples and transition band slope, one can create a filter template that will lend itself to transfer function approximation.
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Butterworth Response
2
0
1( )
1n
H j
ω-3dB=ω0, for all n
The Butterworth response completely avoids ripples in the pass/stop bands at the expense of the transition band slope.
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Poles of the Butterworth Response
02 1
exp exp , 1,2, ,2 2kj k
p j k nn
2nd-Order nth-Order98CH 14 Analog Filters
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Example: Butterworth Order
The Butterworth order of three is needed to satisfy the filter response on the left.
n=3
2
2
1
64.2n
f
f
2 12f f
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Example: Butterworth Response
12 2
2 *(1.45 )* cos sin3 3
p MHz j
32 2
2 *(1.45 )* cos sin3 3
p MHz j
2 2 *(1.45 )p MHz
RC section
2nd-Order SK
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Chebyshev Response
2 2
0
1
1 n
H j
C
The Chebyshev response provides an “equiripple” pass/stop band response.
Chebyshev Polynomial
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Chebyshev Polynomial
Chebyshev Polynomial for n=1,2,3
Resulting Transfer function forn=2,3
10
0 0
cos cos ,nC n
10
0
cosh cosh ,n
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Example: Chebyshev Attenuation
23
2
0 0
1
1 0.329 4 3
H j
ω0=2π X (2MHz)
A third-order Chebyshev response provides an attenuation of -18.7 dB a 2MHz.
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Example: Chebyshev Order
Passband Ripple: 1 dB Bandwidth: 5 MHz Attenuation at 10 MHz: 30 dB What’s the order?
2 2 1
10.0316
1 0.509 cosh cosh 2n
n>3.66
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Example: Chebyshev Response
1 10 0
2 1 2 11 1 1 1sin sinh sinh cos cosh sinh
2 2k
k kp j
n n n n
K=1,2,3,4
2,3 0 00.337 0.407p j
SK2
1,4 0 00.140 0.983p j
SK1
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Chapter 15 Digital CMOS Circuits
15.1 General Considerations 15.2 CMOS Inverter 15.3 CMOS NOR and NAND Gates
106
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Chapter Outline
107CH 15 Digital CMOS Circuits
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Inverter Characteristic
_
X A
An inverter outputs a logical “1” when the input is a logical “0” and vice versa.
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NMOS Inverter
The CS stage resembles a voltage divider between RD and Ron1 when M1 is in deep triode region. It produces VDD when M1 is off.
11
( )on
n ox DD TH
RW
C V VL
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Transition Region Gain
Ideally, the VTC of an inverter has infinite transition region gain. However, practically the gain is finite.
Infinite Transition Region Gain Finite Transition Region Gain
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Example: Transition Gain
Transition Region: 50 mV
Supply voltage: 1.8V
1.836
0.05vA V0 – V2: Transition Region
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Logical Level Degradation
Since real power buses have losses, the power supply levels at two different locations will be different. This will result in logical level degradation.
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Example: Logic Level Degradation
5 25 125V A m mV
Supply A=1.8VSupply B=1.675V
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The Effects of Level Degradation and Finite Gain
In conjunction with finite transition gain, logical level degradation in succeeding gates will reduce the output swings of gates.
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Small-Signal Gain Variation of NMOS Inverter
As it can be seen, the small-signal gain is the largest in the transition region.
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Above Unity Small-Signal Gain
The magnitude of the small-signal gain in the transition region can be above 1.
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Noise Margin
Noise margin is the amount of input logic level degradation that a gate can handle before the small-signal gain becomes -1.
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Example: NMOS Inverter Noise Margin
212
2out DD n ox D in TH out outW
V V C R V V V VL
Vin=VIH1
22
in THout
n ox D
V VV
WC R
L
1L IL TH
n ox D
NM V VW
C RL
1:
H DD IHNM V V 2: 118CH 15 Digital CMOS Circuits
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Example: Minimum Vout
To guarantee an output low level that is below 0.05VDD, RD is chosen above.
19
D
n ox DD TH
RW
C V VL
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Dynamic Behavior of NMOS Inverter Gates
Since digital circuits operate with large signals and experience nonlinearity, the concept of transfer function is no longer meaningful. Therefore, we must resort to time-domain analysis to evaluate the speed of a gate.
It usually takes 3 time constants for the output to transition.120CH 15 Digital CMOS Circuits
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Rise/Fall Time and Delay
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Example: Time Constant
219
D Xn DD TH
LR C
V V
Assuming a 5% degradation in output low level, the time constant at node X is shown above.
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Example: Interconnect Capacitance
Wire Capacitance per Mircon: 50x10-18 F/µm
Total Interconnect Capacitance: 15000X50x10-18 =750 fF
Equivalent to 640 MOS FETs with W=0.5µm, L=0.18µm, Cox =13.5fF/µm2
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Power-Delay Product
2DD XPDP V C
The power delay product of an NMOS Inverter can be loosely thought of as the amount of energy the gate uses in each switching event.
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Example: Power-Delay Product
23 DD oxPDP V WLC
3
3PLH D X
DD DD D X
T R C
PDP I V R C
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Drawbacks of the NMOS Inverter
Because of constant RD, NMOS inverter consumes static power even when there is no switching.
RD presents a tradeoff between speed and power dissipation.
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Improved Inverter Topology
A better alternative would probably have been an “intelligent” pullup device that turns on when M1 is off and vice versa.
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Improved Falltime
This improved inverter topology decreases falltime since all of the current from M1 is available to discharge the capacitor.
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CMOS Inverter
A circuit realization of this improved inverter topology is the CMOS inverter shown above.
The NMOS/PMOS pair complement each other to produce the desired effects.
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CMOS Inverter Small-Signal Model
1 2 1 2||outm m O O
in
vg g r r
v
When both M1 and M2 are in saturation, the small-signal gain is shown above.
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Switching Threshold
The switching threshold (VinT) or the “trip point” of the inverter is when Vout equals Vin.
If VinT =Vdd/2, then W2/W1=µn/µp
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CMOS Inverter VTC
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Example: VTC
As the PMOS device is made stronger, the VTC is shifted to the right.
W2
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Noise Margins
NML =VIL
NMH =Vdd-VIH
1 2 1 22
11 3
dd TH TH dd TH THIL
a V V V V aV VV
aa a
1 2 1 22
11 1 3
dd TH TH dd TH THIH
a V V V V aV VV
aa a
1
2
n
p
WL
aWL
VIL is the low-level input voltage at which (δVout/ δVin)=-1
VIH is the high-level input voltage at which (δVout/ δVin)=-1
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VIL of a Symmetric VTC
1 12 2 3 1
1 3
DD TH DD THIL
a V V a V a VV
a a
Symmetric VTC: a=1
13 1
8 4IL DD THV V V
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Noise Margins of an Ideal Symmetric VTC
, , 2DD
H ideal L idealV
NM NM
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Floating Output
1
2
/ 2
/ 2TH DD
TH DD
V V
V V
When Vin=VDD/2, M2 and M1 will both be off and the output floats.
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Charging Dynamics of CMOS Inverter
As Vout is initially charged high, the charging is linear since M2 is in saturation. However, as M2 enters triode region the charge rate becomes sublinear.
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Charging Current Variation with Time
The current of M2 is initially constant as M2 is in saturation. However as M2 enters triode, its current decreases.
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Size Variation Effect to Output Transition
As the PMOS size is increased, the output exhibits a faster transition.
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Discharging Dynamics of CMOS Inverter
Similar to the charging dynamics, the discharge is linear when M1 is in saturation and becomes sublinear as M1 enters triode region.
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Rise/Fall Time Delay
2 2
22
2
2ln 3 4THL TH
PLHDD TH DD
p ox DD TH
VC VT
W V V VC V VL
Rise Time Delay
1 1
11
1
2ln 3 4THL TH
PHLDD TH DD
n ox DD TH
VC VT
W V V VC V V
L
Fall Time Delay
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Example: Averaged Rise Time Delay
222
1
4AVG p ox DD THW
I C V VL
2
22
22
/ 2. DD DD THL
PLHDD TH
p ox DD TH
V V VCT
W V VC V VL
2 24
3PLH on LT R C
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Low Threshold Improves Speed
The sum of the 1st and 2nd terms of the bracket is the smallest when VTH is the smallest, hence low VTH improves speed.
2 /1 2 /1/
2 /1/ 2 /1
2 /1
2ln 3 4TH THL
PLH HLDD TH DD
p n ox DD TH
V VCT
W V V VC V VL
1st Term
2nd Term
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Example: Increased Fall Time Due to Manufacturing Error
'1 1 1'
11 1
1|| 2on on ON
n ox DD TH
R R RW W
C V VL L
Since pull-down resistance is doubled, the fall time is also doubled.
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Power Dissipation of the CMOS Inverter
2_
1
2Dissipation PMOS L DD inP C V f
2_
1
2Dissipation NMOS L DD inP C V f
2supply L DD inP C V f
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Example: Energy Calculation
2
2
2
1
21
2
stored L DD
dissipated L DD
drawn L DD
E C V
E C V
E C V
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Power Delay Product
2 21 1
11
1
2ln 3 4THin L DD TH
DD TH DDn ox DD TH
Vf C V VPDP
W V V VC V VL
Ron1=Ron2
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Example: PDP
2 2
4 1
3
7.25
on
n ox DD
ox in DD
n
RW
C VL
WL C f VPDP
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Crowbar Current
When Vin is between VTH1 and VDD-|VTH2|, both M1 and M2 are on and there will be a current flowing from supply to ground.
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NMOS Section of NOR
When either A or B is high or if both A and B are high, the output will be low. Transistors operate as pull-down devices.
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Example: Poor NOR
The above circuit fails to act as a NOR because when A is high and B is low, both M4 and M1 are on and produces an ill-defined low.
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PMOS Section of NOR
When both A and B are low, the output is high. Transistors operate as pull-up devices.
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CMOS NOR
Combing the NMOS and PMOS NOR sections, we have the CMOS NOR.
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Example: Three-Input NOR
'outV A B C
Equal Rise & Fall (µn≈2µp)
W1=W2=W3=WW4=W5=W6=6W
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Drawback of CMOS NOR
Due to low PMOS mobility, series combination of M3 and M4 suffers from a high resistance, producing a long delay.
The widths of the PMOS transistors can be increased to counter the high resistance, however this would load the preceding stage and the overall delay of the system may not improve.
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NMOS NAND Section
When both A and B are high, the output is low.
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PMOS NOR Section
When either A or B is low or if both A and B are low, the output is high.
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CMOS NAND
Just like the CMOS NOR, the CMOS NAND can be implemented by combining its respective NMOS and PMOS sections, however it has better performance because its PMOS transistors are not in series.
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Example: Three-Input NAND
'outV ABC
Equal Rise & Fall (µn≈2µp)
W1=W2=W3=3WW4=W5=W6=2W
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NMOS and PMOS Duality
In the CMOS philosophy, the PMOS section can be obtained from the NMOS section by converting series combinations to the parallel combinations and vice versa.
C is in “parallel” with the “series” combination of A and B
C is in “series” with the “parallel” combination of A and B
161CH 15 Digital CMOS Circuits