Chapter 12 : Field – Effect Transistors 12-1 NMOS and PMOS transistors 12-2 Load-line analysis of...
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Transcript of Chapter 12 : Field – Effect Transistors 12-1 NMOS and PMOS transistors 12-2 Load-line analysis of...
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Chapter 12 : Field – Effect Transistors
12-1 NMOS and PMOS transistors12-2 Load-line analysis of a simple NMOS
amplifier12-3 Small –signal equivalent circuits12-4 Common source amplifiers12-5 Source followers12-6 CMOS logic gates
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MOSFET Transsistors
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N-channel enhancement MOSFET
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4-1. Device Structure . Fig. 4-1 . Physical structure of the enhancement- type NMOS transistor
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Fig. 4-2 . The enhancement-type NMOS transistor with applied voltage
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Applying a small vDS . Fig. 4-3 An NMOS transistor with vGS > vt and
s small vDS
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Operation in the cut - off
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Fig. 4-4 . The iD –vDS characteristics of the MOSFET
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With increasing vDS . Fig. 4-5 The enhancement NMOS transistor as vDS is increased
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Fig. 4-6 The drain current iD vs vDS
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Fig. 4-11 The iD – vDS characteristics of an n-channel enhancement type MOSFET
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Fig. 4-12 The iD-vDS characteristic for an enhancement –type NMOS transistor in saturation
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Fig. 4-7 A tapered shape caused by increasing vDS
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Fig. 4-10 Circuit symbol for the n-channel enhancement –type MOSFET
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The p-Channel MOSFET
• vGS , vDS and vt are negative
• iD enters from the source terminal and leaves through the drain terminal .
• NMOS operates faster and at lower power than PMOS .
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Fig. 4-13 Large signal equivalent circuit of an n-channel MOSFET
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Fig. 4-17 Large signal equivalent circuit of the n-channel MOSFET in saturation with r0
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Fig. 4-37 Small signal models for the MOSFET
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Fig. 4-37 (b) with the channel length modulation
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Fig. 4-40 T model of the MOSFET with r0
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Chapter 12 : Field – Effect Transistors
12-1 NMOS and PMOS transistors12-2 Load-line analysis of a simple NMOS
amplifier12-3 Small –signal equivalent circuits12-4 Common source amplifiers12-5 Source followers12-6 CMOS logic gates
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Common- source amplifiers
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Common- source amplifiers
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10.3 CMOS Logic Gate Circuits10.3.1 Basic structure
Fig. 10.8 Representation of a three- input CMOS logic gate