Chapter 10 The Stack. 10-2 Stack: An Abstract Data Type An important abstraction that you will...

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Chapter 10 The Stack

Transcript of Chapter 10 The Stack. 10-2 Stack: An Abstract Data Type An important abstraction that you will...

Page 1: Chapter 10 The Stack. 10-2 Stack: An Abstract Data Type An important abstraction that you will encounter in many applications. We will describe two uses:

Chapter 10The Stack

Page 2: Chapter 10 The Stack. 10-2 Stack: An Abstract Data Type An important abstraction that you will encounter in many applications. We will describe two uses:

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Stack: An Abstract Data TypeAn important abstraction that you will encounterin many applications.

We will describe two uses:

Interrupt-Driven I/O• The rest of the story…

Evaluating arithmetic expressions• Store intermediate results on stack instead of in registers

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StacksA LIFO (last-in first-out) storage structure.

• The first thing you put in is the last thing you take out.• The last thing you put in is the first thing you take out.

Many different implementations satisfy the above definition.

Two main operations:PUSH: add an item to the stack

POP: remove an item from the stack

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A Physical StackCoin rest in the arm of an automobile

First quarter out is the last quarter in.

1995 1996199819821995

199819821995

Initial State AfterOne Push

After Three More Pushes

AfterOne Pop

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A Hardware Implementation

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YesEmpty:

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Initial State AfterOne Push

After Three More Pushes

AfterTwo Pops

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An LC-3 Software ImplementationData items don't move in memory, just our idea about where the TOP of the stack is.

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Initial State AfterOne Push

After Three More Pushes

AfterTwo Pops

x3000 x2FFF x2FFC x2FFER6 R6 R6 R6

R6 is used to hold the Top of Stack (TOS) pointer.

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Basic Push and Pop CodeFor our implementation, stack grows downward(when item added, TOS moves closer to 0)

Push

ADD R6, R6, #-1 ; decrement stack ptr STR R0, R6, #0 ; store data (R0)

Pop

LDR R0, R6, #0 ; load data from TOS ADD R6, R6, #1 ; increment stack ptr

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Pop with Underflow DetectionIf we try to pop too many items off the stack,an underflow condition occurs.

• Check for underflow by checking TOS before removing data.• Return status code in R5 (0 for success, 1 for underflow)

POP LD R1, EMPTY ; Value of TOS when stack EMPTY ADD R2, R6, R1 ; Compare stack pointer BRz FAIL ; with x3000 LDR R0, R6, #0 ; Load the data ADD R6, R6, #1 ; Increment stack pointer AND R5, R5, #0 ; SUCCESS: R5 = 0 RETFAIL AND R5, R5, #0 ; FAIL: R5 = 1 ADD R5, R5, #1 RETEMPTY .FILL x-3000

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Push with Overflow DetectionIf we try to push too many items onto the stack,an overflow condition occurs.

• Check for overflow by checking TOS before adding data.• Return status code in R5 (0 for success, 1 for overflow)

PUSH LD R1, FULL ; Value of TOS when stack FULL ADD R2, R6, R1 ; Compare stack pointer BRz FAIL ; with x2000 ADD R6, R6, #-1 ; decrement stack pointer STR R0, R6, #0 ; store the data AND R5, R5, #0 ; SUCCESS: R5 = 0 RETFAIL AND R5, R5, #0 ; FAIL: R5 = 1 ADD R5, R5, #1 RETFULL .FILL x-2000

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Interrupt Service Routine (ISR)Interrupts were introduced in Chapter 8.

1. External device signals need to be serviced.

2. Processor saves state and starts service routine.

3. When finished, processor restores state and resumes program.

Chapter 8 didn’t explain how (2) and (3) occur,because it involves a stack.

Now, we’re ready…

Interrupt is an unscripted subroutine call,

triggered by an external event.

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Processor StateWhat is needed to completely capture thestate of a running process?

Processor Status Register• Privilege [15], Priority Level [10:8], Condition Codes [2:0]

Program Counter• Pointer to next instruction to be executed.

Registers• All temporary state of the process that’s not stored in memory.

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Save State. How? Where? Who?Processor Status Register

• It’s not addressable (no instruction to read it).

Program Counter • We have no idea when interrupt might occur.

• Can the ISR save the PC?

Registers• Can the ISR save registers?

So PSR and PC must be saved by HW during an interrupt• But where?

– In a special location in memory? Well, sort of, but…

• Interrupts may be nested – an ISR can be interrupted!

Solution: Use a stack!• Location of stack “hard-wired” – memory set aside for this.

• Push state to save, pop to restore.

• Performed automatically when ISR called.

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Supervisor StackA special region of memory used as the stackfor interrupt service routines.

• Manually set this for the LC-3, using R6 as stack pointer

Use R6 as stack pointer.• So that our PUSH/POP routines (from before) still work.

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Invoking the Service Routine – The Details1. Push PSR and PC to Supervisor Stack.

2. Set PSR[15] = 0 (supervisor (aka privilege) mode).

3. Set PSR[10:8] = priority of interrupt being serviced.

4. Set PSR[2:0] = 0.

5. Set MAR = x01vv, where vv = 8-bit interrupt vectorprovided by interrupting device (e.g., keyboard = x80).

6. Load memory location (M[x01vv]) into MDR.

7. Set PC = MDR; now first instruction of ISR will be fetched.

Note: This all happens (automatically) between the STORE RESULT of the last user instruction andthe FETCH of the first ISR instruction.•Cannot happen in the middle of an instruction

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Returning from InterruptSpecial instruction – RTI – that restores state.

1. Pop PC from supervisor stack. (PC = M[R6]; R6 = R6 + 1)

2. Pop PSR from supervisor stack. (PSR = M[R6]; R6 = R6 + 1)

(Both done automatically)

RTI is a privileged instruction.• Can only be executed in Supervisor/Privilege Mode.• If executed in User Mode, causes an exception.

(More about that later.)

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Example (1)

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x3006PC

Program A

ADDx3006

Executing ADD at location x3006 when Device B interrupts.

R6

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Example (2)

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PSR for A

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x6200PC

R6

Program A

ADDx3006

Push PSR and PC onto stack, then transfer toDevice B service routine (at x6200).

x6200

ISR forDevice B

x6210 RTI

ANDx6202

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Example (3)

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PSR for A

x6203

PSR for B

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Program A

ADDx3006

x6200

ISR forDevice B

ANDx6202

ISR forDevice C

Executing AND at x6202 when Device C interrupts.Push PSR and PC onto stack, then transfer toDevice C service routine (at x6300).

x6300

x6315 RTI

x6210 RTI

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Example (4)

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PSR for A

x6203

PSR for B

x6203PC

R6

Program A

ADDx3006

x6200

ISR forDevice B

ANDx6202

ISR forDevice C

Execute RTI at x6315; pop PC and PSR from stack.

x6300

x6315 RTI

x6210 RTI

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Example (5)

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PSR for A

x6203

PSR for B

x3007PC

Program A

ADDx3006

x6200

ISR forDevice B

ANDx6202

ISR forDevice C

Execute RTI at x6210; pop PSR and PC from stack.Restore R6. Continue Program A as if nothing happened.

x6300

x6315 RTI

x6210 RTIR6

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Exception: Internal InterruptWhen something unexpected happensinside the processor, it may cause an exception.

Examples:• Privileged operation (e.g., RTI in user mode)• Executing an illegal opcode• Divide by zero• Accessing an illegal address (e.g., protected system memory)

Handled just like an interrupt• Vector is determined internally by type of exception• Priority is the same as running program

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Another use for a stack: ArithmeticReverse Polish Notation (RPN) Calculators

Instead of registers, some ISA's use a stack forsource and destination operations: a zero-address machine.

Operations:

Push – place something on the top of the stack

Pop – remove item on the top of the stack

Arithmetic Operations – • pop two items from the stack• perform operation with those two items• push result onto stack

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Comparison – Registers vs. Stack-Based

Write E = (A+B)*(C+D) using General Purpose Registers(Assume A, B, C, D, and E are labels for a memory location.)

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Comparison – Registers vs. Stack-Based

Write E = (A+B)*(C+D) using a stack:

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Comparison – Registers vs. Stack-Based

Which instructions are larger?

Which requires more instructions?

Which requires more memory operations?

Why use a stack?• Computer has few registers (registers were once expensive)• Simple programming model and ISA• Java’s machine model is a stack.• Reality: stack is stored on-chip in cache

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