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EE 319KIntroduction to Microcontrollers

Lecture 1: Introduction, Embedded Systems, Product

Life-Cycle, ARM Programming

Erez, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi

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AgendaCourse Description

Book, Labs, EquipmentGrading CriteriaExpectations/ResponsibilitiesPrerequisites

Embedded SystemsMicrocontrollers

Product Life CycleAnalysis, Design, Implementation, TestingFlowcharts, Data-Flow and Call Graphs

ARM ArchitectureProgrammingIntegrated Development Environment (IDE)

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Useful Info• No labs this week!• Lab lectures start this Friday

• F 4–5, M 6:30–7:30 and 7:30-8:30 (ECJ 1.202)• Office hours: see Canvas for most recent?• TAs have office hours too

• They are not there to do your work for you• One course == common exams and HW

• 2/23 7–8:30 (15%) 4/6 7–8:30 (20%) Final TBD (25%)• Most of the learning is in the labs

• 10 labs 30% of grade• HW is important too so 10% for motivation

• Read the book and lab manual!• Canvas, Piazza, and

users.ece.utexas.edu/~valvano/Volume1/

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Action Items• Come introduce yourselves• Take stock of resources

• Class Website (Volume1)• Piazza for class discussions• Email to reach TAs+Me• E-Book: Search “Valvano e-book”

• Order board• Install SW• Read Chapters 1 & 2 of book

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DOs and DON’TsDO•Read

• Book, lab, datasheets•Try before seeking help•Follow Piazza/Canvas•Discuss material with others•Homework (not labs) in groups•Consult the web•Track due dates

DON’T•Don’t cheat!•Never look at another student’s code (current or previous)•Don’t let your partner do all the work•Don’t copy software from book or web without attribution•Don’t expect handholding

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EE306 Recap: Digital Logic

Positive logic: Negative logic : True is higher voltage True is lower voltageFalse is lower voltage False is higher voltage

AND, OR, NOT Flip flops Registers

A ~A

74HC04

+3.3V

~An-type

p-type source

gateA

drain

drain

gate source

0 V active off +3.3V+3.3V off active 0V

A p-type n-type ~A

A01

~A 1 0

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EE306, Also

• Problem solving• Programming• Debugging

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EE302 Recap: Ohm’s LawV = I * R Voltage = Current * ResistanceI = V / R Current = Voltage / ResistanceR = V / I Resistance = Voltage / Current

R = 1kBatteryV=3.7V

Resistor

I = 3.7mA

R

I

V

•P = V * I Power = Voltage * Current•P = V2 / R Power = Voltage2 / Resistance•P = I2 * R Power = Current2 * Resistance

1 amp is 6.241×1018 electrons per second = 1 coulomb/sec

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Embedded System Embedded Systems are

everywhere Ubiquitous, invisible Hidden (computer inside) Dedicated purpose

Microprocessor Intel: 4004, ..8080,.. x86 Freescale: 6800, ..

9S12,.. PowerPC ARM, DEC, SPARC, MIPS,

PowerPC, Natl. Semi.,… Microcontroller

Processor+Memory+I/O Ports (Interfaces)I/O Ports

Microcontroller Electrical,mechanical,

chemical,or

opticaldevices

Embedded system

Bus ADCAnalogsignals

LM3S or TM4C

DAC

Processor

RAM

ROM

MedicalAutomotive

Communications

Comsumer Industrial

Military

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Microcontroller Processor – Instruction Set + memory + accelerators

Ecosystem Memory

Non-Volatileo ROM o EPROM, EEPROM, Flash

Volatileo RAM (DRAM, SRAM)

Interfaces H/W: Ports S/W: Device Driver Parallel, Serial, Analog, Time

I/O Memory-mapped vs. I/O-instructions (I/O-mapped)

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Texas Instruments TM4C123

ARM Cortex-M4+ 256K EEPROM+ 32K RAM+ JTAG+ Ports+ SysTick+ ADC+ UART

GPIO Port D

GPIO Port A

ADC2 channels12 inputs12 bits

PA7PA6

PA5/SSI0TxPA4/SSI0RxPA3/SSI0FssPA2/SSI0Clk

PA1/U0TxPA0/U0Rx

PC7PC6PC5PC4

PC3/TDO/SWOPC2/TDI

PC1/TMS/SWDIOPC0/TCK/SWCLK

PE5PE4PE3PE2PE1PE0

GPIO Port C

GPIO Port E

JTAG

FourSSIs

EightUARTs

PB7PB6PB5PB4PB3/I2C0SDAPB2/I2C0SCLPB1PB0

PD7PD6PD5PD4PD3PD2PD1PD0

PF4PF3PF2PF1PF0

GPIO Port B

FourI2Cs

USB 2.0

Cortex M4 SystickNVIC

Two AnalogComparators

Advanced Peripheral Bus

TwelveTimers

Six64-bit wide

CAN 2.0

System Bus Interface

GPIO Port F

Advanced High Performance Bus

Two PWMModules

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LaunchPad Switches and LEDs TM4C123 PF0

PF4R1 0

SW1 SW2PF3

PF2

PF1

330Red

330Blue

5V

330

Green

DTC114EET1G

PD0PB6PD1PB7

0R9

0R10

0R12

0R11

0R2

R13 0PA1PA0

PD5PD4

Serial

USBPB1

R29

0

R25PB0

+5

0

The switches on the LaunchPadNegative logic Require internal pull-up (set bits in PUR)

The PF3-1 LEDs are positive logic

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I/O Ports and Control Registers

The input/output direction of a bidirectional port is specified by its direction register.

GPIO_PORTF_DIR_R , specify if corresponding pin is input or output: 0 means input 1 means output

Input/Output Port

D Q

Write to port direction register

Direction bits

D Q

Write to port address

Processor

Read from port address

Bus

n

n

n

n

n 1 means output0 means input

GPIO_PORTF_DATA_R

GPIO_PORTF_DIR_R

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I/O Ports and Control RegistersAddress 7 6 5 4 3 2 1 0 Name

400F.E608 - - GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_RCGCGPIO_R

4002.53FC - - - DATA DATA DATA DATA DATA GPIO_PORTF_DATA_R

4002.5400 - - - DIR DIR DIR DIR DIR GPIO_PORTF_DIR_R

4002.5420 - - - SEL SEL SEL SEL SEL GPIO_PORTF_AFSEL_R

4002.551C - - - DEN DEN DEN DEN DEN GPIO_PORTF_DEN_R

• Initialization (executed once at beginning) 1. Turn on clock in SYSCTL_RCGCGPIO_R2. Wait two bus cycles (two NOP instructions)3. Unlock PF0 (PD7 also needs unlocking)4. Set DIR to 1 for output or 0 for input5. Clear AFSEL bits to 0 to select regular I/O6. Set PUE bits to 1 to enable internal pull-up7. Set DEN bits to 1 to enable data pins

• Input/output from pin6. Read/write GPIO_PORTF_DATA_R

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Done

• Hardware • Software

• Specifications • Constraints

Analyzethe

problem

RequirementsDesign

Constraints

Testing

• Block diagrams • Data flow graphs

Deployment

New requirementsNew constraints

Development

Product Life Cycle

Analysis (What?)Requirements ->

SpecificationsDesign (How?)

High-Level: Block DiagramsEngineering: Algorithms,

Data Structures, Interfacing

Implementation(Real)Hardware, Software

Testing (Works?)Validation:CorrectnessPerformance: Efficiency

Maintenance (Improve)

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Data Flow Graph

Lab 8: Position Measurement System

PositionSensor

Voltage0 to +3.3V

ADChardware

ADCdriver

Sample0 to 4095

SysTickISR

Sample0 to 4095

SysTickhardware

LCDdisplay

LCDdriver Fixed-point

0 to 2.000

Position0 to 2 cm

main

Mailbox

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Call Flow Graph

Position Measurement System

main

SysTickhardware

SysTickinit

LCDhardware

LCDdriver

SysTickISR

ADChardware

ADCdriver

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Structured ProgrammingCommon Constructs (as Flowcharts)

Fork

Join

Triggerinterrupt

Return from interrupt

main1

Init1

Body1

main2

Init2

Body2

main

Init

Body

Parallel Distributed Interrupt-driven concurrent

Block 1

Sequence Conditional While-loop

Block 2Block 1 Block 2 Block

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FlowchartToaster oven:

Coding in assembly and/or high-level language (C)

main

toast < desired

Output heatis on Too coldInput from

switch

Input toasttemperature

toast desired

Start Not pressed

Pressed

Output heatis off

Cook

return

Cook

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Flowchart Example 1.3. Design a flowchart for a system that performs two independent

tasks. The first task is to output a 20 kHz square wave on PORTA in real time (period is 50 ms). The second task is to read a value from PORTB, divide the value by 4, add 12, and output the result on PORTD. This second task is repeated over and over.

Clockvoid SysTick_Handler(void){ PORTA = PORTA^0x01;}

E

E

<

>

>

void main(void){unsigned long n; while(1){ n = PORTB; n = (n/4)+12; PORTD = n; }}

BCD

A

main

Input n fromPORTB

A

B

D

Cn = (n/4)+12

Output n toPORTD

PORTA =PORTA^1

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ARM Cortex M4-based System

DCode bus

ARM® CortexTM-Mprocessor

DataRAM

InstructionsFlash ROM

Inputports

Outputports

Microcontroller

ICode bus

Internalperipherals

PPB

System bus

AdvancedHigh-perfBus

ARM Cortex-M4 processor Harvard architecture

Different busses for instructions and data

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ARM Cortex M4-based System RISC machine

Pipelining effectively provides single cycle operation for many instructions Thumb-2 configuration employs both 16 and 32 bit instructions

CISC RISC Many instructions Few instructions Instructions have varying lengths Instructions have fixed lengths Instructions execute in varying times Instructions execute in 1 or 2 bus cycles Many instructions can access memory Few instructions can access memory

Load from memory to a register Store from register to memory

In one instruction, the processor can both read memory and write memory

No one instruction can both read and write memory in the same instruction

Fewer and more specialized registers. some registers contain data, others contain addresses

Many identical general purpose registers

Many different types of addressing modes Limited number of addressing modes register, immediate, and indexed.

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ARM ISA: Thumb2 Instruction Set Variable-length instructions

ARM instructions are a fixed length of 32 bits

Thumb instructions are a fixed length of 16 bits

Thumb-2 instructions can be either 16-bit or 32-bit

Thumb-2 gives approximately 26% improvement in code density over ARM

Thumb-2 gives approximately 25% improvement in performance over Thumb

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ARM ISA: Registers, Memory-mapR0R1R2R3R4R5R6R7R8R9

R10R11R12

R13 (MSP)R14 (LR)R15 (PC)

Stack pointerLink register

Program counter

Generalpurposeregisters

TI TM4C123Microcontroller

256k FlashROM

32k RAM

I/O ports

Internal I/OPPB

0x0000.0000

0x0003.FFFF

0x2000.0000

0x2000.7FFF

0x4000.0000

0x400F.FFFF

0xE000.0000

0xE004.1FFF

Condition Code Bits IndicatesN negative Result is negativeZ zero Result is zeroV overflow Signed overflowC carry Unsigned overflow

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LC3 to ARM - Data MovementLEA R0, Label ;R0 <- PC + Offset to Label

ADR R0,Label or LDR R0,=LabelLD R1,Label ; R1 <- M[PC + Offset]

LDR R0,=Label ; Two steps: (i) Get address into R0LDRH R1,[R0] ; (ii) Get content of address [R0] into R1

LDR R1,R0,n ; R1 <- M[R0+n] LDRH R1,[R0,#n]

LDI R1,Label ; R1 <- M[M[PC + Offset]]; Three steps!!

ST R1,Label ; R1 -> M[PC + Offset] LDR R0,=Label ; Two steps: (i)Get address into R0STRH R1,[R0] ; (ii) Put R1 contents into address in R0

STR R1,R0,n ; R1 -> M[R0+n] STRH R1,[R0,#n]

STI R1,Label ; R1 -> M[M[PC + Offset]]; Three steps!!

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LC3 to ARM – Arithmetic/Logic

ADD R1, R2, R3 ; R1 <- R2 + R3ADD R1,R2,R3 ; 32-bit only

ADD R1,R2,#5 ; R1 <- R2 + 5ADD R1,R2,#5 ; 32-bit only, Immediate is 12-bit

AND R1,R2,R3 ; R1 <- R2 & R3 AND R1, R2, R3 ; 32-bit only

AND R1,R2,#1 ; R1 <- Bit 0 of R2 AND R1, R2, #1 ; 32-bit only

NOT R1,R2 ; R1 -> ~(R2)EOR R1,R2,#-1 ; -1 is 0xFFFFFFFF,

; so bit XOR with 1 gives complement

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LC3 to ARM – ControlBR Target ; PC <- Address of Target

B TargetBRnzp Target ; PC <- Address of Target

B TargetBRn Target ; PC <- Address of Target if N=1

BMI Target ; Branch on MinusBRz Target ; PC <- Address of Target if Z=1

BEQ TargetBRp Target ; PC <- Address of Target if P=1

No EquivalentBRnp Target ; PC <- Address of Target if Z=0

BNE TargetBRzp Target ; PC <- Address of Target if N=0

BPL Target ; Branch on positive or zero (Plus)BRnz Target ; PC <- Address of Target if P=0

No Equivalent

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LC3 to ARM – Subs,TRAP,InterruptJSR Sub ; PC <- Address of Sub, Return address in R7

BL Sub ; PC<-Address of Sub, Ret. Addr in R14 (Link Reg)JSRR R4 ; PC <- R4, Return address in R7

BLX R4 ; PC <-R4, Return address in R14 (Link Reg)RET ; PC <- R7 (Implicit JMP to address in R7)

BX LR ; PC <- R14 (Link Reg)JMP R2 ; PC <- R2

BX R2 ; PC <- R14 (Link Reg)TRAP x25 ; PC <- M[x0025], Return address in R7

SVC #0x25 ; Similar in concept but not implementationRTI ; Pop PC and PSR from Supervisor Stack…

BX LR ; PC <- R14 (Link Reg) [same as RET]

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ARM is a Load-Store machineCode to set (to 1) bit 5 of memory address x400FE608

SYSCTL_RCGCGPIO_R EQU 0x400FE608 ; EQU psedo-op allows use of ; symbolic name to represent a constant

LDR R1, =SYSCTL_RCGCGPIO_R ; R1 holds x400FE608 LDR R0, [R1] ; R0 holds contents of ; location x400FE608 ORR R0, R0, #0x20 ; bit5 of R0 is set to 1STR R0, [R1] ; write R0 contents back to ; location x400FE608

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SW Development Environment

0x00000142 49120x00000144 68080x00000146 F040000F0x0000014A 6008

Start; direction register LDR R1,=GPIO_PORTD_DIR_R LDR R0,[R1] ORR R0,R0,#0x0F; make PD3-0 output STR R0, [R1]

Source code

Build Target (F7)

DownloadObject code

Processor

Memory

I/O

SimulatedMicrocontroller

Address Data

Editor KeilTM uVision®

Processor

Memory

I/O

RealMicrocontroller

StartDebugSession

StartDebugSession