Channel Estimation for W-CDMA on DSPs
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Transcript of Channel Estimation for W-CDMA on DSPs
SR: 599 report
Channel Estimation for W-CDMA on DSPs
Sridhar Rajagopal ECE Dept.,
Rice University
Ele
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Organization
W-CDMA.
DSPs in Wireless Communications.
Channel Estimation.
Aim of the 599 Project.
Implementation Issues and Results.
Future Architectures for Wireless systems.
Conclusions and Future Work.
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W-CDMA
Third Generation Communication Systems.
Multimedia Capabilities.
Multirate Services.
Quality Of Service.
Higher Data Rates.
– 2Mbps, 384kbps, 144kbps.
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DSPs in Wireless Communications
Digital Signal Processor.
Signal Processing Communications.
Features :– Low Power Consumption (1.2 V, 100 mW).
– Low Cost (15$).
– High Performance (100 MIPS).
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The Wireless Channel : Multiuser, Multipath
Direct PathReflected
Paths
Faces Attenuation, Delays and Doppler Effects : Unknown Channel Parameters
Antenna
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At the Receiver
DECODER DETECTOR DEMODULATOR
RCHANNEL ESTIMATOR
A, UZ
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ML Channel Estimation
Send a Preamble.
Channel properties embedded in received signal.
Compare and estimate.
Keep estimate for remaining data bits (static).
Repeat preamble every frame, if no tracking.
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Data Transmission in W-CDMA
Mobile #
1.
2.
3.
4.
5.
:time
C1
C7 C3
C2
C2
C8
C4
C4
C1
C2
Packet Preamble for AcquisitionPacket for Data Transmission
DS-CDMA with Slotted ALOHADS-CDMA with Slotted ALOHA
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W-CDMA- Implementation Issues
Computationally intensive algorithms.
Stringent Time, Power, Size constraints.
Pressure on existing hardware resources.
Real -time Requirements :
1ms 10ms
0.2
5 m
s
Preamble Message
Random Access Burst in Slotted ALOHA
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Aim of the 599 Project
Get a grasp of
– W-CDMA.– DSPs.– Channel Estimation.
Implement ML Channel Estimation on DSPs.
Evaluate its performance (“Execution Time”).
Ways to improve the performance.
Future Architectures for Wireless Communications.
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COMMON
The ML Algorithm Complexity
Complex -Real Dot Product.
Complex-Real Matrix Product.
Complex -Real Product.
Real Square roots.– Solving quadratic equation for least squares fit.
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UUUUUyUyz
L
k
L
k
R
k
R
k
L
k
H
k
R
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H
k
H
k
Assuming Unity Noise CovarianceAssuming Unity Noise Covariance
Offline
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TI TMS320C6701 EVM
32-bit Floating Point DSP at 133MHz.
– VLIW Architecture (8 IPC).
– 8 Functional Units ( 2 Multipliers).
– 32 registers in 2 files.
– 64 Kb each Internal Program and Data Memory.
External Memory.
– 256 Kb SBSRAM (Static RAM : faster).
– 8 Mb SDRAM (Dynamic RAM : slower).
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Steps in DSP Implementation
Original Floating Point Code.
Remove File I/O.
Minimize use of functions.
Minimize use of temporary variables.
Pre-computed Data (Offline).
Use Specialized Approximate Instructions.
Use Assembly Code for critical part.
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Use of Approximate Instructions
0 5 10 150
20
40
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80
100
120
140 Use of Approximate instructions in the DSP
Number of users -->
Exe
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Base C67 code C67 Code with Approximations
TMS320C67x DSP Cycles
Approx. FPReciprocalinstruction
1
FP reciprocalfunction
28
Approx. FPReciprocal Sq. root
Instruction
1
FP Reciprocal Sq.root Instruction
34
L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB
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Use of Assembly Code
0 5 10 150
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140
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Use of Assembly code in the DSP
C67: Original C67: with approximationsC67: with Assembly C67: potential
Assembly Codeused
Dot Product
Matrix VectorMultiplication
L = 150, P =3, N= 31, SNR = 5dB,
SINR = -10 dB
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Comparison with UltraSPARCII
0 5 10 150
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60
Number of Users -->
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Execution time for DSP and GPP for ML Channel Estimation (Parameter Extraction)
C67: Assembly C67: Potential UltraSPARC II UltraSPARC II with VIS
UltraSPARCII
•Super-scalar
•4-way in-order
•250 MHz
•VIS support
L = 150, P =3, N= 31, SNR = 5dB,
SINR = -10 dB
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Joint Estimation and Detection
•Improvement in performance as only subset of parameter extraction.
•Improvement in detector also?.
L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB
0 5 10 150
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Number of users
Exe
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Performance of Channel Estimation using joint estimation and detection on "C67
Joint Method Parameter extraction
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Memory Issues
•Data sizes do not fit in Internal memory.
• Onus on Programmer.
•External Memory Latencies.
•Affects performance
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Improvements in Architecture
Internal Memory.– More internal memory required - On-chip DRAMs.
Data Prefetching.– Matrix oriented operations - Prefetch Buffers.
ASIC/FPGA Support.– Offload critical computations (Viterbi Decoder in C54)
Specialized Instructions.– Array Based instructions, Complex Arithmetic.
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Improvements in Compilers
Compiler Efficiency.
– VLIW Compilers unable to extract all parallelism.– Assembly language subroutines.– Advantages of Architecture not used fully.
OS Support.
– Memory Allocation by Programmer.– May not be optimal / Leads to Errors.– Compiler should assist.– Suggestions acknowledged by TI.
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Future Architectures for Wireless
Large On-chip Memory.
Low Cost / High Performance.
Low Power Consumption.
Multiple DSPs.
GPP-DSP-Coprocessor-ASIC-FPGA.
Vector IRAMs.
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Conclusions
Studied ML Channel Estimation on DSPs.
Effect of Approximations (1.1X).
Effect of Assembly (2X).
GPP Comparison (0.2227 X for 15 users).
Joint Estimation and Detection (2.92X for 15 users).
Memory issues: Does not fit in Internal Memory.
Real-time Requirements: Application Dependant.
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Future Work
Effects on Downlink.
Effects of A/D Converter.
Tracking, Multiple sensors, Doppler effects.
Subspace Based Channel Estimation.
Real-time Performance.
Architectures for Wireless Communications.