Challenges of Single Event Upset and Transient

Testing and Characterization of Mixed Signal Products

Kirby Kruckmeyer

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Agenda

• Overview of National Semiconductor’s radiation programs

• Standards and guidelines for Single Event Effect (SEE) testing of mixed signal products– Test conditions

– Reporting Errors

– Single Event Upset and Transient Definitions

• Challenges for SEE testing• Case Studies

– Ultra High Speed Analog to Digital Converter

– Ultra Low Power Digital to Analog Converter

• Summary

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• 30+ years in the Space Market– QMLV qualified products– One of only 10 RHA (Radiation Hardness Assured)

QML suppliers

• Radiation Testing– TID 60Co gamma cell in South Portland, Maine and Santa Clara, California

– ELDRS: ELDRS Free products

– SEE: SEL, SEU and SET testing

Per EIA/JEDEC JESD57 and ESA/SCC 25100

• World class Supply Chain Management– Dedicated space program managers

National - A Major Space Supplier

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• Radiation process developed to improve total dose performance - National’s Scotland plant

– LM137 10 krad 30 krad

– LF411 10 krad 50 krad

– LM101 10 krad 50 krad

– LM111 10 krad 100 krad

– LM136 10 krad 100 krad

– LM158 10 krad 100 krad

– LM124 10 krad 100 krad

– LM139 10 krad 100 krad

– LM117 10 krad 100 krad

– LM117HV 3 krad 100 krad

– LP2953 10 krad In Process

Continue to work on radiation performance for existing devices

Before Today

Total Dose Improvements on Legacy Products

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• We test them so you don’t have to

• Every wafer tested and qualified at low dose rates

– per Mil-Std-883 method 1019 condition D– Low dose rate of 10 mrad/s (36 rad/hr)– Biased and unbiased

• DSCC unique low dose rate certified part numbers

• ELDRS Free Products LM111 LM117 LM124 LM136-2.5LM139 LM158 LM193 LMP2012

• Low Dose Rate Qualified LM117HV

•Products in Qualification LM101 LM119 LM137 LM6142 LM185 LM2940 LM2941

ELDRS-Free Products!

ELDRS-Free LM139

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National is more than just the LM124

Recent New Product Releases:

• ADC08D1000WGFQV 1 GS/s 8 bit Analog to Digital Converter

• ADC08D1520WGFQV 1.5 GS/s 8 bit Analog to Digital Converter

• ADC128S102WGRQV General Purpose 12 bit Analog to Digital Converter – mW Power

• DAC121S101WGRQV General Purpose 12 bit Digital to Analog Converter – mW Power

• LMP2012WGLQMLV Precision Rail to Rail Operational Amplifier

• ADC14155WGRQV 155 MS/s 14 bit Analog to Digital Converter

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How to test a Mixed Signal Part

• Mixed signal inputs and outputs– How do you monitor it all?

• What supply voltage?– Many parts have wide operating

ranges

– What is worst case?

VA

DOUTVIN

CLOCK OUTCONTROL LOGICCLOCK

CHIP SELECT

VOUTDIN

• Static or dynamic inputs?– A 1 GS/s ADC will never be used with static inputs

– How to monitor a product in dynamic mode?

• No universal test system

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Testing Guidance-Limited For Mixed Signal Products• Test development typically starts with FPGA’s and memories, then

moves to analog parts. Mixed signal products are usually an afterthought

– Sandia proton spec in development - using memories as driver– NASA new SEE guidelines (digitally oriented) and Linear SEE Testing

Guidelines• Standards – Oriented towards digital products

– EIA/JEDEC Standard JESD57• Only mentions bit flips; no guidance on analog outputs or transients

• No mention of mixed signal products

– ASTM Standard Guide F 1192 – 00• Two definitions for transients, but no guidance on testing for them

• No mention of mixed signal products

– ESA/SCC Basic Specification 25100• “Analogue and mixed analogue/digital technologies may generate false

outputs or transients as the result of SEE. Test system shall be capable of monitoring and logging these effects.”

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How to Report the Results? - Digital

Is it “errors per bit” or some other measure?

• “Errors per bit” is a standard metric for digital product– Customers put “errors per bit” in PO’s for all kinds of products

– Some datasheets report “errors per bit” on products like PLL’s

• Does not make sense for most mixed signal products?– What is a bit in a PLL?

– ADC bits have varying values and impact

• ADC: should be reported as complete “code errors”

• PLL’s and clocks: should be reported as output “error rate”

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How to Report the Results? - Analog

Is it a transient (SET) or upset (SEU)?• SET and SEU are used interchangeably for reporting errors on

analog outputs• Upset has a clear definition: a logic state change or bit flip• No consensus on definition of SET

– JESD57 and ESA/SCC 25100 have no definition– ASTM F 1192 – 00 has two

• 3.1.12 single event transient-SET is a self correcting upset (change) of state of a bit induced by a single ion strike.

• 3.1.14 single event transients (SET)-SET’s are SE-caused electrical transients that are propagated to the outputs of combinational logic IC’s. Depending upon system application of these combinational logic IC’s, SET’s can cause system SEU.

– Different definitions by NASA and others• DSET – Transients generated from the digital portion of the product• ASET – Transients generated from the analog portion of the product

• Analog outputs: should be reported as transients

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Vin

Bf1

BF2ADC

bank 1

BF2 ADC bank 2

phi1

phi2

SS2

LVDSOutput

LVDSOutput

Bf1

BF2ADC

bank 1

BF2 ADC bank 2

phi1

phi2

LVDSOutput

LVDSOutput

InputMUXwith

CalibrationCircuit

I+I- Q+

Q-

ControlLogic

VBG

÷2OutputClock

Generator

VREF

CLK+CLK-

CLK/2

ControlInputsSerial

Interface 3

DI

DId

DQ

DQd

8

8

8

8

8

8

8

8

T/H

T/H

SS1

SS1

SS2

1.5Ghz 750

Mhz

Case Study: ADC08D1520WGFQV8 b Analog to Digital Converter

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ADC08D1520WGFQV Testing

• Need to monitor– Digital outputs Output codes

– Clock output Differential output

– Control logic Did part setup change

– Calibration Did calibration drift

– Supply currents Analog and output driver supplies

• SEE testing– Latchup (SEL)

– Functional Interrupt (SEFI)

– Upset (SEU)

– Transient (SET)

– Dynamic Inputs

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ADC08D1520WGFQV Test Challenges

• No easy test system– Production test system run $750K to $1.5M and are not portable

• High speed testing (1 GHz or greater) difficult in the field– Coupling seen between the various input and output signals– Heaters for SEL testing can add noise– Remote power supply and supply current monitoring can degrade

performance– Worse in vacuum chamber, with feed throughs

• Considerations if using an FPGA to monitor outputs– Using a separate clock for the FPGA could add more noise– If using ADC clock for FPGA, clock upsets could impact output

results– Monitoring the output clock of ADC can impact the FPGA

performance• Control registers and calibration circuits cannot be monitored in

real time• How to detect upsets with dynamic input and output

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Solution – Two Setups

• Output SEU– Dedicated board for clean signals and

high resolution output– noise floor 5 LSB– Onboard FPGA to monitor output– Clean clock output line to FPGA– Onboard regulator– Use Beat Frequency and Code Error Test

Method for dynamic testing

• SEL, SEFI and Clock SEU– Output signal not as critical– Remote power supply with monitor

and heaters for SEL– FIFO instead of FPGA so output

clock could be monitored– Fast Fourier Transform (FFT) run

before and after each ion run to monitor SEFI

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Co

de

Sampled Output

Input Clock

DIDId

Channel I

difference

Beat Frequency and Code ErrorTest Method• Beat Frequency allows part to be tested with input frequency close to 2X

Nyquist– Output = sample rate – input signal– Set the input frequency so that the output will change by less than 1 LSB per clock

cycle

• Code Error routine calculates the output delta from one clock cycle to the next

– An error is recorded if the output delta is more than some threshold– Set to 6 LSB due to the background noise at the test facility

Input Output

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ADC08D1520WGFQV SEE Test Results

• Output code SEU– Errors are not bit flips in the

digital output, they are code errors caused by transients

– Error magnitude dependent upon the input voltage

• Output clock SEU– Two types of errors seen– Signal attenuation– Phase shift

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ADC08D1520WGFQV Cross Section Curves

Output upset cross section• Shown in terms of complete

code errors upset events and not errors per bit

• Figure of Merit Calculation:

3.6 x 10-3 upsets per month

• Outage time (factoring in upset length): 5.8 ns per month

Clock upset cross section• Shown in terms of upset events

• Figure of Merit Calculation:

4.0 x 10-5 upsets per month

• Outage time (factoring in upset length): 2.1 ps per month

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Case study: DAC121S101WGRQV12 b Digital to Analog Converter

• How should a Digital to Analog Converter be tested?

• What operating conditions cause the worst case?– Cross section

– Transient amplitude and pulse width

• Operating conditions?– Supply voltage

– Inputs

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• Standards suggest lowest operating voltage– EIA/JESD 57

“As a rule, the worst case condition is at minimum operating voltage”

– ASTM F1192

“A lower bias (minimum of the specified operating range) promotes bit-flips….”

• For analog products, testing shows that maximum operating voltage and minimum input bias is sometimes the worst case

Worst Case Conditions for SET for a Mixed-Signal Part???

LM

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LM

12

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Source: “Testing Guidelines for Single Event Transient (SET) Testing of Linear Devices” C. Poivoy, et al, NASA Goddard Space Flight Center

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DAC121S101WGRQV12 b Digital to Analog Converter

2.7 V to 5.5 V Supply Voltage Range (1.43 mW)

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DAC121S101WGRQV12 b Digital to Analog Converter

2.7 V to 5.5 V Supply Voltage Range (1.43 mW)

Serial input (code range: 0 to 4095)20 MHz

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DAC121S101WGRQV12 b Digital to Analog Converter

2.7 V to 5.5 V Supply Voltage Range (1.43 mW)

Serial input (code range: 0 to 4095)

Rail to rail voltage output

20 MHz

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Test Conditions

DAC121S101Eval Board

Setup insidechamber

Tested with static input - typical application

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Dependence on Supply Voltage

SET Cross Section vs. LET for input code = 3482

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Transient Signatures

Positive

Negative

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Negative transient dependence on input code

-1

-0.5

0

0.5

1

1.5

2

0 1000 2000 3000 4000 5000Pulse width (ns)

Am

pli

tud

e (

V)

Bi

Ta

Tb

Xe

Kr

Cu

Ar

Ne

Input code = 614001001100110

15% of full scale

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Negative transient dependence on input code

-1

-0.5

0

0.5

1

1.5

2

0 1000 2000 3000 4000 5000Pulse width (ns)

Am

pli

tud

e (

V)

Bi

Ta

Tb

Xe

Kr

Cu

Ar

Ne

Input code = 614001001100110

15% of full scale

28

Negative transient dependence on input code

-1

-0.5

0

0.5

1

1.5

2

0 1000 2000 3000 4000 5000Pulse width (ns)

Am

pli

tud

e (

V)

Bi

Ta

Tb

Xe

Kr

Cu

Ar

Ne

-1

-0.5

0

0.5

1

1.5

2

0 1000 2000 3000 4000 5000Pulse width (ns)

Am

pli

tud

e (V

)

Bi

Ta

Tb

Xe

Kr

Cu

Ar

Ne

Input code = 614001001100110

15% of full scale

Input code = 3482110110011010

85% of full scale

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Negative transient dependence on input code

-1

-0.5

0

0.5

1

1.5

2

0 1000 2000 3000 4000 5000Pulse width (ns)

Am

pli

tud

e (

V)

Bi

Ta

Tb

Xe

Kr

Cu

Ar

Ne

-1

-0.5

0

0.5

1

1.5

2

0 1000 2000 3000 4000 5000Pulse width (ns)

Am

pli

tud

e (

V)

Bi

Ta

Tb

Xe

Kr

Cu

Ar

Ne

-1

-0.5

0

0.5

1

1.5

2

0 1000 2000 3000 4000 5000Pulse width (ns)

Am

pli

tud

e (V

)

Bi

Ta

Tb

Xe

Kr

Cu

Ar

Ne

Input code = 614001001100110

15% of full scale

Input code 2048100000000000

50% of full scale

Input code = 3482110110011010

85% of full scale

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Summary

• Testing mixed signal products can be complex and challenging

• There are very few standards or guidelines for testing mixed signal products

• Some unique test methods are needed• Mixed signal Single Event Transient and Upset

responses can be very different than for either pure digital or pure analog products

• It is necessary to characterize a product over all application conditions that will be used

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