Ch6 I MOS Inverters Switching Characteristics I 2 13

8/12/2019 Ch6 I MOS Inverters Switching Characteristics I 2 13

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1

CMOS Digital Integrated Circuits

Ch6 CMOS Inverters:

Switching Characteristics

and Interconnect Effects I

2

CMOS Inverters Dynamic Analysis and Design

Goals

Understand the detail dynamic analysis of the

CMOS inverter.

Understand one set of design from CMOS

equations.

Understand the basic CMOS design process

using the CMOS static and CMOS design form

dynamic equations.

6.1 Introduction


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CMOS Dynamic Analysis: Capacitance Model for CMOS

Vout

VDD

Vin

Cgs,p

Cint

Csb,p

Cgs,n

Cgd,n

Cgd,p

Csb,n

Cdb,p

Cdb,n

Cg

FO

Fig. 6.1 Cascoded CMOS Inverter stages

4

CMOS Dynamic Analysis: Capacitance Model for CMOS

The aggregate capacitance driven by the output

node of a CMOS inverter is in detail working from

left to right,

Cload= Cinput+ Cint+ Cg

in which

Cinput= Cgd,n + Cgd,p + Cdb,n + Cdb,p (intrinsiccomponent)

Cint= interconnect capacitance

Cg= thin-oxide capacitance over the gate area

(extrinsic component)


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CMOS Dynamic Analysis: Delay-Time Definitions

PHL

VOH

V50%

VOL

Vin

t

idealized

step input

VOH

V50%

VOL

Vout

tVout

PLH

t0 t1 t2 t3

fallV90%

V10%t

rise

tA tB tC tD

V50% = VOL+(VOH-VOL)/2

. = (VOH+VOL)/2

PHL = t1-t0

PLH = t3-t2

P = (PHL+PLH)/2

V10% = VOL+0.1(VOH-VOL)

V90% = VOL+0.9(VOH-VOL)

fall= tB-tA

rise = tC-tD

Fig. 6.3

Fig. 6.4


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CMOS Dynamic Analysis

Delay-Time Calculation (First Order Estimates)

The simplest approach of calculating the propagation

delay is based on estimating the average capacitance

currentduring charge down/up.

where I

VVC

I

VVC

LHavg

OLloadPLH

HLavg

OHloadPHL

,

%50

,

%50

)(

)(

=

=

[ ]

[ ]),(),(2

1

),(),(21

%50,

%50,

VVVViVVVViI

VVVViVVVViI

OLoutOLinCoutOLinCLHavg

outOHinCOHoutOHinCHLavg

==+===

==+===

6.3 Calculation of Delay Times

8

CMOS Dynamic Analysis

Delay-Time Calculation (More Accurate)(1/4)

The propagation delay can be found more accurately by

solving the state equation of the output node. The current

flowing through Cloadis a function Voutas

PHL: PMOS is off. The equivalent circuit during high-to-low output transition is

iiidt

dVC nDpDC

outout ,, ==

Vin nMOS

iD,n

Cload

Vout

iidt

dVC nDC

outout ,==

VinVout

iC

iD,p

iD,n

Fig. 6.5


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CMOS Dynamic Analysis: Delay-Time Calculation (2/4)

The nMOS operates in two regions, saturation and linear,

during the interval of PHL.

Saturation Region

iD,n=(kn/2)(Vin-VT,n)2=(kn/2)(VOH-VT,n)

2

Plug iD,n into CloaddVout/dt=-iD,n, and integrate both sides,

we get

t1-t0 = 2CloadVT,n/[kn(VOH-VT,n)

2]

PHL

VOH=VDD

V50%

VOH -VT,n

Vout

tt0 t1

nMOS in saturation

nMOS in linear region

t1 Fig. 6.6

10


Linear Region

iD,n= (kn/2)[2(Vin - VT,n)Vout- Vout2]

= (kn/2)[2(VOH- VT,n)Vout- Vout2]

Plug iD,n into CloaddVout/dt=-iD,n, and integrate both

sides, we have

Finally, since VOH=VDD and VOL=0, we have

, ,

, ,

4( )2ln 1

( )

T n DD T nload

n DD T n DD T n D

HL

D

P

V V VC

V V V V V

= +

PHL

VOH

V50%

VOH -VT,n

Vout

tt0 t1

nMOS in saturation

nMOS in linear region

t1

,

, 50%

4( )ln

( )

DD T nload

n DD T n

V VC

V V V

=

'

1 1t t

Fig. 6.6


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PLH: NMOS is off. The equivalent circuit during low-to-

high output transition is

With the similar way (t0t1t10|VT,p|V50%

saturation linear ), we can have

VinpMOS

iD,p

Cload

Vout

VDD

, ,

, ,

2 4( )ln 1

( )

T p DD T pload

p DD T p D D

L

D T p

P H

D

V V VC

V V V V V

= +

12

CMOS Inverter Design

Design for Performance

Keep capacitance small

Increase transistor size

Watch out for self-loading!

Increase VDD

6.4 Inverter Design with Delay Constraints


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CMOS Inverter Design: Delay as a Function of VDD

VDD increases PHL/PLHdecreases. However,

the power consumption also increases.

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

pHL(normalized)


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CMOS Inverter Design: Device Sizing (1/5)

2 4 6 8 10 12 142.

0

2.2

2.4

2.6

2.8

3.2

3.4

3.6

3.8x 10

-11

S

p(sec)

3.0

Self-loading effect:

Intrinsic capacitances

dominate

(for fixed load)

16


NMOS/PMOS Ratio

R = Wp/ Wn

1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

4

4.5

5x 10

-11

R

p

(sec)

PLH PHL

P


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Self-Loading Effect

Cload = Cgd,n(Wn) + Cgd,p(Wp) + Cdb,n(Wn) + Cdb,p(Wp) + Cint+Cg

= f(Wn,Wp)

Using the junction capacitance expressions in Chapter 3, we have

Cdb,n = (WnDdrain+xjDdrain)Cj0,nKeq,n+(Wn+2Ddrain)Cjsw,nKeq,n

Cdp,n = (WpDdrain+xjDdrain)Cj0,pKeq,p+(Wp+2Ddrain)Cjsw,pKeq,p

Therefore, Cloadcan be rewritten as

Cload = 0+ nWn+ pWp

where

0 =Ddrain(2Cjsw,nKeq,n+2Cjsw,pKeq,p+xjCj0,nKeq,n+xjCj0,pKeq,p)+Cint+Cg

n =Keq,n(Cj0,nDdrain+Cjsw,n)

p =Keq,p(Cj0,pDdrain+Cjsw,p)

small

18


Therefore, PHL and PLHare

The ratio between the channel widths Wn and Wp is

usually dictated by other design constraints such asnoise margins and the logic inversion threshold.

Lets this transistor aspect ratio be defined asR

Wp/Wn. Then, the propagation delay can be

represented as

( )( )

( )( )

,,

, ,

,,

,,

0

0

42ln 1

42ln 1

DD T nT nnPHL

ox DD T n DD T n DDn

DD T pT pp

P

n n p p

n

n

LH

DD T p DDox DD T pn

n p p

p

W W

W

W

V VVL

C V V V V V

V VVL

V V VC V V

W

W

= +

=

+ +

+ +

+

0

0

( )

( )

PH L

PL H

n p n

n

n

np p

p

p

R W

W

WR

W

+ +

+ +

=

=


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As we continue increase the values of Wn and

Wp, the propagation delay will asymptotically

approach a limit value for lager Wn and Wp,

The propagation delay times cannot be

reduced beyond the above limits, and the

limit is independent of the extrinsic

capacitances.

( )

( )

limit

PHL

limit

P

n n p

npH pL

R

R

=

=

+

+

20

CMOS Inverter Design: Impact of Rise Time on Delay

pHL(nsec)

0.35

0.3

0.25

0.2

0.15

rise(nsec)10.80.60.40.20

( )

( )

2(step input)

2(step input)

2

2

2

2

PHL PHL

P

r

f

LH PLH

= +

= +

Propagation delay increases

since both PMOS and

NMOS are on during the

charge-up and charge-down

events.


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CMOS Inverter Design

Impact of Channel Velocity Saturation

The drain current is linearly dependent on VGS

Isat= Wn (VGS-VT)

Propagation delay only has a weak dependence on the

supply voltage VDD

( )

( )

50%/2load DD

n

load

PHD T

Lsat D

C V

W V

C V

I V =

22

CMOS Dynamic Analysis: Dynamic Power Dissipation (1/2)

The dynamic power dissipation can be derived as

follows.

Pdyn,avg= VDDIDD,avg

WithIDD,avgtaken over one clock period T. The

capacitance current which equals the current from the

power supply (assumingIDn = 0 during charging) is

Rearranging and integrating over one clock period T

Gives

IDD,avgT = CloadVDD

dt

dVCI

outloadD=

= V

outload

T

D

DD

dVCdtI00


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CMOS Dynamic Analysis: Dynamic Power Dissipation (2/2)

Solving forIDD,avgand substituting inPavg:

In terms of SPICE simulation, the authors offera circuit called power meter.

It should be noted here the our simple Cload

may underestimate the power dissipated. In terms of SPICE simulation, it offers a circuit

called power meter.

fVCVCT

P DDloadDDloadavg221 ==

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13/13

Ch6 I MOS Inverters Switching Characteristics I 2 13

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