Ch 5 . Logic Design with MSI Components
-
Upload
pascale-foreman -
Category
Documents
-
view
48 -
download
8
description
Transcript of Ch 5 . Logic Design with MSI Components
Ch 5.Logic Design with MSI
Components
Csci 2021 Srping02 2
VHDL The U.S. Department of Defense (DoD) supported the development of VHDL
(VHSIC hardware description language) as part of the VHSIC (very high-speed IC) program in the early 1980s. The companies in the VHSIC program found they needed something more than schematic entry to describe large ASICs, and proposed the creation of a hardware description language. VHDL was then handed over to the Institute of Electrical and Electronics Engineers (IEEE) in order to develop and approve the IEEE Standard 1076-1987. 1 As part of its standardization process the DoD has specified the use of VHDL as the documentation, simulation, and verification medium for ASICs (MIL-STD-454). Partly for this reason VHDL has gained rapid acceptance, initially for description and documentation, and then for design entry, simulation, and synthesis as well.
The first revision of the 1076 standard was approved in 1993. References to the VHDL Language Reference Manual (LRM) in this chapter--[VHDL 87LRM2.1, 93LRM2.2] for example--point to the 1987 and 1993 versions of the LRM [IEEE, 1076-1987 and 1076-1993]. The prefixes 87 and 93 are omitted if the references are the same in both editions. Technically 1076-1987 (known as VHDL-87) is now obsolete and replaced by 1076-1993 (known as VHDL-93). Except for code that is marked 'VHDL-93 only' the examples in this chapter can be analyzed (the VHDL word for "compiled") and simulated using both VHDL-87 and VHDL-93 systems.
Csci 2021 Srping02 3
Csci 2021 Srping02 4
Csci 2021 Srping02 5
Csci 2021 Srping02 6
Csci 2021 Srping02 7
Logic Gates and Symbols
ab F
ab F a F
F = a b F = a + b F = !a
And Or Not
A B F
0 0 0
0 1 0
1 0 0
1 1 1
A B F
0 0 0
0 1 1
1 0 1
1 1 1
A F
0 1
1 0
Csci 2021 Srping02 8
Csci 2021 Srping02 9
Csci 2021 Srping02 10
Csci 2021 Srping02 11
Logic Equation Representation: Sum-of-Products (SOP)
SOP form:
A collection of ANDed variables are Ored together.
Example:
A B F0 0 10 1 01 0 01 1 1
F = !A!B + AB
Also called XNOR
Csci 2021 Srping02 12
Example of SOPExample: A three-input majority function
The function is true when more than half of its inputs are true
F =?
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Csci 2021 Srping02 13
Example of SOPExample: A three-input majority function
The function is true when more than half of its inputs are true
F =!ABC+A!BC+AB!C+ABC
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Csci 2021 Srping02 14
Csci 2021 Srping02 15
Digital Components• High level digital designs are usually made using collections
of logic gates. Such collection of gates are referred as components.• Multiplexer and Decoder are commonly used digital
components.• Levels of integration
SSI (Small Scale Integration) 10-100 components per chipMSI (Medium Scale Integration) 100-1,000 components per chipLSI (Large Scale Integration) 1000-10,000 components per chipVLSI (Very Large Scale Integration) – HigherULSI (Ultra Large Scale Integration) – Higher, higher!
Csci 2021 Srping02 16
Csci 2021 Srping02 17
Csci 2021 Srping02 18
Example: using MUX for Majority
Csci 2021 Srping02 19
An 8-bit multiplexer
entity Mux8 is
generic (TPD : TIME := 1 ns);
port (A, B : in BIT_VECTOR (7 downto 0);
Sel : in BIT := '0'; Y : out BIT_VECTOR (7 downto 0));
end;
architecture Behave of Mux8 is
Begin
Y <= A after TPD when Sel = '1' else B after TPD;
end; Eight 2:1 MUXs withsingle select input.
Timing: TPD (input to Y) = 1 ns
Csci 2021 Srping02 20
Csci 2021 Srping02 21
Csci 2021 Srping02 22
Example: Using Decoder for Majority
Csci 2021 Srping02 23
Csci 2021 Srping02 24
Csci 2021 Srping02 25
Csci 2021 Srping02 26
Csci 2021 Srping02 27
Carry-In A B Sum Carry-out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Sum = A’BC’ + AB’C’ + A’B’C + ABCCarry-out = ABC’ + A’BC + AB’C + ABC
Csci 2021 Srping02 28
A full adder
Entity Full_Adder is generic (TS : TIME := 0.11 ns; TC : TIME := 0.1 ns); port (X, Y, Cin: in BIT; Cout, Sum: out BIT); end Full_Adder;
architecture Behave of Full_Adder is begin Sum <= X xor Y xor Cin after TS; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after TC; end; Timing:TS (Input to Sum) = 0.1 1 nsTC (Input to Cout) = 0.1 ns
Csci 2021 Srping02 29
An 8-bit ripple-carry adder entity Adder8 is port (A, B: in BIT_VECTOR(7 downto 0); Cin: in BIT; Cout: out BIT; Sum: out BIT_VECTOR(7 downto 0));end Adder8; architecture Structure of Adder8 is component Full_Adder port (X, Y, Cin: in BIT; Cout, Sum: out BIT); end component; signal C: BIT_VECTOR(7 downto 0); begin Stages: for i in 7 downto 0 generate LowBit: if i = 0 generate FA:Full_Adder port map (A(0),B(0),Cin,C(0),Sum(0)); end generate; OtherBits: if i /= 0 generate FA:Full_Adder port map (A(i),B(i),C(i-1),C(i),Sum(i)); end generate; end generate; Cout <= C(7); end;
Csci 2021 Srping02 30
The single input lineinto each AND gaterepresents 6 input lines
The single input line into each OR gate represents 8 lines
Darkened circles are placedat crosspoints to indicate connections are made
Csci 2021 Srping02 31
Csci 2021 Srping02 32
Csci 2021 Srping02 33
Csci 2021 Srping02 34
When A,B,C all changed from 0 to 1, there willBe a glitch.
Csci 2021 Srping02 35
Flip-Flop
• A Flip-flop is an arrangement of logic gates that maintains a stable output even after the inputs are made inactive.
• A flip flop can be used to store a single bit of information.
• A S-R flip flop holds a single bit of information and serve as an elementary memory cell.
• In order to achieve synchronization in a controlled fashion, a clock signal is provided. Every state-dependent circuit synchronizes itself by accepting inputs only at discrete times.
Csci 2021 Srping02 36
Csci 2021 Srping02 37
Csci 2021 Srping02 38
Csci 2021 Srping02 39
Csci 2021 Srping02 40
Csci 2021 Srping02 41
Csci 2021 Srping02 42
Csci 2021 Srping02 43
Csci 2021 Srping02 44
Truth Table for Mod-4 Counter
RESET S1 S0 S1/S0 Q1/Q0
0 0 0 0/1 0/1
0 0 1 1/0 1/0
0 1 0 1/1 1/1
0 1 1 0/0 0/0
1 0 0 0/0 0/0
1 0 1 0/0 0/0
1 1 0 0/0 0/0
1 1 1 0/0 0/0
Note that S1/S0 are identical to Q1/Q0
Csci 2021 Srping02 45
Csci 2021 Srping02 46
Csci 2021 Srping02 47
Csci 2021 Srping02 48
Csci 2021 Srping02 49
Finite State Machine
4X5 PLA
Q DS0
Q DS1
X1
X0
Z2
Z1Z0
CLK
Csci 2021 Srping02 50
Truth Table for Vending Machine S1 S0 X1 X0 S1 S0 Z0 Z1 Z2
0 0 0 0 0 1 0 0 0
0 0 0 1 1 0 0 0 0
0 0 1 0 0 0 1 1 0
0 1 0 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0
0 1 1 0 0 0 1 0 1
1 0 0 0 1 1 0 0 0
1 0 0 1 0 0 1 0 0
1 0 1 0 0 0 1 1 1
1 1 0 0 0 0 1 0 0
1 1 0 1 0 0 1 1 0
1 1 1 0 0 1 1 1 1
Csci 2021 Srping02 51
Example
• Assume our vending machine takes only nickels and dimes.
• The machine vends items for 15 cents.
• What is the state transition diagram?
Csci 2021 Srping02 52
Example
• Assume our vending machine takes only nickels and dimes.
• The machine vends items for 15 cents.
• What is the state transition diagram?
A0 cent
B5 cent
C10 cent
N/00
N/00
N/10
D/00
D/10
D/11
N/D: Nickel or Dime0/1: dispense or not 0/1: return nickel or not