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Reconfigurable computingReconfigurable computing is a computer architecture combining some of the flexibility of software withthe high performance of hardware by processing with very flexible high speed computing fabrics like field-programmable gate arrays (FPGAs). The principal difference when compared to usingordinary microprocessors is the ability to make substantial changes to the datapath itself in addition to the

control flow. On the other hand, the main difference with custom hardware, i.e. application-specificintegrated circuits (ASICs) is the possibility to adapt the hardware during runtime by "loading" a newcircuit on the reconfigurable fabric.

Current systems

The reconfigurable computers can be categorized in two classes of architectures: hybrid computer and

fully FPGA based computers. Both architectures are designed to transport the benefits of reconfigurable

logic to large scale computing. They can be used in traditional CPU cluster computers and network infra

structures.

The hybrid computer combine a single or a couple of reconfigurable logic chip, FPGAs, with a standard

microprocessor CPU by exchanging e.g. one CPU of a multi CPU board with a FPGA, also known

as hybrid-core computing , or adding a PCI or PCI Express based FPGA expansion card to the computer.

Simplified, they are Von-Neumann based architectures with an integrated FPGA accelerator. This

architectural compromise results in a reduced scalability of hybrid computers and raises their power

consumption. They have the same bottlenecks as all von Neumann based architectures have

nevertheless it enables users to get an acceleration of their algorithm without losing their standard CPU

based environment.

A relatively new class are the fully FPGA based computers. This class usually contains no CPUs or uses

the CPUs only as interface to the network environment. Their benefit is to transport the energy efficiency

and scalability of FPGAs fully without compromise to their users. Depending on the Architecture of the

interconnection between the FPGAs these machines are fully scalable even across single machine

borders. Their bus system and overall architecture eliminate the bottlenecks of the von Neumann

architecture.

Programming of reconfigurable computers

The FPGA reconfiguration can be accomplished either via the traditional hardware description

languages (HDLs), which can be generated directly or by using electronic design automation ("EDA") or

electronic system level ("ESL") tools, employing high level languages like the graphical tool Starbridge

Viva or C-based languages like for example ROCCC 2.0 from Jacquard Computing Inc. ,Impulse

C from Impulse Accelerated Technologies , SystemC , LISA, Handel-C from Celoxica , DIME-

C from Nallatech , C-to-Verilog.com or Mitrion-C from Mitrionics , or graphical programming languages

like LabVIEW .

http://en.wikipedia.org/wiki/Computer_architecturehttp://en.wikipedia.org/wiki/Computer_architecturehttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Datapathhttp://en.wikipedia.org/wiki/Datapathhttp://en.wikipedia.org/wiki/Datapathhttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/CPUhttp://en.wikipedia.org/wiki/CPUhttp://en.wikipedia.org/wiki/Hybrid-core_computinghttp://en.wikipedia.org/wiki/Hybrid-core_computinghttp://en.wikipedia.org/wiki/Hybrid-core_computinghttp://en.wikipedia.org/wiki/Conventional_PCIhttp://en.wikipedia.org/wiki/Conventional_PCIhttp://en.wikipedia.org/wiki/Conventional_PCIhttp://en.wikipedia.org/wiki/PCI_Expresshttp://en.wikipedia.org/wiki/PCI_Expresshttp://en.wikipedia.org/wiki/Von_Neumann_architecturehttp://en.wikipedia.org/wiki/Von_Neumann_architecturehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/w/index.php?title=Starbridge_Viva&action=edit&redlink=1http://en.wikipedia.org/w/index.php?title=Starbridge_Viva&action=edit&redlink=1http://en.wikipedia.org/w/index.php?title=Starbridge_Viva&action=edit&redlink=1http://en.wikipedia.org/w/index.php?title=Starbridge_Viva&action=edit&redlink=1http://en.wikipedia.org/wiki/C_(programming_language)http://en.wikipedia.org/wiki/C_(programming_language)http://jacquardcomputing.com/roccc/http://jacquardcomputing.com/http://jacquardcomputing.com/http://en.wikipedia.org/wiki/Impulse_Chttp://en.wikipedia.org/wiki/Impulse_Chttp://en.wikipedia.org/wiki/Impulse_Chttp://en.wikipedia.org/w/index.php?title=Impulse_Accelerated_Technologies&action=edit&redlink=1http://en.wikipedia.org/wiki/SystemChttp://en.wikipedia.org/wiki/Language_for_Instruction_Set_Architecturehttp://en.wikipedia.org/wiki/Language_for_Instruction_Set_Architecturehttp://en.wikipedia.org/wiki/Handel-Chttp://en.wikipedia.org/w/index.php?title=Celoxica&action=edit&redlink=1http://en.wikipedia.org/w/index.php?title=Celoxica&action=edit&redlink=1http://en.wikipedia.org/wiki/DIME-Chttp://en.wikipedia.org/wiki/DIME-Chttp://en.wikipedia.org/wiki/DIME-Chttp://en.wikipedia.org/wiki/DIME-Chttp://en.wikipedia.org/wiki/Nallatechhttp://www.c-to-verilog.com/http://www.c-to-verilog.com/http://en.wikipedia.org/wiki/Mitrionicshttp://en.wikipedia.org/wiki/LabVIEWhttp://en.wikipedia.org/wiki/Computer_architecturehttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Datapathhttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/CPUhttp://en.wikipedia.org/wiki/Hybrid-core_computinghttp://en.wikipedia.org/wiki/Conventional_PCIhttp://en.wikipedia.org/wiki/PCI_Expresshttp://en.wikipedia.org/wiki/Von_Neumann_architecturehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/w/index.php?title=Starbridge_Viva&action=edit&redlink=1http://en.wikipedia.org/w/index.php?title=Starbridge_Viva&action=edit&redlink=1http://en.wikipedia.org/wiki/C_(programming_language)http://jacquardcomputing.com/roccc/http://jacquardcomputing.com/http://en.wikipedia.org/wiki/Impulse_Chttp://en.wikipedia.org/wiki/Impulse_Chttp://en.wikipedia.org/w/index.php?title=Impulse_Accelerated_Technologies&action=edit&redlink=1http://en.wikipedia.org/wiki/SystemChttp://en.wikipedia.org/wiki/Language_for_Instruction_Set_Architecturehttp://en.wikipedia.org/wiki/Handel-Chttp://en.wikipedia.org/w/index.php?title=Celoxica&action=edit&redlink=1http://en.wikipedia.org/wiki/DIME-Chttp://en.wikipedia.org/wiki/DIME-Chttp://en.wikipedia.org/wiki/Nallatechhttp://www.c-to-verilog.com/http://en.wikipedia.org/wiki/Mitrionicshttp://en.wikipedia.org/wiki/LabVIEW

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Granularity

The granularity of the reconfigurable logic is defined as the size of the smallest functional unit

(configurable logic block, CLB) that is addressed by the mapping tools. High granularity, which can also

be known as fine-grained, often implies a greater flexibility when implementing algorithms into the

hardware. However, there is a penalty associated with this in terms of increased power, area and delay

due to greater quantity of routing required per computation. Fine-grained architectures work at the bit-

level manipulation level; whilst coarse grained processing elements (reconfigurable datapath unit, rDPU)

are better optimised for standard data path applications. One of the drawbacks of coarse grained

architectures are that they tend to lose some of their utilisation and performance if they need to perform

smaller computations than their granularity provides, for example for a one bit add on a four bit wide

functional unit would waste three bits. This problem can be solved by having a coarse grain array

(reconfigurable datapath array , rDPA) and a FPGA on the same chip.

Coarse-grained architectures ( rDPA ) are intended for the implementation for algorithms needing word-

width data paths (rDPU). As their functional blocks are optimized for large computations and typically

comprise word wide arithmetic logic units (ALU), they will perform these computations more quickly and

with more power efficiency than a set of interconnected smaller functional units; this is due to the

connecting wires being shorter, resulting in less wire capacitance and hence faster and lower power

designs. A potential undesirable consequence of having larger computational blocks is that when the size

of operands may not match the algorithm an inefficient utilisation of resources can result. Often the type

of applications to be run are known in advance allowing the logic, memory and routing resources to be

tailored (for instance, see KressArray Xplorer ) to enhance the performance of the device whilst still

providing a certain level of flexibility for future adaptation. Examples of this are domain specific arrays

aimed at gaining better performance in terms of power, area, throughput than their more generic finer

grained FPGA cousins by reducing their flexibility.

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