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SRAM Design for VFAT3/GdSP

CERN - Jérôme Masson – 21/03

March 21, 2013 SRAM Design for VFAT3/GdSP - CERN

OutlineObjectivesPointers of the issueStrategy

March 21, 2013 2/9SRAM Design for VFAT3/GdSP - CERN

ObjectivesPerform a new implementation of memory modules

for VFAT3/GdSP developmentWhy?

IBM CMOS 130 nm Dual Port

Bypass the issue

March 21, 2013 3/9SRAM Design for VFAT3/GdSP - CERN

Pointers of the issueVFAT2 had 2 memory modules

SRAM1SRAM2

Radiation environment Hamming encoding

March 21, 2013 4/9SRAM Design for VFAT3/GdSP - CERN

SRAM (1/3)Divide SRAM1 … in several little modules

Idea :

Available memory generator for modules

March 21, 2013 5/9SRAM Design for VFAT3/GdSP - CERN

………

M_1 M_nSRAM1

128

800 latencyread ptr write ptr

SRAM Design for VFAT3/GdSP - CERN

SRAM (2/3)Memory implementation and control

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clk

read_enwrite_en

address <6:0> data_in <63:0>

data_out <63:0>

M_1

M_1bis

64

64

128

deco

der

clk

LV1

A

wri

te_e

n read

_en ad

dre

ss

SRAM (3/3)RECAP, first sizing

Use of the memory generatorSize of a memory module : 128 x 64

W = 156 µm ; L = 428 µmTotal area for SRAM1 (#20 modules) Area # 1.3 mm²

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FIFO and Hamming EncodingFIFOHamming Encoding

extra bits so extra size…

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SRAM Design for VFAT3/GdSP - CERN

Thank you for paying attention

March 21, 2013 9/9