Feb 01V 1.2

Preliminary Product Information This document contains Information for a new product. Cortologic reserves the right to modify this product without notice.

Cortologic AG Ostendstr. 25 Tel.: +49 (0) 30 / 53 00 56 - 0 12459 Berlin Fax.: +49 (0) 30 / 53 00 56 –11 Germany http: //www.cortologic.com

CENS90200

Echo & Noise Suppression Circuit

Features: • = Single chip solution with single 3.3 V

power supply (3.0 to 3.6 V) • = Power consumption: typ. 43 mA (@3.3V) • = 64-pin plastic LQFP Package • = Echo Suppression 40 dB (max.) • = Suppression of signals with an echo path

delay of up to 128ms (@ 8 kHz sampling frequency)

• = Noise Suppression 20 dB (typ.) • = Variable sampling frequency (8 kHz to

11,025 kHz) • = Single ended analogue inputs and outputs • = Industry standard digital audio Interface • = Crystal oscillator interface

Description: The CENS90200 is a single chip solution developed for portable, hands free communication with built-in full duplex acoustic echo cancelling and a noise suppressor for the transmission signal. Integrated into the chip are two linear codecs, one for the transmit and one for the receive path. In addition digital I²S(1) interfaces are available for both paths. This device is ideally suited for hands free applications since the echo canceller and the noise suppressor are fully self-adapting with no programming necessary. For noise suppression, one of eight attenuation levels can be selected. The block diagram of the CENS90200 is given in Figure 1. As an additional feature, the CENS90200 offers the spectrum of the output signal of the transmit path. For further information see Appendix 1.

(1) I²S (Inter-IC sound bus) is a registered trademark of Philips

DAC

I2S

ADC

I2S

acousticecho

canceller

adaptivenoisefilter

ADC

I2S

DAC

I2S

i2s clock generatorCENS 90200

Transmit path

Receive path

Figure 1: Block Diagram

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1. Characteristics / Specifications Power Characteristics (Vdd = 3.0 to 3.6 V, Ta = –40 to +85°C)

Parameter Symbol Condition Min Typ Max Unit

Power Supply Voltage Vdd 3,0 3,3 3,6 V Power Supply Current Idd Echo and Noise suppression on,

Vdd = 3.3 V,

fclk =16,9344MHz, fs = 11,025 kHz: Codecs on 43 50 mA Codecs power down 36 41 mA fclk =12,288MHz, fs = 8,0 kHz: Codecs on 34 40 mA Codecs power down 27 32 mA

Digital Interface Characteristics (Vdd = 3.0 to 3.6 V, Ta = –40 to +85°C)

Parameter Symbol Condition Min Typ Max Unit

High Level Digital Output Voltage VOHigh IOHigh = 0.4 mA Vdd-0.7 Vdd V Low Level Digital Output Voltage VOlow IOLow = -0.4 mA 0 0,2 0,4 V Output Leakage Current IO 30 µA Output Load (digital) RDL

CDL 1

20 kOhm

pF Input Voltage (Schmitt trigger char.) Positive-going threshold Negative-going threshold

VIHigh

VIlow

0,8

2,0

V V

Input Leakage Current IIHigh

IIlow VIn = Vdd

VIn = 0 V 10

-10 30

-30 60

-60 µA µA

System delay: Transmit path Receive Path

@ fs = 11,025 kHz @ fs = 8,0 kHz @ fs = 11,025 kHz @ fs = 8,0 kHz

22 31 0,18 0,25

ms ms ms ms

Analogue Interface Characteristics (Vdd = 3.0 to 3.6 V, Ta = –40 to +85°C)

Parameter Symbol Condition Min Typ Max Unit

Output Voltage Level (peak to peak) VOut 2,0 V Output Load (analogue, with coupling C) RAL 2,0 kOhmInput Voltage Level (peak to peak) VIn 2,0 V System delay: Transmit path Receive Path

@ fs = 11,025 kHz @ fs = 8,0 kHz @ fs = 11,025 kHz @ fs = 8,0 kHz

24 33 1,54 2,13

ms ms ms ms

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Absolute Maximum Ratings Parameter Symbol Condition Rating Unit

Power Supply Voltage Vdd -0.3 to +3.6 V Digital Input Voltage VDIN -0.3 to 5.0+0.25 V Digital Output Voltage VDOUT -0.3 to DVdd+0.3 V Analogue Input Voltage (peak to peak)

VAIN -0.3 to CVdd_a V

Analogue Output Voltage VAOUT -0.3 to 2.0 V Storage Temperature TSTG -40 to +125 °C Recommended Operating Conditions Parameter Symbol Condition Min Typ Max Unit

Power Supply Voltage Vdd 3,0 3,3 3,6 V Operating Temperature Tdigital -40 +25 +85 °C Operating Temperature Tanalogue -40 +25 +85 °C Digital Input Rise Time tInr For all digital inputs 10 ns Digital Input Fall Time tInf For all digital inputs 10 ns Master Clock Frequency fclk 12.288 16.9344 MHz Master Clock Duty Ratio Dclk 50 % With: fs = sampling frequency

2. Typical Connection Diagram Application Circuit I: Hands Free Communication

DAC

I2S

ADC

I2S

acousticecho

cancler

adaptivenoisefilter

ADC

I2S

DAC

I2S

i2s clock generatorCENS 90200

Transmitpath

Receivepath

Figure 2: Hands free communication

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CENS90200

Application Circuit II: Intelligent Codec

DAC

I2S

ADC

I2S

acousticecho

cancler

adaptivenoisefilter

ADC

I2S

DAC

I2S

i2s clock generator

DSPapplication

CENS 90200

Transmitpath

Receivepath

Figure 3: Intelligent codec

3. Acoustic Characteristics Echo Canceller Characteristics Parameter Symbol Condition Value Unit

Echo attenuation aE Comb spectra excitation(1) 40 dB

Echo attenuation aE Brown noise excitation(2) 30 dB

Echo path delay (max.) τmax fs = 11,025 kHz 92 ms Echo path delay (max.) τmax fs = 8,000 kHz 128 ms (1) This measurement uses comb spectra as excitation. The transmit (tx) and receive (rx) path signals

are represented by a comb spectra each. The measurement set-up is depicted in Figure 4. Figure 5 shows the rx path and tx path signal before and Figure 6 the two signals after echo cancellation. The black line represents the tx path signal (microphone input) which is a superposition of the delayed receive path signal and the signal generated by a speaker. The grey line represents the rx path signal which is to be suppressed by the echo canceller. It can clearly be seen, that the CENS90200 performs full duplex echo cancelling: Components of the rx path signal in the tx path signal are suppressed by over 40 dB by the echo canceller, and components of the tx path signal which are not present in the rx path signal are not suppressed.

CENS90200

Delay

τ=

123456

Noise filter

Echo cancler

Tx path Rx path

“Speaker“

Figure 4: Set-up for the echo cancellation measurement

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Microphone signal

Receive path signal

Figure 5: Receive and transmit path signal before echo cancellation for comb signal excitation

Microphone signal

Receive path signal

Figure 6: Receive and transmit path signal after echo cancellation for comb signal excitation

(2) Figure 7 shows the echo attenuation as function of the echo path delay time for brown noise

excitation.

0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 02 0

2 2

2 4

2 6

2 8

3 0

3 2

0 2 0 4 0 6 0 8 0 1 0 02 02 22 42 62 83 03 2

0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 02 02 22 42 62 83 03 2

fs = 8,0 kHz

fs = 11,025 kHz

Delay [samples]

Delay [ms]

Delay [ms]

Echo

Atte

nuat

ion

[dB]

Figure 7: Echo attenuation versus echo path delay time for brown noise excitation

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Noise Canceller Characteristics Parameter Symbol Condition Min Typ Max Unit

Noise attenuation aN White noise, voice band, suppression level 7

20 dB

Figure 8 shows the suppression of amplitude modulated white noise for different suppression levels.

0,1 1 10-35

-30

-25

-20

-15

-10

-5

0

Typical range forvoice modulation

Modulation frequency [Hz]

Aten

uatio

n [d

B] Suppression level

level 1 level 3 level 5 level 7 level 8

Figure 8: Suppression of amplitude modulated white noise

Frequency Response Figure 9 shows the frequency response of the CENS 90200.

-80

-70

-60

-50

-40

-30

-20

-10

0

0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1

Frequency [normalized to fs]

Am

plitu

de [d

B]

Figure 9: Frequency response, normalised to the sampling rate fs

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4. Functional Description Figure 10 shows a detailed block diagram of the CENS90200.

DAC

(cod

ec t

x)

ADC

(cod

ec r

x)

I2 S r

ecei

ver

(righ

t ch

anne

l)

acou

stic

echo

canc

ler

adap

tive

nois

efil

ter

ADC

(cod

ec t

x)

code

crx

i2s

cloc

kge

nera

tors

I2 S r

ecei

ver

(left

chan

nel)

I2 S t

rans

mitte

r(le

ft ch

anne

l)

I2 S t

rans

mitte

r(ri

ght

chan

nel)

DAC

(cod

ec r

x)

code

ctx

clkX2clkX1/rst

N[2:0]

E_on

E_act

N_on

Gws

Gsclk

Gmclk

DGnd[1:5]DVdd[1:5]

S_tx

S_rx

c_pwd

Vrefl_rxVrefh_rxVrefout_rx

CGnd_a

aout

_rx

ain_

txai

nfb_

txao

ut_t

x

ain_

rxai

nfb_

rx

Vrefl_txVrefh_txVrefout_tx

Osc

lkO

ws

Osd

ata

Iscl

kIw

sIs

data

Iscl

kIw

sIs

data

Osc

lkO

ws

Osd

ata

Anal

og In

/Out

puts

Dig

ital I

n/O

utpu

ts

Pow

er S

uppl

y

CVdd_dCGnd_d

CVdd_a

Transmit path Receive path

Figure 10: Detailed block diagram of the CENS90200

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4.1 General

Clock - clkX1, clkX2 Pin 9 and 8, input and output Function:

Interface of the crystal oscillator circuit. clkX1 is the input, clkX2 the output of the feedback amplifier. An external oscillator can also be used. Figure 11 shows a typical connection diagram for the oscillator circuit. In both circuits the signal at clkX1 is the digital system clock of the CENS90200. The frequency fclk of the system clock should be equal to 1536•fs, with fs being the desired sample frequency of the codecs. fclk should be between 12.288MHz and 16.9344 MHz, which is equivalent to a sampling frequency of the codecs between 8 kHz and 11,025 kHz.

clkX1

clkX2

CENS90200

clkX1

clkX2

CENS90200

R1

C

C

external clock source internal oscillator circuit

R1: 1 M OhmR2: 4.7K OhmC: 20-100pF

DGnd

DGndR2

Figure 11: Typical connection diagram of the oscillator circuit

Reset - /rst Pin 51, input Function:

Low active digital system reset. Should be 0 until power supply and clock oscillator circuit have stabilised and 1 during normal operation. A typical reset circuit for the CENS90200 is given in Figure 12.

CENS90200

/rst

Reset

DGnd

C

Recommended configuration:R1 = 560KOhmR2 = 33KOhmC = 0,22µF

R1

DGnd

DVdd

R2

Figure 12: Typical reset circuit for the CENS90200 4.2 Power supply

Digital power supply – DVdd, DGnd Pins 6, 23, 27, 32, 54, 58 (+3,3V) and pins 7, 22, 26, 31, 55, 59 (Ground) Function:

These pins supply the digital part of the CENS90200 with power. They must be supported by sets of capacitors of 10µF and 0,1µF. Use at least two sets of capacitors, one set for Vdd2 and Vdd4 and another set for the remaining Vdd pins.

Codec power supply, digital part – CVdd_d, CGnd_d Pin 49 (+3,3V) and pin 50 (Ground)

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Function: These pins supply the digital part of the integrated codec of the CENS90200 with power. They should be supported by two capacitors of 10µF and 0,1µF, which are placed as closely as possible to the pins. These pins of the digital part of the codec should be connected to the digital power supply for the rest of the CENS.

Codec power supply, analogue part – CVdd_a, CGnd_a Pin 41 (+3,3V) and pin 40 (Ground) Function:

These pins supply the analogue part of the integrated codec of the CENS90200 with power. They must be supported by two capacitors of 10µF and 0,1µF, which are placed as closely as possible to the pins.

Reference voltage for the codec – Vrefh, Vrefl Pins 37, 44 and 38, 43 Function:

These pins provide the power for the reference voltage of the codec. Vrefh and Vrefl should be connected to the analogue power supply CVdd_a and CGnd_a. Each Vrefh pin should be supported by two capacitors of 10µF and 0,1µF to Vrefl. The capacitors should be placed to the pins as closely as possible.

Note: Connect Vrefh to CVdd_a via a 0,1 mH inductor to protect the voltage reference from power

surges in the analogue part of the codec. Connect CVdd_a to DVdd via a 0,1 mH inductor to protect the analogue part from power surges

in the digital part. It is also recommended to keep CGnd_a separate from CGnd_d and connect them only at one point. Vrefl can be kept together with CGnd_a. The recommended power supply scheme is shown in Figure 13.

Figure 13: Recommended power supply scheme

4.3 Parameter Selection

Input selection of receive and transmit path – S_rx, S_tx Pins 57 and 60, input Function:

These pins select the type of input (analogue or I²S) for the receive and transmit path, see also Figure 10.

DVdd

DGnd

CVdd_d

CGnd_d

CVdd_a

CGnd_a

Vrefh_tx Vrefh_rx

Vrefl_rxVrefl_tx

L1

DVdd2DVdd4

DGnd2DGnd4

DVdd1DVdd..

DGnd1DGnd..

...L1 L1

C1: 0.1µFC2: 10 µFL1: 0.1mH

digital groundconnected to analogground at one point

only

With: = Digital ground = analog ground = supply voltage

+

C2C1

+

C2C1

+

C2C1

+

C2C1

+

C2C1

+C2C1

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CENS90200

Input source of S_rx

S_tx receive path transmit path

Description

0 0 analogue analogue internal codec used 0 1 analogue I²S "mixed mode" 1 0 I²S analogue "mixed mode" 1 1 I²S I²S I²S used, codec can be powered down, unless

analogue output is desired Notes:

• = S_rx and S_tx should not be changed after /rst is released. Doing so might result in lost samples and/or erroneous operation of the CENS90200 for a short period of time.

• = As soon as a I2S interface is used, the CENS90200 should either be operated in master mode or, if operated in slave mode, the clock of the external master must be very stable.

• = In "mixed mode" the internal I²S clock generators of the CENS90200 must be used for the I²S receiver as well as the I²S transmitter.

• = A typical application of the slave mode would be several CENS90200 operating in parallel with one of them as master.

Echo canceller – E_on, E_act Pins 29 and 56, input Function:

Echo on and Echo active. E_on switches the acoustic echo cancellation on (E_on = 1) or off (E_on = 0). Using E_act, one can deactivate the automatic adaptation of the echo canceller (E_act = 0). However, this is a feature for very specialized applications only. During normal operation E_act should be connected to E_on.

Echo on Echo active Description 1 1 normal operation: echo cancelling enabled * 0 0 normal operation: echo cancelling disabled * 1 0 special applications only: echo cancelling enabled, adaptation disabled 0 1 echo cancelling disabled

* recommended standard operating mode

Noise filter – N_on, N[0:2] Pins 24, 18, 19, 21, input Function:

Pin N_on switches the Noise filter on and off. N_on = 1: adaptive noise filter enabled, N_on = 0: adaptive noise filter disabled. Pins N[0] to N[2] set the level of the adaptive noise filter as follows:

N[2] N[1] N[0] Description 0 0 0 Filter level 1 (weakest) 0 0 1 Filter level 2 0 1 0 Filter level 3 0 1 1 Filter level 4 1 0 0 Filter level 5 1 0 1 Filter level 6 1 1 0 Filter level 7 1 1 1 Filter level 8 (strongest)

Codec power down - c_pwd Pin 53, input Function: Used to “power down“ the codecs of the transmit and receive path. c_pwd = 0: codecs enabled, c_pwd = 1: codecs disabled and in power down mode.

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4.4 Digital Interfaces

I²S Input

Input serial bit clock - Isclk Pin 03, input Function:

I²S input serial bit clock.

Input word select - Iws Pin 05, input Function:

The word select indicates the channel being transmitted: • = Iws=0: left channel, this channel contains the input signal of the receive path • = Iws=1: right channel, this channel contains the input signal of the transmit path

Iws should have the following properties: • = Iws should not be changed during the rising edge of Isclk • = fIws = fs • = fIws ≤ fclk / 1536

With: fIws = frequency of Iws, fs = sample frequency, fclk = system clock frequency

Input serial data - Isdata Pin 62, input Function:

Receives the serial audio data and is read in with the rising edge of Isclk. Isdata should contain at least 14 relevant bits of linear coded 2'complement's PCM sample data per channel. There is no restriction to the number of bits belonging to one sample. (This can be defined by the length of the word select.) The CENS90200 automatically processes the 14 most significant bits only. Figure 14 shows an example for the I2S input timing for a word length of 16 bit. Note: If the CENS90200 is I2s master, the word length is set to 32 bit per channel, as shown in

Figure 17.

D13(L)

D12(L)

'*'(R)

Isclk

Iws

'*'(R)Isdata D13

(R)D12(R)

D0(L)

D1(L)

'*'(L)

'*'(L)

D13(L)

D12(L)

D0(R)

D1(R)

'*'(R)

'*'(R)

302928 3103130 1 151413 1612 17 0 1

left channel data right channel dataD[13:0] : Sample data, MSB downto LSB'*' : "Don't care", bit is ignored by the CENS

Figure 14: Example of I²S input timing with 32 Isclk cycles per Iws period

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CENS90200

I²S Output

Output serial bit clock - Osclk Pin 15, input Function:

I²S output serial bit clock.

Output word select - Ows Pin 16, input Function:

The word select indicates the channel being transmitted: • = Ows=0: left channel, this channel contains the output signal of the receive path • = Ows=1: right channel, this channel contains the output signal of the transmit path

Ows should have the following properties: • = Ows should not be changed during the rising edge of Osclk • = fOws = fs • = fOws ≤ fclk / 1536

With: fOws = frequency of Ows, fs = sample frequency, fclk = system clock frequency

Output serial data - Osdata Pin 17, output Function:

Transmits the serial audio data and changes on the falling edge of Osclk. Osdata contains in each channel 16 relevant bits of linear coded 2'complement's PCM sample data. There is no restriction to the number of bits belonging to one sample. (This can be defined by the length of the word select.) If less than 16 bits per sample are requested, the CENS90200 automatically transmits only the most significant bits. If more than 16 Bits are requested, the surplus bits are set to zero. Figure 15 shows an example for the I2S output timing for a word length of 16 bit. Note: If the CENS90200 is I2s master, the word length is set to 32 bit per channel, as shown in

Figure 17.

D15(L)

D14(L)

D0(R)

Osclk

Ows

D1(R)Osdata D15

(R)D14(R)

D2(L)

D3(L)

D0(L)

D1(L)

D15(L)

D14(L)

D2(R)

D3(R)

D0(R)

D1(R)

302928 3103130 1 151413 1612 17 0 1

left channel data right channel dataD[15:0] : Sample data, MSB downto LSB

Figure 15: Example of I²S output timing with 32 Osclk cycles per Ows period

Note: The I²S input and I²S output operate independently of each other. However, in order to avoid the loss of samples, fIws must be exactly equal to fOws. In practice this can only be achieved by deriving both signals from a common source. But this does not imply that Iws and Ows need to be in any phase relationship which each other.

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CENS90200

I²S Clock Generator

Generated master clock - Gmclk Pin 63, output Function:

Delivers the master clock generated by the CENS90200 for usage by external codecs. This clock is not required by any I²S interface. The frequency of the generated master clock is:

fGmclk = 256 • fs = fclk / 6

With: fGmclk = generated master clock frequency, fs = sample frequency, fclk = system clock

Generated serial bit clock - Gsclk Pin 12, output Function:

Delivers the generated bit clock:

fGsclk = 64 • fs = fclk / 24 See Figure 16 for the relationship between Gmclk and Gsclk.

Generated word select - Gws Pin 14, output Function:

Delivers the generated word select:

fGws = fs = fclk / 1536 See Figure 17 for the relationship between Gsclk and Gws.

0 1 2 3

Gsclk

Gmclk 0 1 2 3

Figure 16: Relationship between Gmclk and Gsclk

Gws

Gsclk 0 163 313062 32 33 0 16362

Figure 17: Relationship between Gsclk and Gws

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CENS90200

4.5 Analogue Interface The CENS90200 has two integrated codecs, one for the receive and one for the transmit path. Since both codecs are identical, there is no distinction made between receive (_rx) and transmit (_tx) path in the functional description. The codecs operate with a sample frequency of fs = fclk / 1536.

Analogue input - ain Pins 39 and 42, input Function:

ain are the input pins of the receive and transmit path for analogue signals.

Analogue input feed back – ainfb Pins 36 and 45, output Function:

ainfb is the respective feedback output of the input amplifiers of the receive and transmit path. A typical connection diagram is shown in Figure 18.

ainfbCENS90200

ainR2

R1analogueinput

C

Recommended configuration:R1 > 50KOhmR2 = 2*R1C = 1*10-5 / R2

e.g. R1=100kOhm, R2=200kOhm, C=50pF

R1

CGnd_a

Figure 18: Typical connection diagram for the analogue input

Analogue output – aout Pins 34 and 47, output Function:

aout are the analogue output pins of DAC of the receive and transmit path. A typical connection diagram is shown in Figure 19.

aout

CENS90200

C

analogueoutput

Recommended configuration:C = 1µFRL > 2kOhm+

RL

CGnd_a

Figure 19: Typical connection diagram for the analogue output

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Reference Output Voltage - Vrefout Pins 33, 48, output Function: Vrefout is the reference voltage output of the codecs in the receive and transmit path. A typical connection diagram is shown in Figure 20. Place C1 and C2 in the order shown, position them as close as possible to the vrefout pin.

Vrefout

CENS90200

C1 C2

CGnd_a

+

Recommended ValuesC1 = 100nFC2 = 10µF

Figure 20: Typical connection diagram for the reference voltage output

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4 Pin Description All digital inputs (di) refer to DVdd and DGnd levels. Driving a digital input to DVdd level will be interpreted as a logic one ('1'), driving it to DGnd as a zero ('0'). All digital inputs have Schmitt trigger characteristics and are 5V tolerant. General Name No. Type Description clkX1 p09 ai Oscillator input f = 1536•fs clkX2 p08 ao Oscillator feedback output /rst p51 di System reset (low active) Power Supply Name No. Type Description DVdd1 p06 pwr Vdd for the digital part (3.3V) DVdd2 p23 pwr " " DVdd3 p27 pwr " " DVdd4 p32 pwr " " DVdd5 p54 pwr " " DVdd6 p58 pwr " " DGnd1 p07 pwr Ground for the digital part DGnd2 p22 pwr " " DGnd3 P26 pwr " " DGnd4 P31 pwr " " DGnd5 p55 pwr " " DGnd6 p59 pwr " " CVdd_a P41 pwr Vdd for the analogue part of the integrated codec (3.3V) CGnd_a P40 pwr Ground for the analogue part of the integrated codec CVdd_d P49 pwr Vdd for the digital part of the integrated codec (3.3V) CGnd_d P50 pwr Ground for the digital part of the integrated codec Parameter Selection Name No. Type Description S_rx p57 di, d Select input for receive path (adc:0 I²S:1) S_tx p60 di, d Select input for transmit path (adc:0 I²S:1) E_on p29 di, u Echo cancellation on (on:1 off:0) E_act p56 di, u Echo active (active:1 inactive:0) N_on p24 di, u Noise filter on (on:1 off:0) N[0] p18 di, u Noise filter level, least significant bit N[1] p19 di, u Noise filter level N[2] p21 di, u Noise filter level, most significant bit C_pwd p53 di, d Power down for codecs in transmit and receive path (DAC on:0 DAC off:1) Digital Interfaces Name No. Type Description

I²S Output Osclk p15 di, d Output serial bit clock Ows p16 di, d Output word select f = fs Osdata p17 do Output serial data

I²S Input Isclk p03 di, d Input serial bit clock Iws p05 di, d Input word select f = fs Isdata p62 di, d Input serial data

I²S Clock Generator Gmclk p63 do Master Clock f = 256•fs Gsclk p12 do Serial bit clock f = 64•fs Gws p14 do Word select f = fs

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Analogue Interface (Codecs) Name No. Type Description

Codec receive path ain_rx p39 ai ADC analogue input ainfb_rx p36 ao ADC input amplifier feedback output aout_rx p34 ao DAC analogue output Vrefout_rx p33 ao ADC and DAC reference voltage output Vrefh_rx p37 pwr Reference power Vdd (3.3V) Vrefl_rx p38 pwr Reference power Vss

Codec transmit path ain_tx p42 ai ADC analogue input ainfb_tx p45 ao ADC input amplifier feedback output aout_tx p47 ao DAC analogue output Vrefout_tx p48 ao ADC and DAC reference voltage output Vrefh_tx p44 pwr Reference power Vdd (3.3V) Vrefl_tx p43 pwr Reference power Vss Sprectrum Interface (see Appendix I) Name No. Type Description Ssclk p64 do Spectrum serial bit clock, fSsclk = fclk / 2 Sfsync p01 do Spectrum frame sync Ssdata p02 do Spectrum serial data Digital Testpins (internally connected) Name No. Type Description i.c. p25 di, d must be connected to DGnd i.c. p20 di, u i.c. p10 di, u i.c. p11 di, u

should be connected to DVdd should be connected to DVdd should be connected to DVdd

i.c. p04 di, d must be connected to DGnd i.c. p13 do leave open Pins not connected n.c. p28, 30, 35, 46, 52, 61 Abbreviations ai analogue input pin ADC analogue-to-digital converter ao analogue output pin DAC digital-to-analogue converter di digital input pin u internally pulled up to DVdd d internally pulled down to DGnd do digital output pin fs sample frequency f frequency i.c. internally connected n.c. not connected pwr power pin

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5 Pin Assignment Figure 21 shows the pin assignment of the CENS90200.

Power pins 00 Codec pins

DVdd4

DGnd4

n.c.

E_on

n.c.

DVdd3

DGnd3

i.c. (connect to DGnd)

N_on

DVdd2

DGnd2

N[2]

i.c. (connect to DVdd)

N[1]

N[0]

Osdata

48 47 46 45 44 43 42 41 40 39 37 36 35 34

1 2 3 5 876 10 119 12 13 14 15

33

16

31

32

29

26

27

28

25

23

24

21

18

19

20

17

51

50

49

52

55

53

56

58

57

60

63

62

61

64

38

4

30

22

54

59

CVdd_d

CGnd_d

/rst

n.c.

c_pwd

DVdd5

DGnd5

E_act

S_rx

DVdd6

DGnd6

S_tx

n.c.

Isdata

Gmclk

Ssclk

Sfsy

nc

Ssda

ta

Iscl

k

i.c. (

conn

ect t

o D

Gnd

)

Iws

DVd

d1

DG

nd1

clkX

2

clkX

1

i.c. (

conn

ect t

o D

Vdd)

i.c. (

conn

ect t

o D

Vdd)

Gsc

lk

i.c.(l

eave

ope

n)

Gw

s

Osc

lk

Ow

s

i.c.: internally connectedn.c.: not connected

Vref

out_

tx

aout

_tx

n.c.

ainf

b_tx

Vref

h_tx

Vref

l_tx

ain_

tx

CVd

d_a

CG

nd_a

ain_

rx

Vref

l_rx

Vref

h_rx

ainf

b_rx

n.c.

aout

_rx

Vref

out_

rx

CENS90200(top view)

Figure 21: Pin assignment of the CENS90200

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DS90200 V 1.2 19

CENS90200

6 Physical Dimensions Figure 22 shows the package dimension of the 64-LQFP-1414 package of the CENS90200.

Figure 22: Package Dimensions

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DS90200 V 1.2 20

CENS90200

Appendix I –Spectrum Interface The CENS902000 features an additional digital serial output, which carries the spectrum of the output signal of the transmit path. The block diagram is given in Figure 23.

DAC

I2S

ADC

I2S

acousticecho

canceller

adaptivenoisefilter

ADC

I2S

DAC

I2S

i2s clock generators

Transmittpath

Receivepath

Spectrum

Figure 23: Block diagram with Spectrum output

A new spectrum is transmitted after every 128 incoming input samples. Note: No spectra are sent when no signal is present at the I2S input and the input selection of the

CENS90200 is set to I2S input (S_rx=1 and/or S_tx=1). Format of the spectrum A spectrum consists of 129 complex values Hn with the corresponding frequencies Fn:

1280256

≤≤= nwithfnF sn

The Hn are given in polar coordinates, each consisting of a scaled radius srn and a scaled phase sφn. Both srn and sφn. are unsigned and 16 bit long.

),( nnn ssrH ϕ= The non scaled radius rn as defined by rn=√(ren

2+imn2) is coded into the scaled radius srn. It can be

obtained with the following equation:

�

�

�

==

≤≤=

12802

12714

nornforsr

nforsr

rn

n

n

The non scaled phase φn as defined by φn=arctan(imn/ren) is coded into the scaled phase sφn. It can be calculated as follows:

πϕϕ 152n

ns=

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DS90200 V 1.2 21

CENS90200

Example Spectrum with fs = 11025Hz:

Hn n srn [Hex] sφn [Hex]

Fn [Hz]

rn [Dec]

φn [Dec]

0 000F FFFF 0 7.5 (2-1/215)π 1 000F C000 43 3.75 1.5π 2 0001 8000 86.1 0.25 π

… … … … … … 127 F001 4000 5469.4 15360.25 0.5π 128 00FF 0 5512.5 127.5 0π

Physical Format of the Spectrum Each spectrum is transmitted as a sequence of 258 frames. Each frame is 16 bit long and contains either a scaled radius srn or a scaled phase sφn. The srn and sφn of a spectrum are packed into the sequence of frames according to Figure 24:

frame 0sr0

frame 1sphi0

frame 2sr1

frame 3sphi1

frame 256sr128

frame 257sphi128

frame 254sr127

frame 255sphi127

Figure 24: Frame sequence of a s single spectrum

Spectrum serial bit clock - Ssclk Pin 64, output Function:

Serial bit clock of the spectrum output. Ssclk is active all the time, even when no spectrum is sent. The serial bit clock is derived from the system clock as follows:

fSsclk = fclk / 2

All other signals of the spectrum output (Sfsync and Ssdata) only change during the rising edge of Sclk. Therefore they should be read with the falling edge of Sclk.

Spectrum frame sync - Sfsync Pin 1, output Function:

Indicates the start of a new frame. The MSB (D15) of every frame is preceded with a pulse on Sfsync which is one Ssclk cycle long. Sfsync stays '0' when no spectrum is transmitted as shown in Figure 25 and Figure 26.

Spectrum serial data - Ssdata Pin 2, output Function:

Contains the frame data as unsigned 16 bit long values. The sequence of transmission is MSB (D15) first and LSB (D0) last. The 258 frames are transmitted without interruption directly one after another. The end of a spectrum is indicated by a D0 bit, which is not accompanied by an Sfsync pulse, as shown in Figure 25.

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DS90200 V 1.2 22

CENS90200

Ssclk

Sfsync

Ssdata D15 D14 D1 D0

frame 0

D15 D14 D1 D0

frame 1

spectrum

... D0 D15 D1 D0

frame 257

...

frames 2 to 256

Figure 25: Timing diagram of the spectrum output

The total spectrum takes 1+258*16=4129 Ssclk cycles to transmit, which is equivalent to 8258 system clock cycles. The spectrum is repeated after 128 new incoming samples have been read.

spectrumframe 0 to 257

8258*TclkX1

128 incoming samples(nominally 128*1536*TclkX1)

spectrumframe 0 to 257

8258*TclkX1

128 incoming samples(nominally 128*1536*TclkX1)

TclkX1: period of one system clock cycle at pin clkX1

idleSpectrumframes

Sfsync

idle

Ssclk

Figure 26: Timing diagram of the spectrum output

Pin Description DSP Interface Name No. Type Description Ssclk p64 do Spectrum serial bit clock, fSsclk = fclk / 2 Sfsync p01 do Spectrum frame sync Ssdata p02 do Spectrum serial data

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CENS90200

Appendix II: Description of the CENS90200 Demo Board An demo board is available for the CENS90200. This board provides the full functionality of the CENS90200. A schematic of the board is given in Figure 27. Supply voltage range for the board is 6V to 12V.

Voltage Regulator

CENS 90200

JP A JP B

I2S Master/Slave

JP JP C D

Input select

Pin Head Connector

Top View

Figure 27: Schematic of the CENS90200 Evaluation Board

The pin header connector on the demo board is used to interface the board with the power supply, the I/O signals and to set the desired echo and noise parameters. The two pairs of jumpers on the demo board can be used to select the input for the receive and transmit path (JP input select) and to configure the I2S interface as master or slave (JP I2S M/S). The exact settings are given in Table 1 and Table 2.

Jumper A Jumper B Description open open CENS90200 is I2S Slave closed closed CENS90200 is I2S Master (fs = fclk / 1536; fGsclk = 64 * fs) open closed Do not use closed open Do not use

Table 1: Selection of I2S Master / Slave operation of the CENS90200

Description Jumper C open Transmit path: analogue input (S_tx = 0) closed Transmit path: I2S input (S_tx = 1) Jumper D open Receive path: analogue input (S_rx = 0) closed Receive path: I2S input (S_rx = 1)

Table 2: Selection of the input of the transmit and receive path The exact pin assignment for the pin header connector is given in Figure 28. Pins 21 to 30 can be jumpered to set echo and noise parameters. For easy use, an adaptor board is available from Cortologic, that fits on the pin header connector and provides dip switches for the echo and noise settings and has standard connectors for the power and analogue I/O signals. This adaptor board is not suitable for I/O signals in I2S format.

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DS90200 V 1.2 24

CENS90200

GND 30 Jp 29 Echo on/off (E_on, E_act) GND 28 Jp 27 Noise on/off (N_on) GND 26 Jp 25 Noise filter-strength bit 2 (N[2]) GND 24 Jp 23 Noise filter-strength bit 1 (N[1]) GND 22 Jp 21 Noise filter-strength bit 0 (N[0]) Reset (/rst)(1) 20 19 Codec power down (c_pwd) Output serial Data (Osdata) 18 17 Input serial data (Isdata) I/O word select (Iws, Ows) 16 15 Generated master clock (Gmclk) I/O serial bit clk (Isclk, Oslk) 14 13 Do not connect +3,3Vout 12 11 Analogue input transmit path (ain_tx) GND 10 9 Analogue output transmit path (aout_tx) GND 8 7 Analogue output receive path (aout_rx) GND 6 5 Analogue input receive path (ain_rx) + 6 to +12 V 4 3 Do not connect + 6 to +12 V 2 1 Do not connect (1) The reset is low active

Top View

Figure 28: Pin description

Figure 29 provides the physical dimensions of the evaluation board.

8,89 mm(0,35 Inch)

3,81 mm(0,15 Inch)

53,34 mm(2,1 Inch)

3,81 mm (0,15 Inch)

53,34 mm(2,1 Inch)

3,81 mm (0,15 Inch)

8,89 mm(0,35 Inch)

Hole diameter: 3,0 mm (0,118 Inch)

CENS 90200

Figure 29: Physical Dimensions

1. Revision History Version / Date Item Revision (see Datasheet for details) 1.0 / 27-11-2001 Initial release - 1.1 / 06-12-2001 Section 3 Fine tuning, Inclusion of Figs. 4-6, 1.2 / 15-12-2001 Section 4.4 Clarifying text for Figs. 14, 15, 27 and 28