Cell-Based IC Physical Design and Verification - Encounter Digital...
Transcript of Cell-Based IC Physical Design and Verification - Encounter Digital...
-
Cell-Based IC Physical Design and Verification - Encounter Digital Implementation
-
Class Schedule
• Day1
– Design Flow Over View
– Prepare Data
– Getting Started
– Importing Design
– Specify Floorplan
– Power Planning
– Placement
• Day2
– Synthesize Clock Tree
– Timing Analysis
– Trial Route
2
Power Analysis
SRoute
NanoRoute
Fill Filler
Output Data
Day3
DRC
LVS
extraction/nanosim
Foundation flow
-
Chapter1- SOC Encounter
3
Cell-Based Physical Design
– EDI 14.24
– EXT 10.13.065 (fire & Ice)
-
Cell-Based Design Flow
4
Logic synthesis
Place&Route
Gate-Level netlist
Post layout
Gate-Level netlist
GDS layout
always @ (posedge clk)
if (in1==1)
a=c+d
else
a=c-d
RTL code
Formal
Formal
LVS
RTL Simulation
Lint check
code coverage analysis
Gate level Simulation
Static Timing Analysis
Power Analysis
Gate level Simulation
Static Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level Simulation
Transistor-level STA
Power Analysis
Implenentation Verification
-
Cell Library
5
A1àO 0.1ns
A2àO 0.2ns
function NAND
symble
timing
layout
schematic
abstract
NOR
A1àO 0.1ns
A2àO 0.2ns
XOR INV FFADD
A1àO 0.1pw
A2àO 0.2pwpower A1àO 0.1pw
A2àO 0.2pw
-
SOC Encounter P&R flow
IO,P/G Placement
Specify floorplan
Amoeba Placement
Power Planning
Timing Analysis
Clock Tree Synthesis
Timing Analysis
Post-CTS Optimization
Power Analysis
IO constraints
SI Driven Route
Timing/SI Analysis
Output GDS,
Netlist
Pre-CTS Optimization
Netlist (verilog)
Timing constraints (sdc)
Post-Route Optimization
RC
dela
y d
ata
Op
timize ca
pa
bility
detail
rou
gh
hig
hlo
w
Clo
ck d
ata
detail
rou
gh
sdc d
efined
6
-
IO, P/G Placement
7
VDD
VSS
IOVDD IOVSS
I1
I2
I3
I4
O2
O1
O3
O4
Corner1 Corner2
Corner3 Corner4
-
Specify Floorplan
Hight
Width
8
-
Floorplan
9
VDD
VSS
IOVDD IOVSS
I1
I2
I3
I4
O2
O1
O3
O4
M2
M1 M3
-
Power Planning
10
VDD
VSS
-
Power Route
11
-
Add IO Filler
12
-
Placement
13
-
Clock Tree Synthesis
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
CLK
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
CLK
14
-
Routing
15
-
Prepare Data • Library
– Physical Library (LEF)
– Timing Library (LIB)
– Capacitance Table
– Celtic Library
• User Data
– Gate-Level netlist (verilog)
– SDC constraints
– IO constraint
– scan def
16
-
LEF Format -- Process Technology
17
Layers Design Rule Parasitic
POLY
Metal1
Metal2
Contact
Via1
Net width Net spacing Area Enclosure Wide metal slot Antenna Current density
Resistance Capacitance
-
LEF Format -- Process Technology : Layer define
18
Layer Metal1
TYPE ROUTING ;
WIDTH 0.28 ;
MAXWIDTH 8 ;
AREA 0.202 ;
SPACING 0.28 ;
SPACING 0.6 RANGE 10.0 10000.0 ;
PITCH 0.66 ;
DIRECTION VERTICAL ;
THICKNESS 0.26 ;
ANTENNACUMDIFFAREARATIO 5496 ;
RESISTANCE RPERSQ 1.0e-01 ;
CAPACITANCE CPERSQDIST 1.11e-04 ;
EDGECAPACITANCE 9.1e-05 ;
END Metal1
Wide metal
width
spacing
Wide metal spacing
-
LEF Format -- APR technology
• Site
• Routing pitch
• Default direction
• Via rule
19
-
LEF Format -- APR technology : SITE
The Placement site give the placement grid of a family of macros
20
a site a row
-
Row Based PR
21
VDD
VSS
VDD
VSS
-
LEF Format -- APR technology : routing pitch , default direction
22
metal2 routing pitch
metal1 routing pitch
Horizontal
routing
Vertical
routing
Metal1
Metal3
Metal5
Metal2
Metal4
Metal6
via
-
Grid Based Routing
23
metal2 grid
metal1 grid
-
LEF Format -- APR technology : Physical Macros
• Define physical data for – Standard cells
– I/O pads
– Memories
– other hard macros
• describe abstract shape – Size
– Class
– Pins
– Obstructions
24
-
LEF Format -- APR technology : Physical Macros cont.
25
MACRO XNOR CLASS CORE ; FOREIGN ADD1 0.0 0.0 ; ORIGEN 0.0 0.0 ; LEQ ADD ; SIZE 19.8 BY 6.4 ; SYMMETRY x y ; SITE coresite ; PIN A DIRECTION INPUT ; PORT LAYER Metal1 ; RECT 19.2 8.2 19.5 10.3 ; ……
END END A PIN B …..
END B OBS ……
END END ADD1
AB
Y
VSS
VDD
A
B
-
Layout vs. Abstraction
26
AB
Y
VSS
VDD
pdiff
ndiff
metal1
contact
nwell
poly
prboundary
AB
Y
VSS
VDD
A
B
Layout Abstraction
pin
blockage
prboundary
-
LIB Format
• Operating condition – slow, fast, typical
• Pin type – input/output/inout
– function
– data/clock
– capacitance
• Path delay/transition
• Internal power
• Timing constraint – setup, hold, mpwh, mpwl, recovery,
removal …
CLK
D Q
QN
type: input
setup/hold time
internal power
CLKàQ delay
CLKàQN delay
type: clock
mpwh/mpwl
max transition
internal power
function: ff
footprint
area
leakage power
type: output
max_cap/max_fanout
internal power
output transition
type: output
max_cap/max_fanout
internal power
output transition
27
-
Capacitance Table
• CapTable
– cap_value = f(configuration, width, spacing)
• CapModel
– CapTable contains the area, fringe and lateral coupling capacitance coefficients organized per layer
28
Fc A L2
Fu Fd
L1 Metal1 Metal1
Metal2 Metal2
-
CeltIC Library cdB model
• Noise Model
29
-
QRC layermap
30
#lefdef lef icecaps layer_ict
layer METAL1 icecaps METAL_1
layer METAL2 icecaps METAL_2
layer METAL3 icecaps METAL_3
layer VIA12 icecaps VIA_1
layer VIA23 icecaps VIA_2
extraction_setup \
-technology_layer_map \
METAL1 METAL_1\
METAL2 METAL_2\
METAL3 METAL_3\
VIA12 VIA_1\
VIA23 VIA_2\
Integrated QRC
Stand Alone QRC
-
gate-level netlist
• If designing a chip , IO pads should be added before the netlist is imported.
• Remove “assign” statement before APR. – The assign statement can be removed in Encounter
Encounter> setDoAssign -buffer buf_name on
• Make sure that there is no “ *cell*” net name in the netlist. – Use the synthesis commands (DC) below to remove “*cell*” cell name
dc_shell> define_name_rules name_rule –map {{\\*cell\\* cell”}} dc_shell> change_names –hierarchy –rules name_rule
• Ensure the names of all instantiated cell types are unique unix> uniquifyNetlist –top TOP output_netlist input_netlist
31
A B
assign B=A ;
-
Static Timing Analysis
32
Main steps of STA
Break the design into sets of timing paths
Calculate the delay of each path
Check all path delays to see if the given timing constraints are met
STA paths
QSET
CLR
D
RN
QSET
CLR
DPATH
PATHPATH
CLK
PO
ENCLK PATH
RESET
PI POPATH
PATH
-
Static Timing Analysis
33
Q
QSET
CLR
D
Q
QSET
CLR
DTn1
Tc1 Tc2 Tc3Tn2
Tn3Tn4
-
Static Timing Analysis
34
Req
Ceq
I1 I2 Dtransition(I1)
Dcell(I2)
Dc Dtransition(I2)
I3
Cell Delay Dcell(I2) = f(Dtransition(I1), Ceq)
Transition Delay Dtransistion(I2) = g(Dtransition(I1), Ceq)
Vin Vout
Output
Capacitance
Input Transition
0 0.5 1
0.1
0.2
0.123 0.234 0.456
0.222 0.432 0.801
Cell Delay
-
Static Timing Analysis setup time and hold time
35
QDQD
clk1 clk2
DFF1 DFF2PATH
hold
time
clk1
clk2setup
time
D
-
SDC constraint basic
create_clock
set_clock_latency
set_clock_uncertainty
36
set_input_delay
set_output_delay
set_drive
set_load
latency
CK
CK
latency uncertainty
input drive
input delay
output load
output delay
current design
create
clock
-
Basic sdc file
create_clock [get_ports {CLK}] -name CLK -period 8 -waveform {0 4}
set_clock_latency 2 [get_clocks {CLK}]
set_clock_uncertainty 1 [get_clocks {CLK}]
set_input_delay 2 [remove_from_collection [all_inputs] [get_ports CLK]]
set_output_delay 2 –clock CLK [all_outputs]
set_drive 0.1 [all_inputs]
set_load -pin_load 20 [all_outputs]
-
SDC constraint others
38
set_generated_clock
set_clock_transition
set_input_transition
set_propagate_clock
set_case_analysis
set_clock_gating_check
set_data_check
set_disable_timing
set_dont_touch
set_dont_use
…..
set_min_delay
set_max_delay
set_false_path
set_multicycle_path
set_max_capacitance
set_max_fanout
set_max_transition
set_max_time_borrow
set_min_pulse_width
…..
-
IO constraint
39
(globals
version = 3
io_order = default
)
(iopad
(top
(inst name=“P_CLK”)
(inst name=“P_HALT”)
)
(right
(inst name =“P_VDD1” cell=“PVDD1DGZ”)
(inst name =“P_VSS1” cell=“PVSS1DGZ”)
)
(left
(inst name=“P_X1”)
(inst name=“P_X2”)
)
(bottom
(inst name=“P_IOVDD1” cell=“PVDD2DGZ”)
(inst name=“P_IOVSS1” cell=“PVSS2DGZ”)
)
(topright
(inst name=“CORNER0” cell=“PCORNER”)
)
(topright/topleft/bottomrignt/bottomleft
……...
)
)
bottom
top
right
left
P_CLK
P_X1
P_HALT
P_X2
P_IOVDD1
P_IOVSS1
P_VDD1
P_VSS1
CORNER0
CORNER3CORNER2
CORNER1
toprighttoplef
bottomlef bottomright
-
IO constraint
• globals
40
(globals
version = 3
io_order = default/clockwise/counterclockwise
space=5
)
(iopad
……
)
(iopin
……
)
counterclockwise
space
-
IO constraint
• side/corner
41
(iopad/iopin
( top / right / left / bottom /
topright / topleft /bottomright / bottomleft/
(inst name=“inst1” ……)
(inst name=“inst2” ……)
(inst name=“inst3” ……)
(inst name=“inst4” ……)
)
)
-
IO constraint
• iopad
42
(iopad
(right
(locals
space = 5
)
(inst name=“P_VDD1”
skip=5
offset= 300
orientation=R90
cell=“PVDD1DGZ”
)
(keepclear begin=200 end=400)
(inst name=“P_VSS1” cell=“PVSS1DGZ”)
(endspace gap =5)
)
)
P_CLK
P_X1
P_X2
P_IOVDD1
P_IOVSS1
P_VDD1
P_VSS1
CORNER0
CORNER3CORNER2
CORNER1
skip offset
endspace gap
-
Orientation
43
R0
MX MY
R180
MX90
R90 R270
MY90
-
IO constraint
• iopin
44
(iopin
(top/right/left/bottom
(locals
io_order=default/clockwise/counterclockwise
space = 5
)
(pin name=“pin_x”
layer=2
width=0.14
depth=0.5
skip=5
)
(pin name =……)
)
)
pin_x
width
depth
-
IO constraint version2
Version: 2
MicronPerUserUnit: value
Pin: pinName side [layer width [depth]]
Pad: padInstanceName side|corner [cellName]
Offset: length
Skip: length
Spacing: length
Keepclear: side offset1 offset2
Orient: orientation
45
Create an I/O assignment file manualy using the following template:
-
IO constraint version2 cont.
S
N
EW
PAD_CLK
PAD_X1
PAD_HALT
PAD_X2
PAD_IOVDD1
PAD_IOVSS1
PAD_VDD1
PAD_VSS1
CORNER0
CORNER3CORNER2
CORNER1
46
Version: 2
Pad: CORNER0 NW PCORNER
Pad: PAD_CLK N
Pad: PAD_HALT N
Pad: CORNER1 NE PCORNER
Pad: PAD_X1 W
Pad: PAD_X2 W
Pad: CORNER2 SW PCORNER
Pad: PAD_IOVDD1 S PVDD2DGZ
Pad: PAD_IOVSS1 S PVSS2DGZ
Pad: CORNER3 SE PCORNER
Pad: PAD_VDD1 E PVDD1DGZ
Pad: PAD_VSS1 E PVSS2DGZ
-
SSO Consideration
• SSO – Simultaneously Switch Outputs
• SSN – The noise produced by SSO buffers
• DI – maximum number of copies of an I/O cell switching from high to low
simultaneously without making the voltage on the quiet output “0” higher than a threshold value “Vil” when a single ground cell is applied.
• DF – Drive Factor, DF = 1/DI
• SDF – Sum of Drive Factor
47
Ground
pad
Output
pad
Ground
bounce
1 DI < Vil
DF 1 < Vil
-
SSO Consideration cont.
• Parameter of DF
– operating condition
– package inductance
– slew-rate control IO
– IO type with different drive strength
• In SSO case
– Required number of ground pads = SDF
– Required number of power pads = SDF/1.1
• Non SSO case (suggest)
– Required number of ground pads = SDF/1.5
– Required number of power pads = SDF/1.6
48
-
SDF Example
• If a design has 20 PDB02DGZ(2mA), 10 PDD16DGZ(16mA). then
• SDF = 20 x 0.02 + 10 x 0.3 = 3.4
• In SSO case,
– number of VSS pad = 3.4 4
– number of VDD pad = 3.4/1.1 = 3.09 4
49
IO Type 2mA 4mA 8mA 12mA 16mA 24mA
DF Value 0.02 0.03 0.09 0.18 0.3 0.56
-
Tips to Reduce the Power/Ground Bounce
• Don’t use stronger output buffers than are necessary
• Use slew-rate controlled outputs cells
• Insert as many power and ground cells for I/O as possible.
• Place power pad near the middle of the output pads
• Place noise sensitive I/O pads away from SSO I/Os
• Consider using double bonding on the same power pad to reduce inductance
50
-
Cadence On-Line document : cdnshelp
51
/usr/cad/cadence/EDI/cur/tools/bin/cdnshelp
-
Getting Started
• Source the encounter environment: unix% source /usr/cad/cadence/CIC/edi.cshrc
• Invoke soc encounter : unix% encounter
• Do not run in background mode. Because the terminal become the interface of command input while running soc encounter.
• The Encounter reads the following initialization files:
– enc.tcl
• Log file:
– encounter.log*
– encounter.cmd*
52
-
GUI
53
display control
design display area
auto query
cursor coordinates
tool widgets
name of
selected
object
menus design views
-
Tool Wedgits
54
Design Import
Zoom
In/Out
Fit
Zoom
Previous
Redraw
hierarchy
Down/Up
Undo/Redo
query
design
density
design
browser
Clear
all
rulers
Summary
Report
violation
browser
highlight
selected
select
move
resize
reshape
cut
rectilinear
query
area
density
ruler
add blockage
edit wire
move wire
cut wire
stretch wire
add polygon
highlight
Selected
attribute
editor
point to point route
Clear
Violation
-
Design Views
55
FloorplanView
displays the hierarchical module and block guides,connection flight lines and floorplan objects
Amoeba View
display the outline of modules after placement
Physical View
display the detailed placements of cells, blocks.
-
Display Control
56
-
ALL Colors
-
Common Used Bindkeys
Key Action
q Edit attribute
f Fits display
z Zoom in
Z Zoom out
Arrows pans design area in the
direction of the arrow
Escape Cancel
K Removes all rulers
Key Action
space Select Next
e popup Edit
T editTrim
0-9 toggle layer[0-9] visibility
h/H hierarchy up/down
x clear Drc
N next via
58
Looking for more bindkey:
OptionsàSet Preference, Binding Key
-
Import Design
59
Import LEF in the order:
technology first
geometry lef for cell/block
antenna lef for cell/block
IO Assignment File:
get a IO assignment template: DesignàSaveàI/O File…
FileàDesign Import…
powerplan placement CTS routingfloorplanimport
-
MMMC Browser
60
FileàDesign Import
-
Traditional Timing Analysis
• One sdc file
– Fit all operation mode in one sdc file
• Max Timing Libraries
– worst-case conditions for setup-time analysis
• Min Timing Libraries
– best-case conditions for hold-time analysis
61
-
Why MMMC Case1
module A
module BCLK
62
Operation Mode1: moduleA runs on 100MHz moduleB not use
Operation Mode2: moduleA runs on 50MHz moduleB runs on 50MHz
-
Why MMMC Case2
• design is required to meet 3 operating corner
– Corner1: 1.1V , 0°C
– Corner2: 0.9V , 100°C
– Corner3: 1.1V , 100°C
63
-
Traditional Timing Analysis to MMMC
64
Max Library Sets
Active Analysis Viewset_analysis_view
-setup max_analysis_view
-hold min_analysis_view
SDC Max Delay Corner
Min Delay Corner
Min Library Sets
RC Corner
Max Analysis View Min Analysis View
Mode Corner
-
Multi-Mode Multi Corner expand view
65
Library Sets 1
Active Analysis Viewset_analysis_view
-setup V1 V2 V4 V5 V7 V8
-hold V3 V6 V9
SDC 1
Delay Corner 1
Delay Corner 2Library Sets 2
RC Corner 1
RC Corner 2
V1
ModeCorner
SDC 2
SDC 3
Delay Corner 3Library Sets 3
RC Corner 3
Analysis View V2 V3 V4 V5 V6 V7 V8 V9
-
Multi-Mode Multi Corner
66
Power Mode - each doamin@nominal
- one sdc
Constraint Mode - one sdc
Analysis View - one constraint mode
- one delay corner
Operating
Condition- PVT
Library Sets- group of librarys
-cdb librarys
Delay Corner - one(or two) libray set
- one RC corner
- one(or two) op cond.
RC Corner - Captable
- res/cap factor
- qx tech file
SDC- clock
- io timing
- case analysis
- false path
- multi-cycle path
……
Active Analysis Viewset_analysis_view
-setup views_for_setup_analysis
-hold views_for_hold_analysis
-
Global Net Connection
67
Powerà Connections Gloval Nets …
powerplan placement CTS routingfloorplanimport
VDD
1'b1
VSS
tie high net
INV inv1(.I(1’b1), .O(o));
-
Check Design
• checkDesign
– Checks for missing or inconsistent library and design data and writes the results to a text and HTML report.
– checkDesign checks the following data:
• I/Os • Netlist
• Physical library
• Timing library
• Power and ground pins
• Tie-high and tie-low pins
• Floorplan
• Placement
powerplan placement CTS routingfloorplanimport
-
Specify Floorplan
Hight
Width
69
FloorplanàSpecify Floorplan …
powerplan placement CTS routingfloorplanimport
-
Specify Floorplan-core utilization
70
core utilization = standard cell + macro cell
core area
powerplan placement CTS routingfloorplanimport
-
71
Floorplan Purposes
Develop early physical layout to ensure design objective can be
archived
Minimum area for low cost
Minimum congestion for design routable
Estimate parasitic for delay calculation
Analysis power for reliability
powerplan placement CTS routingfloorplanimport
-
72
Difference Floorplan Difference Performance
powerplan placement CTS routingfloorplanimport
-
Module Constraint
• Soft Guide
• Guide
• Region
• Fence
73
Fence Region
Guide Soft Guide
powerplan placement CTS routingfloorplanimport
-
Guide , Region, Fence
• Placement constraint
• Create guide for timing issue
• A critical path should not through two different modules
• The more region, the more complicated floorplanning
74
powerplan placement CTS routingfloorplanimport
-
Soft Module & Hard Macro
75
powerplan placement CTS routingfloorplanimport
-
Place Block
76
FloorplanàAutomatic FllorplanàPlan Design…
Automatic generate a quick, initial floorplan.
Move/Resize/Reshape floorplan object.
edit floorplan by functions in :
FloorplanàEdit Floorplan
powerplan placement CTS routingfloorplanimport
-
Block Placement
• Block place issue
– power issue
– noise issue
– route issue
77
powerplan placement CTS routingfloorplanimport
-
Tip for Memory Place
78
powerplan placement CTS routingfloorplanimport
-
Blockage
• Placement Blockage
– Hard
– Soft • The initial placement should not use the area, but later phases, such as
optimization of CTS can use the blockage area.
– Partial • The initial placement should not use more than maxDensity percentage
of the blockage area.
• Routing Blockage
– Blockage on given routing layers
79
powerplan placement CTS routingfloorplanimport
-
Add Halo To Block
• Prevent the placement of blocks and standard cells in order to reduce congestion around a block.
80
FloorplanàEdit FloorplanàEdit Halos…
powerplan placement CTS routingfloorplanimport
hot spot
halo
hard routehalo
metal2
power ring
-
Placement
81
PlaceàPlace Standard Cells …
powerplan placement CTS routingfloorplanimport
D
CLK
Q D
CLK
Q
D
CLK
Q
D
CLK
Q
D
CLK
Q
D
CLK
Q
clk
O
B
d2
d1
d3
-
Mode Setup -- placement
82
OptionsàSet ModeàMode Setup…
powerplan placement CTS routingfloorplanimport
-
Scan Chain
83
Z
A
B
C
11110000
11001100
10101010
00110000
A
B
C
Reg
Reg
Reg
Reg
Inputs outputs
hard to assign value hard to observe
A
B
C
Reg
Reg
Reg
Reg
scan_in
scan_out
Scan Flip-Flop
Q DI
TI 1
0
TO
Reg
TE
CK
QN Tester Cycles
Clock
Scan Enable
Measure PO’s
-
Specify Scan Chain
84
powerplan placement CTS routingfloorplanimport
with scan def
SCANCHAINS 1 ;
- scan1
+ START SIN
+ FLOATING
DCT_tposemem_Bisted_RF_2P_ADV64x16_BistCtrl_i0/S44/State_reg[2] ( IN SI ) ( OUT QN )
DCT_tposemem_Bisted_RF_2P_ADV64x16_BistCtrl_i0/S44/State_reg[1] ( IN SI ) ( OUT Q )
DCT_tposemem_Bisted_RF_2P_ADV64x16_BistCtrl_i0/S44/State_reg[3] ( IN SI ) ( OUT Q )
DCT_tposemem_Bisted_RF_2P_ADV64x16_BistCtrl_i0/S44/State_reg[0] ( IN SI ) ( OUT QN )
…………
+ ORDERED
DCT/tposemem_Bisted_RF2SH64x16_BistCtrl_i0_ST_MAL_i0_S17_reg ( IN SI ) ( OUT QN )
DFT_shared_out_mux_3 ( IN B ) ( OUT Y )
+ STOP SOUT
;
END SCANCHAINS
END DESIGN
scan_def DSI
CKSE
QD
SI
CKSE
Q
SIN
D
SI
CKSE
QD
SI
CKSE
Q
SOUT
ORDERED
FileàLoadàDEF…
-
Generate Scan Def
• Design Vision
– write_scan_def –o scan.def
• RTL compiler
– write_scandef > scan.def
85
-
Specify Scan Chain
• specifyScanChain
– ftname
• The design input/output pin name
– instPinName
• The design instance input/output pin name
• Specifies a scan chain in a design. The actual tracing of the scan chain is performed by the scanTrace or scanReorder command
• enables scanTrace trace through multiple input logic gates in scan path – setScanReorderMode -compLogic
86
encounter > specifyScanChain scanChainName
–start {ftname | instPinName}
– stop {ftname | instPinName}
powerplan placement CTS routingfloorplanimport
with specifyScanChain command
-
Scan Chain Reorder
87
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
SCAN IN SCAN OUT
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
SCAN IN SCAN OUT
powerplan placement CTS routingfloorplanimport
-
Add Tiehi/Tielo cell
88
Tiehi/Tielo cell connect tiehi/tielo net to supply voltage or
ground with resister
Tiehi/Tielo cell is added for ESD protection.
PlaceàTie Hi/Lo CellàAdd
powerplan placement CTS routingfloorplanimport
VDD
VSS
Y
A tie high cell
1'b1
VDD
1'b1
-
Power Planning: Add Rings
PoweràPower PlanningàAddRings
89
powerplan placement CTS routingfloorplanimport
-
Power Planning: Add Rings
90
Use wire group to avoid slot DRC error VDD
VDD
GND
GND
powerplan placement CTS routingfloorplanimport
metal slot
-
Power Planning: Wire Group
VDD
VDD
GND
GND
VDD
VDD
GND
GND
91
Use wire group
no interleaving
number of bits = 2
Use wire group
interleaving
number of bits = 2
powerplan placement CTS routingfloorplanimport
-
Max Density Rule
• Max density violation usually happened on power ring
• Max density rule : metal area coverage must < 70%
92
powerplan placement CTS routingfloorplanimport
x 2x
x 2x
x 2x
2x
density = 2x
2x+x = 66%
-
Power Planning: Block Ring
93
powerplan placement CTS routingfloorplanimport
VDD
VDD
GND
GND
-
Power Planning: Block Ring cont.
94
powerplan placement CTS routingfloorplanimport
VDD
VDD
GND
GND
-
Block power pin
VDD
VDD
GND
GND
95
VDD
VDD
GND
GND
Add Stripes
- set to set distance
SRoute
- block
Add stripes
- over p/g pins
ring type: ping type: rail type:
-
Power Planning: Add Stripes
VDD
VDD
GND
GND
96
powerplan placement CTS routingfloorplanimport
I
I1I2I3
IR drop
-
Power Planning: Add Stripes
97
powerplan placement CTS routingfloorplanimport
-
Power Planning: Add Stripes
98
powerplan placement CTS routingfloorplanimport
VDD
VDD
VSS
VSS
blockage
-
Stripes
99
power rail
vertical
stripe
horizontal
stripe
VDD
VDD
VSS
VSSVSS
power rail
vertical
stripe
horizontal
stripe
-
SRoute
• RouteàSpecial Route
• Route Special Net (power/ground net)
– Block pins
– Pad pins
– Pad rings
– Follow pins
– Floating Stripes
– Secondary Power Pins
100
powerplan placement CTS routingfloorplanimport
-
PowerPlan Order
1. create power ring
2. connect pad pin
3. create block ring
4. connect block pin
5. create stripe
6. connect follow pin
101
hint: connect wider nets prior then narrow ones.
powerplan placement CTS routingfloorplanimport
-
Add IO filler
• Connect io pad power bus by inserting IO filler.
• Add from wider filler to narrower filler.
102
ADD IO FILLER
addIoFiller –cell
[ –prefix ]
[ -side { n|w|s|e } ]
[ -fillAnyGap ]
powerplan placement CTS routingfloorplanimport
-
Add IO filler cont.
• In order to avoid DRC error
– The sequence of placing fillers must be from wider fillers to narrower ones.
– Only the smallest filler can use -fillAnyGap option.
• Use addIoFiller.cmd provided in CIC design kit – source addIoFiller.cmd
103
powerplan placement CTS routingfloorplanimport
addIoFiller -cell PADFILLER20 -prefix IOFILLER
addIoFiller -cell PADFILLER10 -prefix IOFILLER
addIoFiller -cell PADFILLER5 -prefix IOFILLER
addIoFiller -cell PADFILLER1 -prefix IOFILLER
addIoFiller -cell PADFILLER05 -prefix IOFILLER
addIoFiller -cell PADFILLER0005 -prefix IOFILLER -fillAnyGap
fill any gap
A gap that unable to place any filler
-
Edit Route
104
Change layer
Change width
Duplicate wire
Split wire
Merge wire
Trim wire
Delete wire
Clear DRC markers
powerplan placement CTS routingfloorplanimport
hotkey : e
Fix Wire Wider than Max Width
-
Edit Route cont.
105
Trim wire
(hotkey : T)
Fix wire wider
than max width
powerplan placement CTS routingfloorplanimport
-
Edit Route cont.
106
Add Wire
Move Wire
Cut Wire
Stretch Wire
powerplan placement CTS routingfloorplanimport
-
Edit Route cont.
• Edit Route Form
107
powerplan placement CTS routingfloorplanimport
-
Edit Power Via
• PowerPower PlanningEdit Power Via…
powerplan placement CTS routingfloorplanimport
-
Clock Problem
• Clock problem
– Heavy clock net loading
– Long clock insertion delay
– Clock skew
– Skew across clocks
– Clock to signal coupling effect
– Clock is power hungry
109
powerplan placement CTS routingfloorplanimport
-
Clock Tree Topology
110
CLK
powerplan placement CTS routingfloorplanimport
-
Clock Concurrent Optimization powerplan placement CTS routingfloorplanimport
-
CCOpt/CCOpt-CTS Flow powerplan placement CTS routingfloorplanimport
-
Configure CCOpt/CCOpt-CTS
powerplan placement CTS routingfloorplanimport
-
Configure Route Type
create_route_type -name leaf_rule -non_default_rule CTS_2W1S
-top_preferred_layer M5 -bottom_preferred_layer M4
create_route_type -name trunk_rule -non_default_rule CTS_2W2S
-top_preferred_layer M7 -bottom_preferred_layer M6
-shield_net VSS -bottom_shield_layer M6
create_route_type -name top_rule -non_default_rule CTS_2W2S
-top_preferred_layer M9 -bottom_preferred_layer M8
-shield_net VSS -bottom_shield_layer M8
set_ccopt_property -net_type leaf route_type leaf_rule
set_ccopt_property -net_type trunk route_type trunk_rule
set_ccopt_property -net_type top route_type top_rule
set_ccopt_property routing_top_min_fanout 10000
-
NON DEFAULT RULE
115
NONDEFAULTRULE CTS2W2S
LAYER M1
WIDTH 0.24 ;
SPACING 0.2 ;
END M1
LAYER M2
WIDTH 0.28 ;
SPACING 0.3 ;
END M2
LAYER M3
WIDTH 0.28 ;
SPACING 0.3 ;
END M3
MINCUTS VIA1 4 ;
MINCUTS VIA2 4 ;
END CTS2W2S
LEF
-
Configure Library Cells
set_ccopt_property buffer_cells { BUFX12 BUFX8 BUFX6 BUFX4 BUFX2 }
set_ccopt_property inverter_cells { INVX12 INVX8 INVX6 INVX4 INVX2 }
set_ccopt_property clock_gating_cells { PREICGX12 PREICG8 PREICGX6 PREICGX4 }
set_ccopt_property use_inverters true
116
-
Configure Target Transition
1. Configure the maximum transition target. set_ccopt_property target_max_trans 100ps
2. CCOpt translate target_max_trans_sdc property form sdc set_max_transition constraints. If target_max_trans is not set, the target_max_trans_sdc will be inspected.
117
-
Configure Target Skew
• Configure a skew target for CCOpt-CTS (ccopt_design -cts).
• This is ignored by CCOpt (ccopt_design).
set_ccopt_property target_skew 50ps
118
-
Create CCOpt clock tree spec
Create a clock tree specification by analyzing the timing graph structure of all active setup and hold analysis views
create_ccopt_clock_tree_spec
or written to a file for inspection and then loaded
create_ccopt_clock_tree_spec -file ccopt.spec
source ccopt.spec
A clock tree specification contains clock_tree, skew_group, and property settings.
119
-
CCOpt clock tree spec
• A clock tree specification contains clock_tree, skew_group, and property settings.
120
-
Source Latency Update • CCOpt and CCOpt-CTS update sdc constraint automatically
1. switch clocks to propagated mode
2. update source latencies of clock root
• To disable source latency update,use: set_ccopt_property update_io_latency false
121
-
Outer CCOpt commnad
set_ccopt_property
get_ccopt_property
delete_ccopt_clock_tree_spec
reset_ccopt_config
report_ccopt_clock_trees
report_ccopt_skew_groups
……
122
-
CCOpt Clock Tree Debugger ClockàCCOpt Clock Tree Debugger..
123
-
Trial Route
• perform quick routing for congestion and parasitics estimation
124
• Prototyping: Quickly to gauge the feasibility
of netlist.
components in design might not
routed at legal location
powerplan placement CTS routingfloorplanimport
-
Trial Route Congestion Marker
• visually check the congestion statistics.
125
25/20
The vertical (V) overflow is 25/20
(25 tracks are required , but only 20 tracks are
available) .
powerplan placement CTS routingfloorplanimport
-
Trial Route Congestion Marker cont.
• Set Congection Map Stype
– RouteàNanoRouteà Analysis Congection…
126
Level Color Overflow Value
0 Black 4
powerplan placement CTS routingfloorplanimport
-
Timing Analysis
127
TimingàReport Timing …
powerplan placement CTS routingfloorplanimport
placement
Routing
Extract RC
Delay calculation
Timing analysis
-
Timing Debug
powerplan placement CTS routingfloorplanimport
TimingàDebug Timing
-
Timing Debug
129
TimingàDebug Timing
powerplan placement CTS routingfloorplanimport
-
Timing Path Analyzer
130
powerplan placement CTS routingfloorplanimport
drive adjustment uncertainty setup
negative slack
Data Path
CK
D
CLKclock latency
set drive
input delay
-
Timing Path Analyzer
131
powerplan placement CTS routingfloorplanimport
Clock Path
-
Timing Path Analyzer
132
powerplan placement CTS routingfloorplanimport
Path SDC
drive adjustment uncertainty setup
negative slack
-
Timing Path Analyzer
133
powerplan placement CTS routingfloorplanimport
Timing Interpretation
-
Timing Path Analyzer
134
powerplan placement CTS routingfloorplanimport
Schematic
-
Timing Path Analyzer reg2reg
135
powerplan placement CTS routingfloorplanimport
CLKlatency
CKCKlatency
D D
-
Timing Path Analyzer reg2out
136
powerplan placement CTS routingfloorplanimport
CLK
CKlatency
Dset output delay
set output load
-
Debug Hold Time
137
powerplan placement CTS routingfloorplanimport
-
Optimization
• Optimization
– setup time
– hold time
– DRV (Design Rule Violation)
138
Optimizeà Optimize Design…
powerplan placement CTS routingfloorplanimport
-
Mode Setup -- Optimization
139
powerplan placement CTS routingfloorplanimport
-
Useful Skew
140
10ns
balanced clock
11ns 9ns
1ns
10ns
schedule clock
11ns 10ns
-1ns
9ns
After CTS
Before CTS
powerplan placement CTS routingfloorplanimport
-
Power Analysis
141
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
powerplan placement CTS routingfloorplanimport
-
Power Component
• dynamic power
– switching power
• P=f*1/2CV2
– internal power
• static power
– leakage power
142
Q
rst
clk
D
DFF
switching power
Internal power
reverse bias
-
143
Internal Power Model
143
Req
Ceq
I1 I2 I3
powerplan placement CTS routingfloorplanimport
-
Power Analysis
144
gate-level
netlist
Power Analysis
Power
model
Power
report
toggle
probabilitySimulation
SDF gate-level
netlistsimulation
pattern
simulation
modelTCF/VCD Power Analysis
Power
model
Power
report
powerplan placement CTS routingfloorplanimport
-
Switching Activity Information
• Get VCD file by simulation – save netlist for simulation
• FileàSaveàNetlist…
– save sdf for simulation • TimingàWrite SDF…
– simulation and dump vcd file. • $dumpvars;
• $dumpfile(“wave.vcd”);
– Input vcd file for power analysis
145
setAnalysisMode -analysisType bcwc
write_sdf
-max_view av_func_mode_max \
-typ_view av_func_mode_typ \
-min_view av_func_mode_min \
-edges noedge \
-splitsetuphold \
-remashold \
-splitrecrem \
-min_period_edges none \
CHIP.sdf
(CELL
(CELLTYPE "INVXL")
(INSTANCE DFT_shared_out_mux_6)
(DELAY
(ABSOLUTE
(IOPATH A Y (0.14:0.29:0.32) (0.08:0.17:0.23))
)
)
)
-
Power Analysis
• Create power grid library ( required by dynamic power analysis mode)
– Setup library mode:
• PoweràRail Analysisà Set PG Library Mode
– Create library
• PoweràRail Analysisà Generate PG Library
• Run Power Analysis
– Set power analysis mode
• PoweràPower AnalysisàSetup…
– run power analysis
• PoweràPower AnalysisàRun …
powerplan placement CTS routingfloorplanimport
146
-
Power Grid Library Mode
147
PoweràRail AnalysisàSet PG Library Mode…
powerplan placement CTS routingfloorplanimport
-
Create Power Library
148
PoweràRail AnalysisàGenerate PG Library
power grid view contain
tap location
tap capacitance
tap current
internal resistor grid
device decoupling
powerplan placement CTS routingfloorplanimport
-
Power Analysis PoweràPower AnalysisàSetup…
149
powerplan placement CTS routingfloorplanimport
-
Power Analysis
PoweràPower AnalysisàRun…
150
powerplan placement CTS routingfloorplanimport
-
Power Analysis result • Power report
• Power DB
• Instance current file
151
powerplan placement CTS routingfloorplanimport
Group Internal Switching Leakage Total Percentage
Power Power Power Power (%)
----------------------------------------------------------------------------------------------------
Sequential 22.07 2.88 0.00354 24.96 30.61
Macro 3.228 0.03977 0.01 3.278 4.02
IO 17.96 14.97 0.003231 32.93 40.39
Combinational 9.817 6.712 0.005406 16.53 20.28
Clock (Combinational) 1.493 2.341 0.000202 3.835 4.703
Clock (Sequential) 0 0 0 0 0
----------------------------------------------------------------------------------------------------
Total 54.57 26.95 0.02238 81.54 100
-
Power Histograms…
152
PoweràReportàPower Histograms…
powerplan placement CTS routingfloorplanimport
-
Power & Rail Results
153
PoweràReportà
Power&Rail Results…
powerplan placement CTS routingfloorplanimport
-
Power Graph – Instance Total Power
154
powerplan placement CTS routingfloorplanimport
-
Power Graph – Instance transistion Density
155
powerplan placement CTS routingfloorplanimport
-
Rail Analysis
156
powerplan placement CTS routingfloorplanimport
I
power analysis
VCD/SAIF
instance current
rail analysis
simulation
-
Rail Analysis
• Create power grid library ( required by dynamic rail analysis)
– Setup:
• PoweràRail Analysisà Set PG Library Mode
– Generate:
• PoweràRail Analysisà Generate PG Library
• Run Rail Analysis
– Set rail analysis mode
• PoweràRail AnalysisàSet Rail Analysis Mode…
– run rail analysis
• PoweràRail AnalysisàRun Rail Analysis…
157
powerplan placement CTS routingfloorplanimport
-
Rail Analysis
158
PoweràRail AnalysisàSet Rail Analysis Mode…
powerplan placement CTS routingfloorplanimport
-
Rail Analysis
159
PoweràRail AnalysisàRun Rail Analysis…
powerplan placement CTS routingfloorplanimport
-
Pad Location File
160
powerplan placement CTS routingfloorplanimport
-
Power & Rail Results
161
PoweràReportà
Power&Rail Results…
powerplan placement CTS routingfloorplanimport
-
Power Graph – IR drop
162
powerplan placement CTS routingfloorplanimport
I
I1I2I3
-
Power Graph – Electromigration
163
powerplan placement CTS routingfloorplanimport
-
Dynamic Waveforms
164
PoweràReportàDynamic Waveforms…
powerplan placement CTS routingfloorplanimport
-
NanoRoute
165
RouteàNanoRouteàRoute
powerplan placement CTS routingfloorplanimport
Optimize Via
Optimize Wire
-
Crosstalk
166
Crosstalk problem are getting more serious in 0.25um and below
for:
Smaller pitches
Greater height/width ratio
Higher design frequency
-
SI Problem
167
Aggressor
original signal
impacted signal
Delay problem
Noise problem Aggressor
original signal
impacted signal
-
SI Prevention
168
Placement solution
Insert buffer in lines
Upsize driver
Congestion optimization
Routing solution
Limit length of parallel nets
Wider routing grid
Shield special nets
Add buffer
Upsize
-
SI Analysis
169
TimingàReport Timing …
powerplan CTS routingimport placementfloorplan
-
Verify Gemoetry
170
VerifyàVerify Geometry
powerplan CTS routingimport placementfloorplan
-
Verify Connectivity
171
VerifyàVerify Connectivity
powerplan CTS routingimport placementfloorplan
D
CLK
Q D
CLK
Q
D
CLK
Q
D
CLK
Q
D
CLK
Q
D
CLK
Q
connectivity
database
layout
database
-
Verify process Antenna
172
VerifyàVerify Process Antenna…
powerplan CTS routingimport placementfloorplan
-
173
Antenna Effect
In a chip manufacturing process, Metal is initially deposited so
it covers the entire chip.
Then, the unneeded portions of the metal are removed by
etching, typically in plasma(charged particles).
The exposed metal collect charge from plasma and form voltage
potential.
If the voltage potential across the gate oxide becomes large
enough, the current can damage the gate oxide.
powerplan placement CTS routingfloorplanimport
-
Antenna Ratio
174
+ + + + + +
Plasma
gate oxide poly
metal1
via1
Antenna Ratio = Area of process antennas on a node
Area of gates to the node
metal2
via2
metal2
+ + + + + + +
Plasma
powerplan placement CTS routingfloorplanimport
-
Antenna Problem Repair
• Add jumper
• Add antenna cell (diode)
• Add buffer
175
gate oxide
poly metal1 via1
metal2
powerplan placement CTS routingfloorplanimport
-
Add Core Filler
• Connect the NWELL/PWELL layer in core rows.
• Insert Well contact.
• Add from wider filler to narrower filler.
176
PlaceàFilleràAdd Filler…
powerplan placement CTS routingfloorplanimport export
core filler
well
gap
-
Add bonding pads
177
PIN
Bonding matel
Logic and driver
Linear IO pad Stagger IO pad
PR boundary
Outer Bonding
Inner Bonding
Abutted Stagger IO
powerplan placement CTS routingfloorplanimport export
-
Circuit Under Pad
178
traditional bonding pad CUP bonding pad
200 u
m
-
Add bonding pads
• For the limitation of bonding wire technique , the stagger IO pads are used in order to reduce IO pad width.
• We have to add the bonding pads after APR is finished if stagger IO pads is used. But Encounter does not provide a built-in function for add bonding pads, CIC reaches this purpose by the way of importing DEF.
• CIC provides a perl script to calculate the bonding pad location. The full flow is described in next page
179
powerplan placement CTS routingfloorplanimport export
-
Add bonding pads flow (stagger IO pads only)
180
A placed and routed
design in encounter
routed.def
addbond.cmd addbonding_v3.pl routed.def
(In unix terminal)
Export DEF
(In encounter)
source addbond.cmd
(In encounter terminal)
finish
addbonding_v3.pl
io.list
powerplan placement CTS routingfloorplanimport export
-
Add Dummy Metal
• Why add dummy – meet minimize metal density rule
– prevent over etching
– prevent sagging in local area
– improve yield
– reduce on chip variation
• better connect dummy metal to VSS
• Side effect – introduce parasitic to signal line
181
-
Add Dummy Metal
182
RouteàMetal FillàSetup…
-
Add Dummy Metal
183
RouteàMetal FillàAdd…
-
Add text IOVDD & IOVSS
184
add_text -layer METAL5 -label IOVSS -pt 1365 1095 -height 10
add text location
powerplan placement CTS routingfloorplanimport export
-
Output Data
• Export GDS for DRC,LVS,LPE,and tape out.
• Export Netlist for LVS and simulation.
• Export Netlist and sdf for post layout simulation
• Export DEF for reordered scan chain.
185
powerplan placement CTS routingfloorplanimport export
DesignàSaveàGDS…
DesignàSaveàNetlist…
write_sdf
DesignàSaveàDEF
-
Export sdf
setAnalysisMode -analysisType bcwc
write_sdf -max_view av_func_mode_max \
-typ_view av_func_mode_typ \
-min_view av_func_mode_min \
-edges noedge \
-splitsetuphold \
-remashold \
-splitrecrem \
-min_period_edges none \
CHIP.sdf
186
source savesdf.cmd
savesdf.cmd
(CELL
(CELLTYPE "INVXL")
(INSTANCE DFT_shared_out_mux_6)
(DELAY
(ABSOLUTE
(IOPATH A Y (0.14:0.29:0.32) (0.08:0.17:0.23))
)
)
)
CHIP.sdf
-
Stream Out
streamOut CHIP.gds \
-mapFile streamOut.map \
-merge { gds/RF2SH64x16.gds \
gds/tpb973gv.gds \
gds/tsmc18_core.gds \
gds/tsmc18_io.gds } \
-stripes 1 -units 1000 -mode ALL
187
EditàSaveàGDS/OASIS…
• source savegds.cmd savegds.cmd
-
Stream Out
• Merge gds
188
only cell name and location full cell layout information
cell gds
-
Stream Out map
189
METAL1 ALL 16 0
NAME METAL1/NET 16 0
NAME METAL1/SPNET 40 0
NAME METAL1/PIN 40 0
NAME METAL1/LEFPIN 16 0
VIA12 ALL 17 0
METAL2 ALL 18 0
…
…
Layer/object name layer/object type layer number data type
powerplan placement CTS routingfloorplanimport export
-
Chapter 2
Encounter Foundation Flow
190
-
Flow feature
• The recommended flow to implement a block of flat chip from a completed floorplan.
• A single source of all data required to run design
• A flow environment that is both structured and flexible
191
-
Flow Step
192
-
Create Flow Environment
1. Create Flow template – FlowsàCreate Foundation Flow TemplateàSave
– writeFlowTemplate
2. Prepare setup file – FlowsàFoundation Flow Wizard…
– SCRIPTS/gen_edi_setup.tcl
3. Generate script – SCRIPTS/gen_edi_flow.tcl
or
or
-
Foundation Flow Wizard
• FlowsàFoundation Flow Wizard…
-
Library
-
Design
-
Timing
-
Power
-
Tool Setup
-
User Plug-in
-
Environment setup
• setup file (by Foundation Flow Wizard) – setup.tcl
– edi_config.tcl
– lp_config.tcl
• Create Flow script – SCRIPTS/gen_edi_flow.tcl
• Generate tcl script
• Generae Makefile
• Execution – make make_target
201
-
Flow Environment Structure file or directory description
setup.tcl
edi_config.tcl
lp_config.tcl
design data setup
Makefile make file
FF/ flow script
RPT/ timing/clock/verification report
DBS/ encounter data save
LOG/ command log and message log
make/ makefile flow control
PLUG/ user custom plugin
202
-
Data Prepare
• EDI System configuration file (setup.tcl)
– Timing libraries
– Lef libraries
– timing constraints
– capacitane table or QRC technology file
– SI libraries
• Verilog netlist
• Floorplan file
• clock Tree Specification file
• Scan Chain information
• GDS Layer map file
203
-
Flow control
make target Script DBS condition
init run_init.tcl Init.enc make/init
place run_place.tcl place.enc make/place
prects run_prects.tcl prects.enc make/prects
cts run_cts.tcl cts.enc make/cts
postcts run_postcts.tcl postcts.enc make/postcts
postcts_hold run_postcts_hold.tcl postcts_hold.enc make/postcts_hold
route run_route.tcl route.enc make/route
postroute run_postroute.tcl postroute.enc make/postroute
postroute_hold run_postroute_hold.tcl postroute_hold.enc make/postroute_hold
signoff run_signoff.tcl signoff.enc make/signoff
204
-
Files in Plug directory
205
always_source.tcl
pre_init.tcl
post_init.tcl
pre_partition.tcl
pre_place.tcl
post_place.tcl
pre_place_checks.tcl
pre_prects.tcl
post_prects.tcl
pre_cts.tcl
post_cts.tcl
pre_postcts.tcl
post_postcts.tcl
pre_postcts_hold.tcl
post_postcts_hold.tcl
pre_route.tcl
post_route.tcl
pre_postroute.tcl
post_postroute.tcl
pre_postroute_hold.tcl
post_postroute_hold.tcl
pre_postroute_si_hold.tcl
post_postroute_si_hold.tcl
pre_postroute_si.tcl
post_postroute_si.tcl
pre_signoff.tcl
post_signoff.tcl
-
Post-Layout Verification – DRC/ERC/LVS/LPE
Chapter3
-
Post-Layout Verification Overview
• Post-Layout Verification do the following things :
– DRC ( Design Rule Check )
– ERC (Electrical Rule Check )
– LVS (Layout versus Schematic )
– LPE/PRE (Layout Parasitic Extraction / Parasitic Resistance Extraction) and Post-Layout Simulation.
207
-
Post-Layout Verification Overview cont.
208
DRC
LPE/PRE ERC
LVS
0 1 3 2
zn i compare with
zn i
vdd!
VSS!
zn i
vdd!
VSS!
zn i extract
clk vdd!
short
-
DRC flow
• Prepare Layout
• Prepare command file
• run DRC
• View DRC error (DRC summary/RVE)
209
-
Prepare Layout
• stream out with cell gds merged
• be sure to use layer map file provided by CIC
210
-
Prepare command file
• Prepare DRC Command file:
– TSMC 90nm (CBDK_TSMC90G_Arm) Calibre
• CLN90S_3XTM_9M.22a1
– TSMC 0.18 (CBDK018_TSMC_Artisan) Calibre
• CLM18_LM16_6M.28a_m.drc
211
-
Prepare Calibre Command file
• Edit runset file
212
LAYOUT PATH “CHIP.gds2”
LAYOUT PRIMARY “CHIP”
LAYOUT SYSTEM GDSII
…
…
…
DRC SELECT CHECK
NW.W.1
NW.W.2
…
DRC UNSELECT CHECK
NW.S.1Y
NW.S.2Y
…
DRC ICSTATION YES
INCLUDE “Calibre-drc-cur”
-
Submit Calibre Job
• Submit Calibre Job
– unix% calibre –drc CLM18_LM16_6M.28a_m.drc
– Result log
– DRC.sum (ASCII result)
– DRC.db (Graphic result)
213
-
View Calibre result in SOC Encounter
ToolsàViolation Browser…
214
-
Calibre Interactive In Encounter
• STEP1
– source calibre.cshrc
– source edi.cshrc
– exec encounter
– In encounter terminal:
source /usr/cad/mentor/calibre/cur/lib/cal_enc.tcl
-
Calibre menu in Encounter
-
Setup streamout options
• STEP2 : calibreàSetupàGDS Export
streamOut CHIP.gds \
-mapFile streamOut.map \
-merge { gds/RF2SH64x16.gds \
gds/tpb973gv.gds \
gds/tsmc18_core.gds \
gds/tsmc18_io.gds } \
-stripes 1 -units 1000 -mode ALL
-
Calibre Interactive
• STEP3: calibreàRun nmDRC
-
Calibre RVE
-
LVS Overview
220
a
a
a
a
a
a
b
b
b
b
b
b
VSS!
VSS
VDD
VDD
VSS
clk rst VDD cin
s s. . . . .
sel VSS
Layout Data Schematic Netlist
a
b
clk
rst
cin
sel
s
carry
-
Initial Correspondence Points
• Initial correspondence points establish a starting place for layout and schematic comparison.
• Create initial correspondence node pairs by
– adding text strings on layout database.
– all pins in the top of schematic netlist will be treated as an initial corresponding node if calibre finds a text string in layout which matches the node name in schematic.
221
a
b
. . .
. . .
VDD
a
b . . .
initial corresponding
node pairs
global pin : VDD and VSS
-
Black-Box LVS
Calibre black-box LVS
– One type of hierarchical LVS.
– Black-box LVS treats every library cell as a black box.
– Black-box LVS checks only the interconnections between library cells in your design, but not cell inside.
– You need not know the detail layout of every library cells.
– Reduce CPU time.
222
-
Black-Box LVS vs. Transistor-Level LVS
223
Transistor Level LVS
i1
VDD
VSS
z
i2
i1
i2
z
Black-Box LVS
vs.
vs.
i1
i2
z
inv0d1 nd02d1
inv0d1 nd02d1 i1
i2
VDD
VSS
z
-
LVS flow
• Prepare Layout
– The same as DRC Prepare Layout
• Prepare Netlist
– v2lvs
• Prepare calibre command file
• run calibre LVS
• View LVS error (LVS summary/RVE)
224
-
Prepare Netlist for Calibre LVS
• v2lvs –v CHIP.v –l tsmc18_lvs.v –l tpz973gv_lvs.v –s tsmc18_lvs.spi –s tpz973gv_lvs.spi –o source.spi –s1 VDD –s0 VSS
If a macro DRAM64x16 is used • v2lvs –v CHIP.v –l tsmc18_lvs.v –l tpz973gv_lvs.v –l DRAM64x16.v –s tsmc18_lvs.spi –s
tpz973gv_lvs.spi –s DRAM64x16.spi –o source.spi –s1 VDD –s0 VSS
225
source.spi
v2lvs
Prepare Netlist
Verilog
CHIP.v tsmc_18lvs.v
tpz973gv_lvs.v
tsmc_18lvs.spi
tpz973gv_lvs.spi
-
226
CIC Supported Files (tsmc0.18)
CIC supports the following files in our cell library design kit.
Calibre LVS rule file
Calibre.lvs
Black-box LVS relative files
pseudo spice file
tsmc18_lvs.spi
tpz973gv_lvs.spi
pseudo verilog file
tsmc18_lvs.v
tpz973gv_lvs.v
-
Black Box related file
• Pseudo spice file .GLOBAL VDD VSS
.SUBCKT AN2D1 Z A1 A2 VDD VSS
.ENDS
…
• Pseudo verilog file module AN2D1 (Z, A1, A2);
output Z;
input A1;
input A2;
endmodule
…
227
-
Generate Pseudo Verilog file
• gen pseudo verilog for from simulation model, but leaving only header definition.
• gen pseudo spice by run v2lvs on pseudo verilog
unix% v2lvs –v RF2SH64x16.v
• ADD VDD VSS port on pseudo spice
228
module RF2SH64x16 (
QA,
AA,
CLKA,
CENA,
AB,
DB,
CLKB,
CENB
);
output [15:0] QA;
input [5:0] AA;
input CLKA;
input CENA;
input [5:0] AB;
input [15:0] DB;
input CLKB;
input CENB;
endmodule
.SUBCKT RF2SH64x16 QA[15] QA[14] QA[13] QA[12] QA[11] QA[10] QA[9] QA[8] QA[7]
+ QA[6] QA[5] QA[4] QA[3] QA[2] QA[1] QA[0] AA[5] AA[4] AA[3] AA[2] AA[1] AA[0]
+ CLKA CENA AB[5] AB[4] AB[3] AB[2] AB[1] AB[0] DB[15] DB[14] DB[13] DB[12]
+ DB[11] DB[10] DB[9] DB[8] DB[7] DB[6] DB[5] DB[4] DB[3] DB[2] DB[1] DB[0]
+ CLKB CENB
.ENDS
.SUBCKT RF2SH64x16 QA[15] QA[14] QA[13] QA[12] QA[11] QA[10] QA[9] QA[8] QA[7]
+ QA[6] QA[5] QA[4] QA[3] QA[2] QA[1] QA[0] AA[5] AA[4] AA[3] AA[2] AA[1] AA[0]
+ CLKA CENA AB[5] AB[4] AB[3] AB[2] AB[1] AB[0] DB[15] DB[14] DB[13] DB[12]
+ DB[11] DB[10] DB[9] DB[8] DB[7] DB[6] DB[5] DB[4] DB[3] DB[2] DB[1] DB[0]
+ CLKB CENB VDD VSS
.ENDS
-
Prepare command file for Calibre LVS
• Edit Calibre LVS runset
229
LAYOUT PATH “CHIP.calibre.gds”
LAYOUT PIMARY “CHIP”
LAYOUT SYSTEM GDSII
SOURCE PATH “source.spi”
SOURCE PRIMARY “CHIP”
…
…
INCLUDE “/calibre/LVS/Calibre-lvs-cur”
Edit Calibre LVS rule file …
…
LVS BOX PVSSC
LVS BOX PVSSR
LVS BOX DRAM64x4s
-
Submit Calibre LVS
• calibre –lvs –spice layout.spi –hier –auto Calibre.lvs > lvs.log
230
layout verilog
source.spi layout.spi
v2lvs extract
-
Check Calibre LVS Summary
• OVERALL COMPAISON RESULTS
• CELL SUMMARY
• INFORMATION AND WARNINGS
• Initial Correspondence Points
231
-
Check Calibre LVS Summary OVERALL COMPAISON RESULTS
OVERALL COMPARISON RESULTS
# ################### _ _
# # # * *
# # # CORRECT # |
# # # # \___/
# ###################
232
-
Check Calibre LVS Summary CELL SUMMARY
*************************************************
CELL SUMMARY
*************************************************
Result Layout Source
----------- ----------- --------------
CORRECT CHIP CHIP
233
-
Check Calibre LVS Summary INFORMATION AND WARNINGS
****************************************************************** INFORMATION AND WARNINGS ****************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ----------- ----------- -------------- --------------- -------------- Nets: 11525 11525 0 0 Instances: 1 1 0 0 ADDFHX1 54 54 0 0 ADDFHX4 79 79 0 0 ADDFX2 542 542 0 0 AND2X1 …… …… .. .. …………. 8 8 0 0 XOR3X2 ----------- ----------- -------------- --------------- -------------- Total Inst: 10682 10682 0 0
234
-
Check Calibre LVS Summary Initial Correspondence Points
Initial Correspondence Points:
Nets: VDD VSS I_X[2] I_X[3] I_X[4] I_X[5] I_X[6] I_X[7] I_X[8] I_X[9] I_X[10]
I_X[11] O_SCAN_OUT O_Z[0] O_Z[1] O_Z[2] O_Z[3] I_HALT I_RESET_ I_DoDCT I_RamBistE I_CLK I_SCAN_IN I_SCAN_EN I_X[0] O_Z[4] I_X[1] O_Z[5] O_Z[6] O_Z[7] O_Z[8] O_Z[9] O_Z[10] O_Z[11]
235
-
Check Calibre LVS Log
• TEXT OBJECT FOR CONNECTIVITY EXTRACTION
• PORTS
• Extraction Errors and Warnings for cell “CHIP”
236
-
Check Calibre LVS Log TEXT OBJECT FOR CONNECTIVITY EXTRACTION
--------------------------------------------------------------------------------
TEXT OBJECTS FOR CONNECTIVITY EXTRACTION
--------------------------------------------------------------------------------
O_Z[0] (523.447,31.68) 105 CHIP O_Z[1] (598.068,31.68) 105 CHIP
O_Z[2] (821.931,31.68) 105 CHIP O_Z[3] (896.553,31.68) 105 CHIP
O_Z[4] (971.175,31.68) 105 CHIP O_Z[5] (1164.455,372.964) 105 CHIP
O_Z[6] (1164.455,446.966) 105 CHIP O_Z[7] (1164.455,520.968) 105 CHIP
O_Z[8] (1164.455,594.97) 105 CHIP O_Z[9] (1164.455,668.972) 105 CHIP
O_Z[10] (1164.455,742.974) 105 CHIP O_Z[11] (1164.455,816.976) 105 CHIP
……
……
237
-
Check Calibre LVS Log PORTS
--------------------------------------------------------------------------------
PORTS
--------------------------------------------------------------------------------
O_Z[0] (523.447,31.68) 105 CHIP O_Z[1] (598.068,31.68) 105 CHIP
O_Z[2] (821.931,31.68) 105 CHIP O_Z[3] (896.553,31.68) 105 CHIP
O_Z[4] (971.175,31.68) 105 CHIP O_Z[5] (1164.455,372.964) 105 CHIP
……
……
238
-
Check Calibre LVS Log Extraction Errors and Warnings for cell “CHIP”
Extraction Errors and Warnings for cell "CHIP" ---------------------------------------------- WARNING: Short circuit - Different names on one net: Net Id: 18 (1) name “VSS" at location (330.301,216.95) on layer 102 "M2_TEXT" (2) name “VSS" at location (673.2,29.1) on layer 101 "M1_TEXT" (3) name "VDD" at location (748.1,31.5) on layer 101 "M1_TEXT" (4) name "VDD" at location (208.93,274.56) on layer 101 "M1_TEXT" The name "VDD" was assigned to the net.
239
-
Post-Layout Timing Analysis -- Nanosim
Chapter4
-
What Introduce After Place&Route?
• Interconnection wire’s parasitic capacitance.
241
M1 to substrate
capacitance
M1 to M1
capacitance
M1 to M2
capacitance
M1
M2
vdd!
VSS!
vdd!
VSS!
-
What Introduce After Place&Route?
• Interconnection wires’ parasitic resistance.
242
M1 parasitic resistance
M2 parasitic resistance
VIA parasitic resistance
vdd!
VSS!
vdd!
VSS!
M1
M2
VIA
-
Pre-Layout And Post-Layout Design
• A pre-layout design (before P&R) and a post-layout design (after P&R)
243
pre-layout
post-layout
-
Post-layout Timing Analysis Flow
244
Gate-level
Netlist
Gate-level
Analysis
Delay
Calculation
Layout
Tr. Netlist
RC Network
Tr-level
Analysis
RC Network
Extraction
Gate-level post-layout
timing analysis
Tr.-level post-layout
timing analysis
-
Transistor-level Post-layout Simulation
245
layout
netlist/parasitic
extraction
SPICE netlist
Post-layout
simulation
simulation
stimulus
simulation
result
Calibre LPE/PRE
VCS-Nanosim
-
What is Nanosim
• Nanosim is a transistor- level timing simulation tool for
digital and mixed signal CMOS and BiCMOS designs.
• Nanosim handles voltage simulation and timing check.
• Simulation is event driven, targeting between SPICE
( circuit simulator ) and Verilog ( logic simulator ).
246
-
Prepare for Post-Layout Simulation
• Apply for a CIC account
– http://www.cic.org.tw 工作站帳號申請.
– fill in your personal data and your request.
• Connect to CIC queue server
– ssh -l your_account queue.cic.org.tw
• Put gds file to your account via ftp
247
-
Replace Layout / LPE
248
Example:
Qentry –M LPE –tech TSMC18 –f CHIP.gds –T CHIP -s RAM1.spec –t
t18ra1sh –s RAM2.spec –t t18ra2sh –s RAM3.spec –t t18ra2sh –c TSMC18 –i TSMC18 –o CHIP.netlist
Use showq to check the status of your job.
The result is stored in “result_#” directory.
Qentry -M [DRC|LPE] -tech TSMC18
-f gds_file
-T top_module
[ -c TSMC18 ]
[ -i TSMC18 ]
[ -s ram_spec_file -t t18ra1shd ]
[ -s ram_spec_file -t t18ra2sh ]
[ -s ram_spec_file -t t18ra2sh ]
[ -s ram_spec_file -t t18rf1sh ]
[ -s ram_spec_file -t t18rf2sh ]
[ -s ram_spec_file -t t18rodsh -rom rom_code_file ]
[ -addTagCell ]
[ -addDummyCell ]
Qentry -M DRC -tech TSMC18 -help
Available process technology:
TN40LP
TSMC90GUTM
TN65GP
TN40G
TSMC35
TSMC25HVG2
TSMC18
-
Replace/LPE
• INPUT
– gds2
– ram spec
• OUTPUT
– output netlist
– TOP_CELL.NAME
– nodename
– spice.header
– nanosim.run
– log files for strem in, stream out, lpe
249
-
VCS-Nanosim co-simulation
• Architecture
250
TOP (verilog)
DUT1(spice)
DUT2(spice)
pattern gen
(verilog)
-
VCS-Nanosim co-simulation
• Advantage
– Simulation directly with VCS command and option. In this way, we no longer need to generate patterns for nanosim simulation.
– For some case, the test pattern must depend on the response of the DUT, such as the unpredictable locking time of a PLL. In this way, this problem can be solved.
– Multi-chip simulation is now available.
251
-
Running VCS_Nanosim
• Qentry -M VCS_NS @vcs_argument -ad=vcsAD.init
• Example: –Qentry –M VCS_NS a.v b.v –v tsmc18.v –f vlog.f -ad=vcsAD.init
• Use showq to check the status of your job.
• The result is stored in “result_#” directory.k
252
-ad is a required option for mixed signal simulation
-
Example Design
• Archtecture
• command
– Qentry -M VCS_NS CHIP_sim.v CHIP.v -ad=vcsAD.init
253
test (verilog stimulus module)
CHIP (DUT spice subckt)
CHIP_sim.v
CHIP.spi
The DUT netlist is CHIP.spi, but a pseudo verilog CHIP.v is needed.
Origial vcs cmd: vcs CHIP_sim.v CHIP.v
-
Example Design
• vcsAD.init
254
use_spice -cell CHIP ;
choose nanosim -n spice.header CHIP.spi -C TOP.cfg -o wave;
set bus_format [%d];
set spice_port_order_as_vlog;
config for top
output wave name
indicate CHIP is an analog module
DUT
subckt port order match verilog module order
-
Example Design
• CHIP.v
– A reference module for spice subckt port matching
255
module CHIP ( IOVDD, IOVSS, VDD, VSS,
CLK, HALT, RESET_, DoDCT,
X, Z, Mode, SCAN_IN,
SCAN_OUT, SCAN_EN);
inout IOVDD, IOVSS, VDD,VSS;
input [11:0] X;
output [11:0] Z;
input CLK, HALT, RESET_, DoDCT, Mode, SCAN_IN, SCAN_EN;
output SCAN_OUT;
endmodule
.subckt CHIP IOVSS VSS IOVDD VDD SCAN_OUT X[11] X[10] X[9] X[8] X[7] X[6] X[5]
+ X[4] X[3] Z[0] Z[1] Z[2] Z[3] Z[4] Z[5] X[2] X[1] X[0] HALT RESET_ CLK DoDCT
+ Mode Z[6] SCAN_IN Z[7] Z[8] Z[9] Z[10] Z[11] SCAN_EN
CHIP.spi
-
Example Design
• TOP.cfg
256
set_node_v test.CHIP.IOVDD 3.3
set_node_gnd test. CHIP.IOVSS
set_node_v test.CHIP.VDD 1.8
set_node_gnd test. CHIP.VSS
set_node_cap test. CHIP.Z[11:0] 20p
set_node_cap test. CHIP.SCAN_OUT 20p
report_node_powr test. CHIP.VDD test.CHIP.VSS test.CHIP.IOVDD test.CHIP.IOVSS
print_node_logic test.CHIP.SCAN_OUT
print_node_logic test.CHIP.X[11:0]
print_node_logic test.CHIP.Z[11:0]
print_node_logic test.CHIP.HALT
print_node_logic test.CHIP.RESET_
print_node_logic test.CHIP.CLK
print_node_logic test.CHIP.DoDCT
print_node_logic test.CHIP.Mode
print_node_logic test.CHIP.SCAN_IN
print_node_logic test.CHIP.SCAN_EN
set_print_format for=fsdb file=merge
bus_notation [ : ]
X[0] X[1] . . . . . . CLK DoDCT . . . . . .
nodename file
-
Example Design
• spice.header
257
.lib "rf018.l" dio3
.lib "rf018.l" dio_dnw
.lib "rf018.l" dio
.lib "rf018.l" tt_rfres_sa
.lib "rf018.l" tt_rfmvar
.lib "rf018.l" tt_rfind
.lib "rf018.l" tt_rtmom
.lib "rf018.l" tt_bbmvar
.lib "rf018.l" tt
.lib "rf018.l" tt_rfesd
*epic tech="voltage 3.3“
*epic tech="temperature 100"
-
View Simulation Result --- nWave
• Environment setup unix% source /usr/cad/synopsys/CIC/verdi.csh
• Starting nWave unix% nWave &
258
-
Load Simulation Result --- nWave
259
-
Select Signals --- nWave
Signals Get Signals ...
260
-
Check Simulation Result --- nWave
261
-
Power Analysis Result
• The power analysis result is stored in Nanosim simulation log (xxx.log) file
262
. . . . . .
Current information calculated over the intervals:
0.00000e+00 - 1.00010e+03 ns
Node: VDD
Average current : -3.53355e+05 uA
RMS current : 3.53388e+05 uA
Current peak #1 : -4.54061e+05 uA at 6.78400e+02 ns
Current peak #2 : -4.34973e+05 uA at 4.00000e-01 ns
Current peak #3 : -3.88048e+05 uA at 2.59000e+01 ns
Current peak #4 : -3.87280e+05 uA at 1.27500e+02 ns
Current peak #5 : -3.84302e+05 uA at 5.77800e+02 ns
. . . . . .