September 7, 2018 Sam Siewert

CEC 450Real-Time Systems

Lecture 3 – Real-Time Service Implementation

Part 1

More Embedded SystemsSummer - Analog, Digital, Firmware, Software

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Reasons to Consider…

Catch up over summer

Cultural mind expansion

High Tech Jobs abroad

Fairly affordable

Full Stack HW -> SWCEC495 - Zephyr RTOS

Beautiful West Coast

English and Irish Language

Weather nice in summer!

Quick ReviewLast Week – Service Utility, Qualitative Utility over Time

Week Before – RM Policy, Feasibility, Safety

Timing Diagrams over LCM

Use Cheddar to Check Work - Overview

Assignment #1 - My Solution (not ideal, but basically works) - Lab 1 Sequencer

Better solution for sequencing (one delay) - Generic Sequencer Sam Siewert 3

Theory to RTOS to Linux CompareRM Theory with 10 msec units– S1=fib10, C1=1, T1=D1=2; S2=fib20, C2=2, T2=D2=5

VxWorks RTOS equivalent with synthetic workload

Jetson Linux equivalent with synthetic workload (float msec)

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Lab 1 T1 2 C1 1 U1 0.5 LCM = 10T2 5 C2 2 U2 0.4 Utot = 0.9

RM ScheduleS1S2 FREE

S1S2

Idle

3 Approaches to RT SystemsCyclic ExecE.g. Shuttle Flight Software, Network elements, process control, Ada CE

Custom, Deeply Embedded Systems

Low over-head, purpose-built

Costly to develop

RTOSVxWorks, QNX, ThreadX, TI RTOS, FreeRTOS, Zephyr, Nucleus, RTEMS, etc.

Embedded Systems, Scalable and Portable

Medium overhead, quick to market

License costs

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OS + RT POSIXRT Linux, Solaris, LynxOS, FSM Labs, Concurrent, RTAI, Linux Foundation RT, etc.

RT Services for Scalable Apps and Systems

Highest overhead, mixed RT + SRT + BE

Maintenance costs

Brief History of Unix, Linux, OS-X vs RTOS

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VxWorks

RTEMS

Linux, Zephyr,

FreeRTOS

C/ASM & CE,

Fortran, Ada

OS-less

Wind River

Intel 8051

Zilog Z80

Intel RAM

1951 - TI

RTOS - Proprietary vs Open SourceNew Projects - Open Source

Embedded Linux and FreeRTOS are future

VxWorks, etc. are Legacy Embedded Systems

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Today

Next …

https://m.eet.com/media/1246048/2017-embedded-market-study.pdf

Embedded SystemsSoftware is primary job function along with Firmware & System Integration

HW System, PCB, and least-most Chip Design

Industrial control and IoT (sensor networks)

Consumer electronics and communications Sam Siewert 8

https://m.eet.com/media/1246048/2017-embedded-market-study.pdf

Embedded ProgrammingC/C++ASMPython - prototyping and verification

Real-time is most common capability with DSP and Networking

Analog signal processing for Sensor AFE (Analog Front End)

Sam Siewert 9https://m.eet.com/media/1246048/2017-embedded-market-study.pdf

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Real-Time Service TypesTypes of Services– Hard Real-Time (Flight Software, Anti-Lock Braking)– Soft Real-Time (Multi-media, Audio, Video, Virtual Reality)– Best Effort (E.g. Desktop Applications)– Isochronal Hard Real-Time (Digital Feedback Control

Systems) – Isochronal Soft Real-Time (Continuous Media, Video,

Audio)

Real-Time Service Types in Terms of Utility– Utility Curve Shows Value/Harm of Response Over Time

From ReleaseBoth Before and After Deadline Relative to Release

– Full Utility - Service Performs as Required– Zero Utility- Service is Not Provided

Drop-out Causes No Harm– Negative Utility

Harm to System and/or User and Significant Loss of Assets

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Hard Real-Time Service Utility

Deadline

Utility

Time

Release

100%

0%

After Deadline, Utility is Negative

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Soft Real-Time Service Utility

Deadline

Utility

Time

Release

100%

0%

F(t)

After Deadline, Utility DiminishesAccording to Some Function F(t)

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Best Effort Service Utility

Deadline Does Not ExistUtility

Time

Release

100%

0%

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Isochronal Hard Real-Time UtilityDeadline

Utility

Time

Release

100%

0%

After Deadline, Utility is NegativeBefore Deadline, Utility is Negative

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Isochronal Soft Real-Time UtilityDeadline

Utility

Time

Release

100%

0%

After Deadline, Utility is < 100%Before Deadline, Utility is < 100%

F(t)F(t)

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Anytime Utility Curve

DeadlineUtility

Time

Release

100%

0%

After Deadline,Utility is Negative or Zero

Before Deadline,Utility is </= 100%

F(t)

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OutlineReal-Time Services – The RT Embedded System Resource Space

CPUIOMemory

– Service Release Timeline– Intro to Timing diagrams– Intro to Traces– Safe Real-Time Resource Utilization Bounds

High-Level Design– Input Interfaces– Output Interfaces– Services– Real-Time Requirements (Ci, Ti, Di for Si)– Decomposition from Services to Functions and Vice Versa– Methodologies

Structured Analysis/DesignUMLSDL

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View of RT CPU ResourcesCPU– How Fast? - Clock Rate– How Efficient? - CPI = Clocks Per Instruction or IPC = Instructions

Per ClockPipeline Stalls Due to Hazards – e.g. Read Data DependencyCache Misses, Write Buffer Stalls, Branch Mispredicts

– How Complex? – Ci = Instruction Count on Service Longest PathIdeally Ci DeterministicWCET – Worst-Case Execution Time

– Longest, Most Inefficiently Executed Path for Service– Not Directly Related to Response Time

IO LatencyInterference by Higher Priority Services and Interrupts

– How Often? – Ti = Service Release Period

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View of RT IO ResourcesIO

– Latency?Arbitration Latency for Shared IO Interfaces – e.g. BusRead Latency

– Time For Data Transit From Device to CPU Core Register, TCM or L1 Cache– Register, Tightly-Coupled-Memory, and L1 Cache Considered Zero Wait-State Single

Cycle Access– Bus Interface Read Requests and Completions

Split TransactionDelay

Write Latency– Time for Data Transit From CPU Core to Device– Posted Writes Prevent CPU Stalls– Posted Writes Require Bus Interface Queue

– Bandwidth?Average Bytes or Words Per Unit TimeSays Nothing About Latency

– Queue Depth?Write Buffer StallsRead Buffer – Most Often Stalled by Need for Data to Process

– CPU Coupling?DMAProgrammed IOCycle Stealing

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View of RT Memory ResourcesMemory Hierarchy From Least to Most Latency

– Level-1 CacheSingle Cycle AccessTypically Harvard Architecture – Separate Data and Instruction CacheLocked for Use as TCM, Unlocked for Set-Associative or Direct Mapped Cache

– Level-2 Cache or TCMFew or No Wait-States (e.g. 2 Cycle Access)Typically UnifiedLocked for Use as TCM, Unlocked to Back L1

– MMR – Memory Mapped Registers– Main Memory – SRAM, SDRAM, DDR

Processor Bus Interface and ControllerMulti-Cycle Access Latency On-ChipMany-Cycle Access Latency Off-Chip

– MMIO – Memory Mapped IO Devices– Non-Volatile Memory

Processor Bus Interface and ControllerSlowest Read/Write Access, Most Often Off-ChipRequires Algorithm for Block Erase

– Interrupt Upon Completion– Poll for Completion

Total Capacity for Code, Data, Stack, HeapAllocation of Data, Code, Stack, Heap to Physical Hierarchy

– Most Frequently Accessed In Lowest Latency Segment– Moving Blocks or Cache Lines/Sets– Prefetches

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Conceptual View of RT ResourcesThree-Space View of Utilization Requirements– CPU Margin?– IO Latency (and

Bandwidth) Margin?– Memory Capacity (and

Latency) Margin?

Upper Right Front Corner – Low-MarginOrigin – High-Margin

CPU-Util

IO-Util

Memory-Util

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A Service Release and ResponseCi WCETInput/Output LatencyInterference Time

EventSensed Interrupt Dispatch Preemption Dispatch

Interference

Completion(IO Queued)

Actuation(IO Completion)

Input-Latency

Dispatch-Latency

Execution Execution

Output-Latency

Time

Response Time = TimeActuation – TimeSensed(From Release to Response)

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Real-Time ServicesTheoretical Timing Diagrams

– Lehoczky, Shah, and Ding Theorem (Timing over Longest T)

– Look at Timing Over LCM of All Periods

– Simple for Small Number of Services

Necessary and Sufficient Proof of Feasibility

22112 / TCCTT ≤+

T2T1

C.I.

S1

S2

22112 / TCCTT ≤+

LCM

Trace Tools for Real Timing– Software Trace Tools

(WindView), SystemViewerLinux Trace Toolkit

Given: Services S1, S2 with periods T1 and T2 and C1 and C2, Assume T2 > T1E.g. T1=2, T2=5, C1=1, C2= 1, then if prio(S1) > prio(S2), we can see that the service set is feasible by diagramming.

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Safe Resource Utilization BoundsCPU

– How Much Margin to Guarantee Deadlines Will Be Met for a Set of Services?Accounting for InterferenceHow Well Can CPU Be Scheduled?

– Sufficient – RM LUB– Necessary and Sufficient – Lehoczky, Shah, Ding Theorem– If CPU Was the Only Resource Needed …

Priority InversionEfficiency

IO– Is Bandwidth a Guarantee?– What About Latency?

Memory– Allocation in Hierarchy By Latency Requirements– Total Capacity– Dynamic Memory Allocation?– Queue Depths– Producer/Consumer Rates – Matched?

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High-Level DesignInput Interfaces – HW Design and CharacterizationOutput Interfaces – HW Design and CharacterizationServices – What Are They?Real-Time Requirements (Ci, Ti, Di for Si)– Identification of Services– Frequency of Service Requests– Execution/Processing Complexity– Deadline for Response

Decomposition from Services to Functions and Vice VersaSystem-Level Methodologies– Structured Analysis/Design– UML– SDL

Space Transportation System – Shuttle Example (1989-1992)

Ascent and Entry Guidance - PASSArchitecture of the Space Shuttle Primary Avionics Software System – Gene D. Carlow [Canvas]Phases of Flight Divided into Major Modes [E.g. 601]Each Mode Has Real-Time Scheduling– Cyclic Executive with High, Medium and Low Frequency– Each Executive is a “Loop” with Interrupts to Preempt it– Services are Implemented on an Executive

E.g. Control and Sensors in HFE (Stability, Monitoring, Health & Safety)E.g. Navigation in MFE (State Estimation from Multiple Sensors over Time)E.g. Guidance in LFE (Long Term Targets)

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DATA CHASER Shuttle Payload Example(1994-97)

Rapid Development– 1 Year from Concept to Launch– Demonstration of AI Real-Time Automation for Payloads– Anytime Algorithms Used for On-Line Planning/Re-planning Services

Motorola 68EC030Custom FPGA IO Boards for 3 InstrumentsFairly Low Resource Utilization (Low Frame Rates)– RS232 9600 baud Command/Telemetry– RS422 1 Mbit / sec Downlink for Science Data

Flown on STS-85Automation Demonstration SuccessfulScience Return MinimalDeveloped by CU for JPL

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SIRTF High Level Design Example(1997-2000)

CPU Bound – 95%+ Loading for Sky-Scan Mosaic Images– Data Compression– Synchronization Between Space Telescope Slew and Imaging

IO Bound – 95%+ VME Bus Loading for Sky-Scan– 3 Synchronized Detectors Operating Concurrently– FIFO interface Block Transfer

Write-through DMA prevented use of DMARead/Write Multiple Instruction on PowerPC (Programmed IO)

– Data Compression and Grouping for DownlinkAllocation of Functions/Service to:– 2 Hardware State Machines (Actel FPGA)– 23 VxWorks Tasks

In Operation Now … (www.sirtf.caltech.edu)