cc_man

RTDS

RTDS

R E A L T I M E D I G I T A L S I M U L A T O RC O N T R O L S L I B R A R Y M A N U A L

( R S C A D V E R S I O N )

JULY 2013

Technologies

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TABLE OF CONTENTS

1 OVERVIEW 1.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.1 Introducing the RealTime Digital Simulator 1.1. . . . . . . . . . . . . . . . . . . . . . . . . . . .1.2 Control System Modelling 1.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3 List of Controls Library Function Blocks (by Group) 1.3. . . . . . . . . . . . . . . . . . . . . .

2 GENERAL USAGE 2.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.1 Creating a Control System Model 2.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2 Running a Control System Model Simulation 2.9. . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3 Interfacing External Signals 2.10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.4 Numerical Considerations 2.13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5 Signal Time Delays 2.16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.6 Execution & Communication Time 2.18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7 Interconnection to Power System Components 2.19. . . . . . . . . . . . . . . . . . . . . . . . . . .

3 FUNCTION BLOCKS 3.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .MATH 3.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .LOGIC 3.22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SELECTOR 3.32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .LIMITER 3.38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DATA CONVERSION 3.45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .INPUT/OUTPUT 3.52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .METERS 3.74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TRANSFER FUNCTION 3.80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TIMER 3.85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SIGNAL PROCESSING 3.94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SIGNAL GENERATOR 3.117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .LOAD 3.122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .MISCELLANEOUS 3.128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 GENERATOR CONTROLS 4.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.1 Connection of Generator Controls to RTDS Generator Model 4.2. . . . . . . . . . . . . . .4.2 Automatic Initialization 4.5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.3 Internal Variable Monitoring 4.6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.4 PSCAD/RunTime Components 4.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5 Block Diagrams 4.8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IEE2ST PSS 4.10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEEST PSS 4.12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PSS2A 4.14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EXAC1 AVR 4.16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EXAC1A AVR 4.18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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EXAC2 AVR 4.20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EXAC3 AVR 4.22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EXAC4 AVR 4.24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EXDC2 AVR 4.26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EXST1 AVR 4.28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EXST1A AVR 4.30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EXST2 (A) AVR 4.34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EXST3 AVR 4.37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EXPIC1 AVR 4.39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEET1 AVR 4.42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEET2 AVR 4.44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEET3 AVR 4.46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEET4 AVR 4.48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEET5 AVR 4.50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEEX1 AVR 4.52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEEX2 AVR 4.54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEEX2A AVR 4.56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DC1 AVR 4.58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DC2 AVR 4.60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .REXS AVR 4.62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .AC7B AVR 4.64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GAST GOV 4.66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .HYGOV GOV 4.68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEESGO GOV 4.71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEEG1 GOV 4.73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEEG2 GOV 4.76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IEEEG3 GOV 4.78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TGOV1 GOV 4.81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .WEHGOV GOV 4.83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .HYGOV4 GOV 4.86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GGOV1 GOV 4.89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TGOV5 GOV 4.92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 COMPLEX NUMBER MATH FUNCTIONS 5.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 SEQUENCER 6.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.1 Introduction 6.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.2 Parameter Menu 6.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.3 Sample Case 6.8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 GTNET Components 7A.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7A GTNET GSE 7A.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7A.1 GOOSE Mode 7A.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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7A.2 GSSE Mode 7A.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7A.3 RSCAD Draft Component and Parameter Entries 7A.3. . . . . . . . . . . . . . .

7B GTNET Comtrade 7B.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7B.1 Comtrade Files and Data Format 7B.1. . . . . . . . . . . . . . . . . . . . . . . . . . . .7B.2 RTDS Files 7B.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7B.3 Linear Interpolation 7B.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7B.4 Data Scaling 7B.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7B.5 Operating in PreTransient (prefault) and PostTtransient (postfault) datamode 7B.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7B.6 Playback 7B.5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7B.7 RSCAD Draft Component and Parameter Entries 7B.6. . . . . . . . . . . . . . .7B.8 Sending Comtrade Signals to a Peripheral Device 7B.11. . . . . . . . . . . . . .

7C GTNET DNP 7C.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7C.1 Description 7C.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7C.2 DNPRTDS Point Mapping 7C.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .7C.3 RSCAD Draft Component and Parameter Entries 7C.8. . . . . . . . . . . . . . .7C.4 MultiRack Communication 7C.10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7D GTNET PLAYBACK 7D.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7D.1 Model Description 7D.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7D.2 Playback Data File Format 7D.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7D.3 Playback Operation 7D.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7D.4 RSCAD Draft Component and Parameter Entries 7D.3. . . . . . . . . . . . . . .7D.5 GTNET Playback Example Cases 7D.10. . . . . . . . . . . . . . . . . . . . . . . . . . .

7E GTNET SV 7E.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7E.1 Sampled Values Communication 7E.1. . . . . . . . . . . . . . . . . . . . . . . . . . . .7E.2 RSCAD Draft Component and Parameter Entries 7E.2. . . . . . . . . . . . . . .

7Ex GTNET SVse 7Ex.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Ex.1 Sampled Values Special Edition Communication 7Ex.1. . . . . . . . . . . . . .

7F GTNET PMU 7F.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7F.1 Model Description 7F.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7F.4 Calibration of PMU 7F.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7F.6 Configuration 7F.6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7G GTNET104 7G.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7G.0 Minimum Version Requirements 7G.2. . . . . . . . . . . . . . . . . . . . . . . . . . . .7G.1 Model Description 7G.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7G.2 IEC 608705104RTDS Point Mapping 7G.4. . . . . . . . . . . . . . . . . . .7G.3 RSCAD Draft Component and Parameter Entries 7G.8. . . . . . . . . . . . . . .7G.4 MultiRack Communication 7G.10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 MultiFunction Relay Elements 8.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.1 Introduction 8.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.2 MultiThreaded Component 8.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.3 Creating A Protection System Model 8.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.4 MultiFunction Distance 8.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.5 MultiFunction Overcurrent 8.24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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8.6 MultiFunction Differential 8.36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.7 MultiFunction Sequence Component 8.45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8 MultiFunction Impedance Component 8.48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8A MultiFunction Control Elements 8A.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8A.1 Introduction 8A.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8A.2 MultiFunction Breaker Control 8A.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8A.3 MultiFunction Tap Changer Control 8A.10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8B MultiFunctionMeter Elements 8B.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8B.1 Introduction 8B.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8B.2 MultiFunction Sequence 8B.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8B.3 MultiFunction Impedance 8B.5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8B.3 MultiFunction Phasor Measurement 8B.10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Rev. 02: Oct 04

RTDS TECHNOLOGIES INC. 1.1

1 OVERVIEWThis manual provides information regarding the control system component modelswhich are available for use with the RealTime Digital Simulator (RTDS). Specifi-cally, the general usage, capabilities and limitations of the individual models arepresented, as well as how to interconnect the individual components to form controlsystemmodels for simulation. Documentation regarding the interconnection of con-trol system signals to power system components and exporting power system signalsfor use in control systems is also given.

TheRTDSTutorialManualmaybe referenced for fully documented example casesillustrating the use of the RTDS. One of the ways in which the user can gain confi-dence with a specific component model is to stimulate the component in isolation,and observe its response. It is especially useful to perform tests where the compo-nents observed response is directly proportional to its user specified parameters. Forexample, applying basic input signals such as a step or ramp and observing the outputthe user can gain confidence with that control system function block.

Before introducing the individual control system component models available foruse on the RTDS, some fundamental concepts pertaining to the RTDS technology asawholewill be presented. The remainder of this chapter is dedicated to a brief discus-sion of RTDS hardware and software. This discussion is intended to give the user ageneral overview of the technology and to introduce some of the terminology whichis commonly used when referring to the RTDS.

1.1 INTRODUCING THE REALTIMEDIGITAL SIMULATOR ( RTDS )

The RealTime Digital Simulator ( RTDS ) is a special purpose computer initiallydesigned to study Electromagnetic Transient Phenomena in realtime.The RTDS iscomprised of both specially designed hardware and software. RTDS hardware isDigital Signal Processor ( DSP ) based and utilizes advanced parallel processingtechniques in order to achieve the computation speeds required to maintain continu-ous realtime operation.

3PC PROCESSOR CARDS

Power and control system component software is executed using RTDS Processorcards labelled 3PC or RPC. At the present time, October 2004, the 3PC and the RPC

CC OVERVIEW


are the only type of processor cardwhichmay be usedwith theRTDS.Controlsmod-els execute only on the 3PC.

3PCs useAnalogDevices 21064 processors, commonly referred to as SHARCs (Su-perHarvardArchitecture). SHARCprocessors use the IEEEFloating Point standardfor representation of floating point numbers and execute a single instruction every25 nanoseconds

RTDS SOFTWARE

RTDS software includes extensive libraries of power system and control systemcomponents. Power system and control system components may be interconnectedto form the overall system for simulation.

This Manual describes the SHARC based control system components available inthe RSCAD/Draft library named 3PC_Controls. All SHARC control componentsinclude an double line at the bottom of their outline.

G1 + sT

SHARC Component(rtds_sharc_ctl_REALPL)

SHARC Control Component Representation

The naming convention of SHARC controls components is rtds_sharc_ctl_COM-PONENTNAME. It is possible to see a components name by putting the cursorover the ungrouped component in RSCAD/Draft and then hitting the d key. Thecomponents name will be displayed in the message area near the bottom of theRSCAD/Draft screen. Only SHARC control components are included in the default3PC_Controls library.

1.2 CONTROL SYSTEMMODELLING

Although it is possible to interface physical control systems to the RTDS, indeed thisis one of themain features of theRTDS, it is not practical to interface all of the variouscontrols systems required for a given power systemmodel. Controllers such as auto-matic voltage regulators, stabilizers and speed governors are required to operate eachgenerator included in the power system. Physical controllers for power electronic

CC OVERVIEW


based equipment such as HVDC, SVC, TCSCandGTObased bridges are also rarelyavailable to the power system engineer. The operation of such controllers play animportant role in the steadystate and dynamic performance of the power system.The controls component library permits the RTDS user to construct models of con-trol systems using individually function blocks. These function blocksmay be inter-connected to each other, as well as, to power system components.

As a simple example consider the voltage regulation function illustrated below. Inthis case control system function blocks are used to compute the difference betweenthe measured bus voltage and a setpoint and dynamically adjust the generator fieldvoltage tominimize the error. Node voltages, as sine waves, are read from the powersystem and the controllers output, field voltage, is provided to the generator model.

Simple Automatic Voltage Regulator

1.3 LIST OF CONTROLS LIBRARY FUNCTION BLOCKS (BY GROUP)

The graphical libraries included in the DRAFT program include only the most com-monly used controls and power system components. There are many other special-ized components that can be added by right clicking with the mouse in the librarywindow and following the indicated path. If the users library is customized, it maybe saved with a unique name for quick recall in future sessions of DRAFT.

The following list does not include all of the specialized components in the controlslibrary. It is intended only to provide an overview of the main functions available.Furthermore, several varieties of someof the listed components exist. If a specializedcomponent is required that does not exist in the supplied libraries, it can be createdwith the User Defined Component facility.

CC OVERVIEW


MATH GROUP

Summing Junction Multiplication Junction Divide JunctionGain, xN, KxN, xy xyAbsolute Value Square Root Inverse Square Rootex Log Trig (sin,cos,tan)Arctrig(arcsin,arccos,arctan) 3 Phase Sine ATan2F(X) Table Lookup Randommodulo div

LOGIC GROUP

Boolean (AND,OR,XOR) NOT BitShiftBit2Word Word2Bit SR FlipFlopRing Counter Edge Detector Bitmapper

SELECTOR GROUP

Selectmin/Max IfThenElse Range CheckSignal Select Signal Switch Compare c/w Fraction

LIMITER GROUP

Fixed Limits Dynamic Limits Fixed Rate LimitsDynamic Rate Limits DeadBand Low LimitFixed Output Deadband High Limit HysteresisHystersis with time out

DATA CONVERSION GROUP

NEC>IEEE IEEE>NEC INT>REALREAL>INT RADDEG

INPUT/OUTPUT GROUP

Digital Input Digital Output Analogue OutputAnalogue Input DAC16 DITSFront Panel LEDs FDAC DDACDOPTO

METERS GROUP

RMS Frequency Angle Difference3 Phase P & Q Full Wave Rectifier

CC OVERVIEW


TRANSFER FUNCTION GROUP

Integrator Lag LeadLagWashout 2nd Order

TIMER AND COUNTER GROUP

Time Elapsed Time CounterScheduler 1 T Delay Sampled DelayPulse Generator Clock2 Up/Down CounterVariable Delay

SIGNAL PROCESSING GROUP

Zero Crossing Detector Phase Locked Loop (type1)Phase Locked Loop (type 2) Discrete Fourier Transform (DFT)3 Phase Transformation Butterworth Filter3 Phase DQ0 Transformation DQ0 3 Phase TransformationDown Sampler Moving Average FilterSynchronous Buffer Synchronous CounterFIR Filter Sample/Hold

SIGNAL GENERATOR GROUP

Source Fixed Ramp Variable RampFiring Pulse

MISCELLANEOUS GROUP

Stop Plot Update Set Flag 0SendT0 Pst

GENERATOR CONTROLS GROUP

IEE2ST PSSEXAC1 AVR EXAC1A AVR EXAC2 AVREXAC3 AVR EXAC4 AVR EXDC2 AVREXST1 AVR EXST2 AVR EXST3 AVREXPIC1 AVR IEEET1 AVR IEEET2 AVRIEEET3 AVR IEEET4 AVR IEEET5 AVRIEEEX1 AVR IEEEX2 AVR IEEEX2A AVRGAST GOV HYGOV GOV IEESGO GOVIEEEG1 GOV IEEEG2 GOV IEEEG3 GOVTGOV1 GOV

LOAD GROUP

Load ModelZIP Calculation Exponential Load Calculation

Rev. 02: Oct. 04


2 CONTROLS COMPILER USAGEControl systemmodels for simulation using theRTDScan be constructed using basiccontrol system function blocks. This Chapter documents the general features of theControls Compiler software.

2.1 CREATING A CONTROL SYSTEMMODEL

RSCAD/DRAFT

Control system component function blocks can be accessed from RSCAD/Draft byloading the library named 3PC_Controls. The same stretchable wire componentand jumper components that are used to interconnect power system components areused to interconnect control system components. Inputs to a component are identi-fied by an arrow and outputs by a line. All component inputs must be connected toan output signal. A compile time errorwill be generated if an input signal is left float-ing. Component output signals need not be connected to anything.

N1 |X| max

N2 |X|

N3 |X|

maxVmaxVa

Vb

Vc

input signals are identified byan arrow.

PROCESSOR ASSIGNMENT

Sincemost control components require only a relatively small amount of executablecode, many control system components can be assigned to the same SHARCproces-sor. Controls components are assigned to a processor by setting their Proc parame-ter in RSCAD/Draft. The assigned processor will be allocated in the rack corre-

CC USAGE


sponding to the RSCAD/Draft subsystem page in which the component is placed.Assignment of the actual processorwithin the rackwill usually notmatch the numberentered for the Proc parameter, however. In other words, the processor referred toin the Proc parameter is a virtual processor. The RTDS Controls Compiler will as-sign controls processors to the first available non dual 3PC unit in the rack. Sincecontrol components do not make use of the features available in a dual 3PC unit, thedual units are left for other components which may be assigned later in the compileprocess. If a nondualunit cannot be found within the rack the controls componentswill be assigned to a dual 3PC.

The user is able override the search for the first nondualunit and to force assignmentof control components to a specific processor by using the ASSIGN CONTROLSPROCESSOR block. This block (rtds_sharc_ctl_PROCASN) forces the assign-ment of all control function blocks with the same value of Proc to a specifiedSHARC processor.

N1 |X| 5.01X

Proc=1 Proc=5 Proc=8

abs gain inverse

If the circuit above represents the only control system components on a givenRSCAD/Draft page, then the abs function blockwill be assigned to the first availableprocessor residing on a nondual3PCcard, the gain block on the next available proc-essor and the inverse function on the next after that. For example, if the rack towhichthe subsystemwas assigned contained a total of five 3PC cards with the first and sec-ond arranged as dual and the third and fourth arranged as dual and the fifth as a singlethen the abs block would be assigned to 3PC #5A, the gain block to 3PC #5B and theinverse block to #5C. If the rack contained only four 3PC cards, again with the firstand second and third and fourth arranged as dual then the abs block would be as-signed to 3PC #1A, the gain to 3PC #1B and the inverse to 3PC #1C.

By placing ASSIGN CONTROLS PROCESSOR blocks onto the RSCAD/Draftpage, virtual control processors can be forced onto actual 3PC processors. The AS-SIGN block must not be used to assign more than one virtual controls processor toan actual processor or a compile time error will result.

In this example, delays between the execution of each block have been introducedby forcing each component to run in a separate processor. The consequences of thisare discussed in Section 2.5.

CC USAGE


N1 |X| 5.01X

Proc=1 Proc=5 Proc=8

abs gain inverse

ASSIGNCONTROLS

PROCESSOR #1

to 3PC 1A

ASSIGNCONTROLS

PROCESSOR #5

to 3PC 1B

ASSIGNCONTROLS

PROCESSOR #8

to 3PC 1C

abs block > 3PC 1Again block > 3PC 1Binverse block > 3PC 1C

PRIORITY ASSIGNMENT

The order in which control function blocks assigned to the same processor are exe-cuted can be very important. Assignment of blocks in the non optimum order mayresult in unnecessary signal time delays. The Pri parameter associated with controlsystem function blocks can be used to manually set the order of execution for func-tion blocks assigned to the same processor. A component with Pri= 1will be execut-ed before a component with Pri= 2. The user may leave gaps when assigning valuesto the Pri parameter. For example, assigning values of 1, 5, 10, 15 ... to functionblocks is acceptable. It is probably a good idea to leave gaps between Pri values soas to allow blocks to be inserted at a later time. Blocks assigned the same Pri valuewill be executed in randomorder. For example, a set of blocks assigned the followingPri values

Block #1 Pri= 1Block #2 Pri= 5Block #3 Pri= 5Block #4 Pri= 10

may be executed in the order Block #1, Block #2, Block #3 and Block #4, or in theorder Block #1, Block #3, Block #2 and Block #4.

Automatic priority assignment by the Controls Compiler software is available andusually preferable. In this case the Pri value should be set to 1 for each controls func-tion block and the automatic ordering option should be turned on in RSCAD/Draft.

CC USAGE


To access the Auto/Manual ordering option select the OPTIONS button with a rightclick and hold in the circuit area of RSCAD/Draft. The following popup menu willappear.

Processor number andpriority can be displayed inRSCAD/Draft by a left clickandhold on the File label in upper left hand corner of the screen and sliding down to Op-tions. The followingmenuwill appear. Select the Showcontrols priority&processor# box. The box can be deselected by clicking on it again if it is already selected.

Once the simulation case has been compiled, the order inwhich the components havebeen allocated, as well as, the actual processor to which they have been allocated canbe seen by reading the MAP file. The actual processor and the order of executionare listed here.

CC USAGE


Alternatively, a graphical display of the component order for each processor may beseen by selecting the box with the vertical bars at the top of the Draft screen.

Note that the graphical display will only show the correct component order after thecase has been compiled. In addition to ordering, this display provides informationabout the total length of time taken to complete execution of all components allocatedto a particular processor. This information is useful for ensuring that the longest con-trols processor execution time is not impacting the length of the overall time step ina case. It is also useful for balancing the execution load on controls processors whenmore than one is required in a case. Note that the processor numbers shown refer tothe virtual controls processor number and not the actual one.

In many cases, it is useful to have selected portions of a large control system runningon separate controls processors. The user can arrange the allocation of different partsof the control to different processors so that the resultant time delays do not degradeperformance. To guarantee that particular controls components are given the sameprocessor number, the selected controls can beGrouped inDraft and then all changedwith anEdit Common command. Edit Common is available only on grouped compo-nents and changes all variables with the same name in the Group. It is performed bya right clickandholdon the Group, sliding down to Edit and across to Common.In this case, the variable Proc must be entered, followed by the desired processornumber.

IMPORT/EXPORT COMPONENTS

IMPORT and EXPORT components are used to exchange control signals betweencontrol blocks assigned on different subsystems. An EXPORT component(rtds_sharc_ctl_EXPORT)must be assigned a unique name (ie. a control signal mayonly be exported once). One or more IMPORT components (rtds_sharc_ctl_IM-PORT) given the same name as the corresponding export component may be con-nected to input wires for components on different RSCAD/Draft subsystem pages.An IMPORT/EXPORT pair which spans RTDS racks which are not directly con-nected by an InterRackCommunication (IRC) channel will result in a compile timeerror. The IMPORT component requires that the signal type be specified (FLOATor INT). Only upper case letters may be used.

CC USAGE


SIG1|X| 5.01X

circuit in subsystem #1

SIG1

export

|X|

circuit in subsystem #2import

Import/Export component pairs must also be used to bring monitored signals pro-duced by power system components into control system components. In the case ofnode voltages andmonitored outputs there is no wire to which the EXPORT compo-nent may be attached. In this case an EXPORT component with a name matchingthe power signal may be placed anywhere on the RSCAD/Draft page which also in-cludes the relevant power system component. Alternatively, an IMPORT/EXPORTcombination component (rtds_sharc_ctl_IMPEXP) may be used. This component issimply a single component which represents both the IMPORT and EXPORT com-ponents together.

I1210.0

N2 N1

N2 I12

N1

N2

+V12

I12 0.1453I12PU

NodeVoltageN2 andBranchCurrent I12are exported from the power system andimported to controls using separate IM-PORT and EXPORT components. NodeVoltage N1 uses a combined IMPORT/EXPORT component.

import/export

export export

import

import

CC USAGE


A

B

C

SOURCE MODEL: MONITORING SUBMENU

PSRCimport/export

0.01PPU

QSRCimport/export

0.01QPU

IMPORT/EXPORT components areused to bring monitored signals frompower system components into controlsystem components.

SHARC

src

AC Type

230.0 kV

HIERARCHY COMPONENT

The Hierarchy Component may be used to schematically separate circuit diagramsinto a number of blocks. Separate Hierarchy components may be allocated for eachmajor control function and may be nested so that the controls component structurereflects the actual controls.

Control signals which are common between separate Hierarchy components or be-tween the DRAFT main page and a Hierarchy component should be identified withwire labels.

A Hierarchy component may be made to appear as an actual control block as shownbelow. TheHierarchy componentmay be shaped as desired and given a color includ-ing white. Labeled wires can be drawn to the edge of the box as shown.

CC USAGE


If several components of the same type are needed, the Hierarchy box can be copiedand placed repeatedly in the circuit. However, wire labels must be changed in eachinstance to match the correct external signals.

Controls componentswithin theHierarchy run on the same rack as any other controlson the main page. They may be grouped to run in a seperate processor, if desired.

COMPILING

Once the control system circuit has been completely drawn, the case must be com-piled. This done in the same manner as compiling a power system or mixed powerand controls case. If the case has not been compiled before, the user is required toenter a file name. Note that the size of the time step and the starting rack number aregiven default values.

The compiling procedure is done in two steps. Firstly, the RSCAD/Draft softwarecreates data files (case.dta and case.dtp). The case.dtp file is used as input by theRTDS compiler (rtdspc) which in turn generates the following text (ASCII) files

case.map Information regarding the allocation and orderingof components to processors. The minimum timestep is listed at the end of the .map file.

case.inf A list of all input and output variables and theirinternal RTDS addresses.

case.sib The default Batch file for RSCAD/RunTime. Thisfile is updated when SAVE is selected in RSCAD/RunTime.

case_r1 ... One such file for each subsystem. The _r# refersto the rack number. Each file contains the dataand executable code for the RTDS processors.

Although all of the files are readable, the .map file is the only one which containsinformation pertinent to the user.

CC USAGE


2.2 RUNNING A CONTROL SYSTEMMODEL SIMULATION

Once the circuit for simulation has been successfully compiled (no errors) inRSCAD/Draft the case is ready for simulation. Running cases which include con-trols is not much different than running power system simulation cases. An empty.sib file, which can be loaded using the File>Open command inRSCAD/RunTime,is created by the compile process.

MONITORING CONTROL SIGNALS (WIRE LABELS)

In order for control signals to be viewable using meter or plot components inRSCAD/RunTime, the wire must be labelled using a wire label component (wirela-bel). Any control signal thus labelled will appear under the Subsys-tem#>CTLs>Vars group when an output component is created. The created com-ponent will automatically display FLOAT or INT depending upon the type of signalbeing monitored.

|X| 5.01X

S1 S2

Signals S1 and S2 may be monitored using RSCAD/RunTime

Create > Plot

CC USAGE


RSCAD/RUNTIME INPUT COMPONENTS

Control system input signals may be connected to RSCAD/RunTime input devicessuch as sliders, switches, push buttons and dials. The input components are placedin RSCAD/Draft and assigned a unique names. Corresponding components maythen be placed in RSCAD/RunTime in order to dynamically set values to the controlsignals.

5.0

slider

0

1switch

0

dial

5

button

0

1

RSCAD/Draft Input Components

Right clickandholdAnd select

OR Select one of these

Initial values for each input component may be set from within RSCAD/Draft. Thespecified initial valuewill be assigned to the control signal towhich the input compo-nent is connected even if the corresponding input component is not created inRSCAD/RunTime. Switches and Push Buttons may be specified to produce REALor INTEGER type data. Dial components can be configured as REAL, INTEGERor HEX. Sliders only produce REAL values.

2.3 INTERFACING EXTERNAL SIGNALS

ANALOG I/O

The following control function blocks are available to write control signals to ana-logue output ports available on the RTDS.

CC USAGE


rtds_sharc_ctl_AOUT front panel analogue output portrtds_sharc_ctl_DAC16 3 channel 16 bit D/A output boardrtds_sharc_ctl_FDAC Optically isolated 6 channel 16 bit D/Artds_sharc_ctl_DDAC Optically isolated 12 channel 16 bit D/A

3PC cards do not include onboard analogue input capability. As such an externaloptical analoguedigital converter board (OADC) is required. The following com-ponent can be used to read in external analogue signals from the OADC board

rtds_sharc_ctl_OADC 6 channel 16 bit A/D input board

Note: the OADC, FDAC andDDAC communicate with the 3PC card via the opticalport which is only available to the C processor on the 3PC. Thertds_sharc_ctl_OADC, rtds_sharc_ctl_FDAC and rtds_sharc_ctl_DDAC functionblocks may thus only be assigned to a C processor.

DIGITAL I/O

The A and B processors on 3PC cards each have direct access to a digital I/O port.Sixteen digital input and sixteen digital output signals are available at each port. Thefollowing componentsmay be used to read/write control signal data to the digital I/Oport.

CC USAGE


rtds_sharc_ctl_DIGINP Read signal from digital input portrtds_sharc_ctl_DIGOUT Write signal to digital input portrtds_sharc_ctl_DITS Digital Input Time Stamp Cardrtds_sharc_ctl_DOPTO Digital Optical Isolated I/O

TheDITS card is used to acquire digital inputs from external firing pulse generators.It not only signals the arrival of a firing pulse, it also generates a signal called Fracthat records the arrival time of the firing pulse within a time step.

The DOPTO card is used to optically isolate digital inputs and outputs. It connectsvia ribbon cable to the DOPTO CC and the DOPTO OC for convenient connectionto terminal blocks. Also, the DOPTO communicates with the 3PC card with linkports to processor C and leaves the Digital I/O ports free for use with the A andB processors.

CC USAGE


2.4 NUMERICAL CONSIDERATIONS

Sharc control component input and output signals may be either REAL (IEEE Float-ing Point) or INTEGER. A control components input or output wire may be of afixed type or may be changed by the setting of a parameter associated with the com-ponent. Connection of a REAL signal to an INTEGER signal results in a compiletime error.

TPC & 3PC MIXED MODE OPERATION

The processors used on TPC cards (NEC 77240) and on 3PC cards (ADSP21062)within RTDS racks use a different format for representation of floating point num-bers. In order to permit simulation cases to run when both TPC and 3PC cards areused in the same simulation case, 3PC cards are equipped with NEC>IEEE andIEEE>NEC format conversion hardware. NEC processors are not able to convertfloating point data to and from IEEE format.

If the RTDS compiler recognizes that a simulation case will run on racks which in-clude both TPC and 3PC cards the floating point mode is automatically set to NEC.This results in all power system components running on SHARC processors to con-vert their output and input fromNEC to IEEE format. In this way all external powersystem floating point data is in NEC format.

Control system components running on TPC cards also read and write floating pointdata only inNEC format. Control system components running on 3PCcards, howev-er, read and write only IEEE format data. In order to exchange floating point databetween SHARC control components and power system components or NEC con-trol components the user must place IEEE>NEC(rtds_sharc_ctl_IEEE2NEC) andNEC>IEEE (rtds_sharc_ctl_NEC2IEEE) conversion function blocks. These con-version blocks are only available in the SHARC controls library. NEC>IEEEcon-version blocks should be allocated the highest priority (lowest Pri values) so that theyare executed before any other control blocks. NEC>IEEE conversion blocksshould be given the lowest priority (highest Pri value) so that they are executed afterall of the other control blocks.

CC USAGE


10.0

N2 N1

N1

N2

+

10.0

N2 N1

N1

N2

+

5.0 EFIELD

to generator model

...

...

Simulation Case runon RTDS racks withno TPC Cards.

Same case as above runon RTDS racks with acombination of TPC and3PC racks.

...NEC

IEEE

NECIEEE

NEC Format IEEE Format

5.0 EFIELD

to generator model

...IEEE

NEC

IEEE FormatNEC Format

FLOATING POINT RESOLUTION

Sharc processors use 40bit extended precision floating point formatwith 32bits allo-cated to the mantissa and 8 bits to the exponent. Floating point registers within theSharc processor, as well as, Sharc internal memory and 3PC external memory are allable to store 40 bit data. Communication between processor cards, however, uses theRTDS rack backplanewhich is 32bits. Anydata transferred between processor cardsis truncated from 40 bits to 32 bits.

CC USAGE


ADSP21062

ADSP21062

ADSP21062

SHARC A

SHARC B

SHARC C

QUAD PORT

MEMORY

BACKPLANE

40 BIT DATA 40 BIT DATA

40BITDATA

32BITDATA

32 BIT DATA

3PC CARD

RTDS RACK BACKPLANE

There are circumstances where the 40 bit floating point representation does not pro-vide enough accuracy. Consider the casewhere an integrator takes as input the differ-ence between a measured quantity and a setpoint. Applying trapezoidal rule in-tegration, the integrator output is computed as follows

Y(t)= t / 2T * [X(t) + X(tt)] + Y(tt)X(t)= new input

X(tt)= input from previous timestepY(tt)= output from previous timestepT= integrator time constant

t= integration timestepThe fraction t/2T can be very small since t is usually on the order of s and T canbe on the order of seconds. It is possible that the magnitude difference between theoutput term (y(tt)) and the input term (t / 2T * [x(t) + x(tt)] ) is greater thanthe processors floating point precision. In such circumstances the integrator outputremains at the initial output value even thought its input is nonzero.The Integrator controls component includes an extended precision mode which de-tects that a nonzero input resulted in no change to the output and accumulates theinput term until the value of y(t) changes.

CC USAGE


2.5 SIGNAL TIME DELAYS

Due to the parallel processing aspects of the RTDS, there are circumstances wherethere may be delays between the time when a signal is written out from a componentand when that signal is read in by another component. Timestep delays will alsobe introduced when control system circuits include feedback paths.

All RTDS processors used for a particular simulation case operate in lock step. Eachprocessor receives the same timestep signal and starts its computations at the sametime. Once all processors have completed their computations for the given timestep, data is communicated fromeach processor to all others. For example, data com-puted by Processor A on 3PC #1 will be transferred so that in the next timestepallprocessors on the same rack will have access to that data. In cases where the com-puted signal is required as input on other racks the data will be transferred and madeavailable to all processors on the other rack as well. Only named control signals aretransferred. Signal wires not labelled with a wire label are stored in the processorsinternal memory and are not available for input by other processors, nor are thosesignals available for metering in RSCAD/RunTime.

Controls components are solved sequentially on each processor. Time is only in-cremented at the start of each new timestep. There are no timedelayswhen an out-put signal from a component which is executed prior to the component which re-ceives the signal as input when the two components are assigned to the sameprocessor.

|X| 5.01X

S1 S3

Signal S3 based on S2(t), S2(t) based on S1(t)

S2

Pri=1 Pri=2 Pri=3

|X| 5.01X

S1 S3

Signal S3 based on S2(t), S2(t) based on S1(tt)

S2

Pri=3 Pri=1 Pri=2

In the case where components are executed on processors residing on different 3PCcards, the input signal will be based on the output computed from the previous timestep. Outputs computed on one processor card are communicated to other processorcards at the end of each time step. Using the example above, consider the case whenthe abs and gain (*5.0) blocks are executed on 3PC 1A and the 1/X block on 3PC 2A.In this case signal S2(t) is computed based on input S1(t). Signal S2, however, is notavailable to processors on card 3PC 2A until the next timestep. Signal S3 is com-

CC USAGE


puted one timestep after signal S2. If signals S2 and S3 are plotted on a commongrid in a RSCAD/RunTime plot, it will be observed that signal S3 changes one timestep later than S2.

|X| 5.01X

S1 S3S2

Proc=1 (3PC 1A) Proc=1 (3PC 1A) Proc=4 (3PC 2A)Pri=1 Pri=2 Pri=3

timestep #1

Proc #1 (3PC 1A)

|X| Block

Gain *5 Block

Proc #1 (3PC 1A)

1/X Block

communication interval

timestep #2

S2(t)

. . .

1/X Block

S2(tt)

S1(t)

The situation is somewhat more complex for the case when controls components areassigned to blocks which are executed on processors residing on the same 3PC proc-essor. Since all three processors residing on a 3PC share a single block of externalmemory, signals written to external memory by one processor may be accessed bythe other processors on that card during the same timestep. However, only controlblocks which are executed after completion of the block producing the output willread the (t) value. Blocks which use the signal as input, but are executed before theblock producing the output has completed will receive the (tt) signal. The sharedmemory will not permit reading andwriting at the same time thus preventing invaliddata from being read as input.

CC USAGE


Synchronized communication between processors residing on a 3PC card is possibleusing link ports. Each of the A, B and C processors can communicated to theother two using link ports. A control components named rtds_sharc_ctl_LPWRwillwrite a signal to the designated link port channel and the rtds_sharc_ctl_LPRD com-ponent is used to read the data. The link port hardwarewill cause the reading proces-sor to wait until the data has been received from the writing processor.

3PC cards arranged as dual units are able to use link port communication betweenprocessors on the two cards. Only AA,BB and CC link port communication ispossible between processors which are part of a dual 3PC unit.

2.6 EXECUTION & COMMUNICATION TIME

All computation and communication must be complete within the specified timestep. As the number of control components allocated to a processor increases thecomputation time required by that processor increases. The processor whose com-putation time is longer than all others determines the minimum timestep that canbe used to maintain realtimeoperation of the RTDS. The computation time associ-ated with each control component is given by the _SHINST_ variable in the COM-PUTATION section within the components definition. The _SHINST_ variable isequal to the number of instructions required to execute the longest path through thecomponents code. Since some components include ifthenelsestructures the timetaken to execute the code may vary from timestep to timestep. Since the Sharcprocessor executes an instruction every 25 nanoseconds the time required to com-plete a block is equal to _SHINST_* 0.025 s.Once all processors participating in a simulation case have completed their execut-able code, data is communicated from one processor card to all others on the rack.0.125 s is required to transfer each data word. Each control signal identified withawire labelmust be transferred. Signals not identified with awire label, but requiredas input on another 3PC card, signals exchanged between racks and signals ex-changed between control system and power system components must also be trans-ferred.

The longest computation time, as well as, communication time are listed at the bot-tome of the .map file produced by theRTDScompiler. Processor loading can be seenby opening the processor usage window in RSCAD/Draft (see Section 2.1 above).

HIDDEN TRANSFERS

Control signals that are not required as input by any other control system block orpower system component and are required only formonitoring in RSCAD/RunTimeare transferred as hidden transfers. Such transfers are only allocated if the RTDS isequipped with WIF cards (not WIC cards). Hidden transfers occur after the normalcommunication period when the processors have begun the next timestep. Sincethese transfers occur in parallel with a computation interval they do not add to thetime step. For every 8 signals allocated as hidden in a single rack simulation case,the timestepmay be reduced by 1 s. Signals allocated as hidden are identified in.map file produced by the RTDS compiler.

CC USAGE


2.7 INTERCONNECTION TO POWER SYSTEM COMPONENTS

Interconnection of signals between control system components and power systemcomponents can be done using IMPORT/EXPORT components, by signal name orby direct connection using wire components. The method to be used depends on thetype of power system component to which the control signals are to be interfaced.

Named signals computed by power system components can be attached to controlsignal wires using an IMPORT/EXPORT component pair. The name given to theIMPORT/EXPORT components must be upper case and must match the name as-signed to the variable in the power system component menu. Signals such as moni-tored branch or breaker currents, node voltages and monitored signals produced bypower system components can all be attached to control signalwires using IMPORT/EXPORT component pairs. A timestep delay is introduced when a signal is pro-cessed through a control circuit. For example, if node voltage N1 is Imported intoa control system gain (*1.0) block and both the node voltage and the gain block out-puts are plotted on the same grid in PSCAD/RunTime the control signal will bedelayed by one timestep.The connection between control signals that are used as input to power system com-ponents can be made using a control signal wire label component. The wire labelnamemust be the same as the name specified for the signal in the power system com-ponent menu. If the control component producing the signal resides on another sub-system then an IMPORT/EXPORT pair must be used. The EXPORT componentshould be attached to the control signal wire and the IMPORT component placed inthe same subsystem as the power system component.

CC USAGE


Rev. 03: Aug 07


3 CONTROL BLOCKSControl components are accessed from RSCAD/Draft 3PC_Controls library. Thelibrary windowmay be customized and saved as a user library using SAVE TABASfunction. Individual components may be added to a library by using theCOMPONENT>ADDfunction. The library must be saved in order for the newlyadded component to be stored in the library.

A components name can be displayed by highlighting the component (put the cursorover the component) and pressing the d key. The components name is displayedas part of a message shown in the message window near the bottom of theRSCAD/Draft window.

CC BLOCKS


MATHMATH SUMMING JUNCTIONSUMMING JUNCTION

CLASS: MATH FUNCTION

FUNCTION: 2 or 3 Input Summing Junction

RSCAD/Draft ICON: rtds_sharc_ctl_SUM3

+

Num= 3

+

Num= 2

Description:

2 or 3 input summing junction. Inputs may be individually set to add to or subtractfrom the output. INTEGER or REAL operation may be specified.

See Also:

Execution Time: 0.375 s

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MATHMATH MULTIPLICATION JUNCTIONMULTIPLICATION JUNCTION


FUNCTION: 2 or 3 Input Multiplication Junction

RSCAD/Draft ICON: rtds_sharc_ctl_MUL

Num= 3 Num= 2

X X

Description:

2 or 3 inputmultiplication junction. INTEGERorREALoperationmay be specified.

See Also: GAIN


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MATHMATH DIVIDE JUNCTIONDIVIDE JUNCTION


FUNCTION: 2 Input Divide Junction

RSCAD/Draft ICON: rtds_sharc_ctl_XDIVY

X

Y

X/Y

Description:

2 input divide junction. Inputs and output are REAL. The usermay specify the resultof a divide by zero (ie. Y input = 0.0) as either HALT or SET OUTPUT.

In halt mode, a divide by zero causes the simulation to stop with RSCAD/RunTimeissuing the error message Floating point invalid. In halt mode the output X/Y isset equal to 0.0 for the first timestep after starting the simulation case.In setoutputmode, a denominator value less than 1.0e12results in the output beingset to the user specified value (Val). No error or warning message is issued inRSCAD/RunTime.

See Also: INVERSE


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MATHMATH GAINGAIN


FUNCTION: Gain

RSCAD/Draft ICON: rtds_sharc_ctl_GAIN

1.0

Description:

Gain block, output= gain * input. Input and Output are REAL.

See Also: MULTIPLICATION JUNCTION


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NMATHMATH XX NNkXkXNN


FUNCTION: X raised to power N (2 =< N >= 99)

RSCAD/Draft ICON: rtds_sharc_ctl_XPOWNrtds_sharc_ctl_KXPOWN

XN

X= InputN= Integer Constantk= Real Constant

kXN

Description:

output= input raised to power N or input raised to power N multiplied by k. Input,k and Output are REAL, power is an integer greater than or equal to 2 and less thanor equal to 99.

See Also: rtds_sharc_ctl_EXP

Execution Time: 5+N s

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MATHMATH XX yy


FUNCTION: X raised to power y

RSCAD/Draft ICON: rtds_sharc_ctl_XPOWY

XY

X

Y

Description:

output= input raised to power y. Inputs X and Y, and Output are REAL.

See Also: rtds_sharc_ctl_EXPrtds_sharc_ctl_KXPOWNrtds_sharc_ctl_XPOWN


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MATHMATH XXKKCLASS: MATH FUNCTION

FUNCTION: Inverse K/X

RSCAD/Draft ICON: rtds_sharc_ctl_INV

XK

X= InputK= Constant

Description:

output= K/input. Input, K and Output are REAL. The user may specify the initialinput signal value which will be used to compute the output for the first timestepafter start of the simulation. The operationmode for a divide by zero (ie. Input = 0.0)may be specified as either HALT or SET OUTPUT.

In halt mode, a divide by zero causes the simulation to stop with RSCAD/RunTimeissuing the error message Floating point invalid. In halt mode the output X/Y isset equal to 0.0 for the first timestep after starting the simulation case.In setoutputmode, a denominator value less than 1.0e12results in the output beingset to the user specified value (Val). No error or warning message is issued inRSCAD/RunTime.

See Also: DIVIDE JUNCTION

Execution Time: Halt mode= 0.55 sSet output mode= 0.7 s

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MATHMATH ABSOLUTE VALUEABSOLUTE VALUE


FUNCTION: Absolute Value

RSCAD/Draft ICON: rtds_sharc_ctl_ABS

|X|

Description:

output= abs(input). Input and Output are REAL.

See Also:


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MATHMATH SQUARE ROOTSQUARE ROOT


FUNCTION: Square root

RSCAD/Draft ICON: rtds_sharc_ctl_SQRT

X

Description:

output= sqrt(input). Input andOutput are REAL. The operationmode for a negativesquare root (ie. Input < 0.0) may be specified as either HALT or SETOUTPUT=0.

In halt mode, a negative input causes the simulation to stop with RSCAD/RunTimeissuing the error message Negative Square Root Error.

In setoutput=0mode, a negative input results in the output being set to 0.0. No erroror warning message is issued in RSCAD/RunTime.

See Also:


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MATHMATH INVERSE SQUARE ROOTINVERSE SQUARE ROOT


FUNCTION: Inverse Square root

RSCAD/Draft ICON: rtds_sharc_ctl_INVSQRT

X

1

Description:

output= 1.0/sqrt(input). Input and Output are REAL. The operation mode for anegative square root or zero input (ie. Input =< 0.0) will cause the block output to be0.0. No error or warning message is issued in RSCAD/RunTime.

See Also:


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MATHMATH eexx


FUNCTION: e raised to power X

RSCAD/Draft ICON: rtds_sharc_ctl_EXP

eX

X= Inpute= 2.71828183

Description:

output= e raised to power input. Input and Output are REAL.

See Also:


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MATHMATH LOGLOG


FUNCTION: Natural Log, Log base 10 or Log base 2

RSCAD/Draft ICON: rtds_sharc_ctl_LOGS

eLOG

Func= LN

10LOG

Func= Log10

2LOG

Func= Log2

Description:

output= Natural Log, Log base 10 or Log base 2 of the input. Input and Output areREAL.

See Also:


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MATHMATH TRIGTRIG


FUNCTION: sine, cosine, tangent

RSCAD/Draft ICON: rtds_sharc_ctl_SINE

sin(rad)

FT= sin

cos(rad)

FT= cos

tan(rad)

FT= tan

Description:

output= Sine, Cosine or Tangent of the input. The input signal may be specified asradian or degree by setting the Mode parameter. Input and Output are REAL.

See Also:


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MATHMATH ARCTRIGARCTRIG


FUNCTION: arcsine, arccosine, arctangent

RSCAD/Draft ICON: rtds_sharc_ctl_ARCTRIG

arcsin(rad)

Fun= arcsin

arccos(rad)

Fun= arccos

arctan(rad)

Fun= arctan

Description:

output= ArcSine, ArcCosine or ArcTangent of the input. The output signal may bespecified as radian or degree by setting the Osig parameter. Input and Output areREAL. Input signals for the arcsin and arccos functions are limited to the range

1.0

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MATHMATH 3 PHASE SINE3 PHASE SINE


FUNCTION: 3 Phase Sine

RSCAD/Draft ICON: rtds_sharc_ctl_SINE3

A

B

C

3 PhaseSine

Ph (rad)

A

B

C

3 PhaseSine

Ph (rad)

G

(pk)

Gain= No Gain= Yes

Description: Three phase sine wave generator. The input signal is phase in eitherradians or degrees depending on theMode parameter setting (rad or deg). The outputis a three phase sine wave with phase rotation ABCand with outputs

A= sine(Ph)B= sine(Ph 120_)C= sine(Ph + 120_)

With the Gain parameter set to No, the output magnitude is limited to +/1.0. Withthe Gain parameter set to Yes the output magnitude is controlled using the G inputsignal.

All input and output signals are REAL.

See Also:

Execution Time: Gain=No 3.55 sGain=Yes 3.7 s

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MATHMATH ATAN2ATAN2


FUNCTION: 2 input arctangent

RSCAD/Draft ICON: rtds_sharc_ctl_ATAN2

ATAN2(rad)

R

I

Input R= Real Component Input

Input I= Imaginary Component Input

Description:

output= ArcTangent of the input. By specifying both the real and imaginarycomponents of the input, the output can be computed in the range =

180_ < Y

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MATHMATH F(X)F(X)


FUNCTION: Nonlinear gain functionRSCAD/Draft ICON: rtds_sharc_ctl_NLINEAR

rtds_sharc_ctl_NLG32

Y=F(X)

X

Y

Xn1

Yn1

Description: NLINEAR

A nonlinear gain is specified by entering up to 10 pairs of X,Y points. The output(Y) is computed given the input (X) and the specified data points. The first and lastline segments are extended so that an input greater than Xn or less than X1 will havea computed output. The entered values of X1, X2 ... Xn must be monotonicallyincreasing (ie. Xn+1 > Xn).

Description: NLG32

The same as above except that 32 pairs of points can be entered.

See Also:


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MATHMATH TABLE LOOKUPTABLE LOOKUP


FUNCTION: Table Lookup

RSCAD/Draft ICON: rtds_sharc_ctl_TABLE

20

Description:

Input is an index into a table of predefined numbers. The number of entries in thetable is limited to 48 and may be specified as REAL or INTEGER (IorF parameter).The input is INTEGER and must be in the range of 1 .. N where N is the number ofentries in the table. An input of 2, for example, results in the value associated withthe second table entry to be sent to the output signal. An input value less than 1 resultsin the first table entry to be sent to the output and an input value greater thanN resultsin the last table entry to be sent to the output.

See Also:


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MATHMATH RANDOMRANDOM


FUNCTION: Random Number Generator

RSCAD/Draft ICON: rtds_sharc_ctl_RAND

RAND RAND(white) (Gaussian)

Description:

output= Random Number. For white noise, a random number in the range 1

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MATHMATH MODULO DIVISIONMODULO DIVISION


FUNCTION: Modulo Division

RSCAD/Draft ICON: _rtds_MODULO.def

MOD2

Description:

This component calculates the modulo operation. It finds the remainer of thedivision of the input by a user specified divisor. The input, divisor and output are allfloating point numbers. The calculation carried out by this component is expressedmathematically below.

Y= X trunc YMOD

MODwhere X is the input,MOD is the divisor and Y is the output.

Example:

For an input of 25.5 and a modulo divisor value of 5, the output will be 0.1.


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LOGICLOGIC BOOLEANBOOLEAN

CLASS: LOGIC FUNCTION

FUNCTION: AND, OR, XOR

RSCAD/Draft ICON: rtds_sharc_ctl_LOGIC

Type= AND Type= OR Type= XOR

Description:

output= AND, OR, XOR of the inputs. The number of inputs may be specifiedbetween 2 and 6 and the outputmay be inverted or noninverted. The logic operationmay be performed on a Least Significant Bit (LSB) or WORD basis. With the Opparameter set to LSB all bits except the LSB are set to 0. With the Op parameterset to WORD the logic operation is performed on all 32 bits of the input word.Inputs and output are INTEGER.

65635

65635

LSB

Y= 1

65635

65635

WORD

Y= 65535

65635

65635

LSB

Y= 0

65635

65635

WORD

Y= 65536

See Also:

Execution Time: 0.175 + no_inputs*0.05 seg. 2 input AND= 0.275 s

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LOGICLOGIC NOTNOT


FUNCTION: NOT

RSCAD/Draft ICON: rtds_sharc_ctl_NOT

OP= LSB OP= WORD

Description:

output= input. The logic operation may be performed on a Least Significant Bit(LSB) or WORD basis. With the Op parameter set to LSB all bits except the LSBare set to 0. With the Op parameter set to WORD the logic operation is performedon all 32 bits of the input word. Input and output are INTEGER.

65635Y= 0

65635Y= 65536

OP= WORDOP= LSB

See Also:


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LOGICLOGIC BITSHIFTBITSHIFT


FUNCTION: BIT SHIFT

RSCAD/Draft ICON: rtds_sharc_ctl_BSHIFT

> 1

SD= Right

Description:

output= logical shift(input). Left or right shift operation may be performed. Inputand output are INTEGER.

1 >> 1

SD= Right

Y= 0

See Also:


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LOGICLOGIC BIT2WORDBIT2WORD


FUNCTION: CONVERT BITS to WORD

RSCAD/Draft ICON: rtds_sharc_ctl_BIT2WORD

bit w

ord

dot represents LSBconnection wire

Description:

Converts multiple logical inputs to a single word. The least significant bit input wireis identified by a small dot. All input signals must be logical (ie. 0 or 1 only). Thenumber of inputs may be specified up to a maximum of 8. The output is INTEGER.

See Also:

Execution Time: 0175 + no_inputs * 0.125 s

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LOGICLOGIC WORD2BITWORD2BIT


FUNCTION: CONVERT WORD TO BITS

RSCAD/Draft ICON: rtds_sharc_ctl_WORD2BIT

word b

it

dot represents LSBconnection wire

Description:

Converts multiple an integer word to multiple logical signals. The least significantbit input wire is identified by a small dot. All output signals are logical (ie. 0 or 1only). The input is INTEGER.

See Also:

Execution Time: 0175 + no_outputs * 0.125 s

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LOGICLOGIC SR FLIPFLOPSR FLIPFLOP


FUNCTION: SET RESET TYPE FLIPFLOPRSCAD/Draft ICON: rtds_sharc_ctl_SRFF

SR

FLIPFLOP

Q

Q

S

R

SR

FLIPFLOP

Q

Q

S

R

INV= HIGH INV= LOW

Description:

Set Reset, non clocked flipflop. The flipflop operates according to the followingtruth tables. The initial state of the flipflop (Q=0 or Q=1) is defined by the ISTAparameter.

Inputs Active High: Inputs Active Low

Qinit= 0 Qinit= 0

S R Q Q S R Q Q

0 0 0 1 0 0 0 1

0 1 0 1 0 1 1 0

1 0 1 0 1 0 0 1

1 1 1 0 1 1 0 1

See Also:


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LOGICLOGIC TTYPE FLIPFLOPTTYPE FLIPFLOP


FUNCTION: TTYPE (Toggle Type) FLIPFLOPRSCAD/Draft ICON: rtds_sharcu_ctl_Tflipflop

The TType flip flop toggles its outputs on a clock signal when input T=1. WhenT=0, the current state of the output is equal to the previous state. The initial state ofthe flipflop (Q=0 or Q=1) is defined by the Init parameter. The flip flop can triggeron a rising edge, falling edge or a level clock signal. The trigger type is defined bythe Trig parameter. The flipflop operates according to the following truth table.

T Q(t) Q(t+1) Q(t+1)

0 0 0 1

0 1 1 0

1 0 1 0

1 1 0 1

Execution Time: 1.48 s (3PC)66.7 nS (RPC)

40.0 nS (GPC)

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LOGICLOGIC RING COUNTERRING COUNTER


FUNCTION: Ring Counter

RSCAD/Draft ICON: rtds_sharc_ctl_RINGCOUNTER

6

Description:

The output value increments to next table entry each time a valid input transitionoccurs. Valid input transitions are defined by the OP parameter and may be set toRising Edge (0>1), Falling Edge (1>0)or Both. A valid input transition when theoutput is at the last table entry results in the first table entry being output.

See Also:


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LOGICLOGIC EDGE DETECTOREDGE DETECTOR


FUNCTION: Edge Detector

RSCAD/Draft ICON: rtds_sharc_ctl_EDGEDET

EdgeDetector

Description:

A single timestep pulse is output when a valid input transition occurs. Valid inputtransitions are defined as 0>1, 1>0or Both by the ED parameter. The magnitudeof the one timestep pulse is defined by the OV parameter.Input and output are INTEGER.

See Also:


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LOGICLOGIC BIT MAPPERBIT MAPPERCLASS: LOGIC FUNCTION

FUNCTION: Bit Mapper

RSCAD/Draft ICON: rtds_sharc_ctl_MAPBITS

123456

123456

Bit Mapper

Description:

One to six bits in an input integer can be rearranged in a user selectable way for theoutput.

Input and output are INTEGER.

See Also:


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SELECTORSELECTOR SELECT6SELECT6

CLASS: SELECTOR FUNCTION

FUNCTION: 6 INPUT SELECTOR

RSCAD/Draft ICON: rtds_sharc_ctl_SELECT6

SELECT

1

2

3

4

5

6

S

Description:

Output is set equal to input 16 selected by value at input S. Function can operateonREALor INTEGERnumbers. For example, if S= 1 then output= input 1. A selectvalue less than 1 selects input 1. A select value greater than 6 selects input 6.

See Also:


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SELECTORSELECTOR MIN/MAXMIN/MAX


FUNCTION: 2 or 6 input Minimum or Maximum selector

RSCAD/Draft ICON: rtds_sharc_ctl_MINMAX,rtds_sharc_ctl_MINMAX6

min max

min max

Description:

Output is set equal to the minimum or maximum input value. Input and Output canbe selected as INTEGER or REAL.

See Also:

Execution Time: minmax= 0.3 sminmax6= 0.8 s

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SELECTORSELECTOR IFTHENELSEIFTHENELSE


FUNCTION: IfThen_else select blockRSCAD/Draft ICON: rtds_sharc_ctl_COMPARE

IF A>= BY= 1ElseY= 2EndIf

A

B

Y

LOG= A>=B

IF A== BY= 1ElseY= 2EndIf

A

B

Y

LOG= A==B

IF A!= BY= 1ElseY= 2EndIf

A

B

Y

LOG= A!=B

IF A> BY= 1ElseY= 2EndIf

A

B

Y

LOG= A>B

Description:

Output is set equal to the specified value depending on inputs A and B and chosenlogic function.

A>=B: A greater than or equal to BA==B: A equal to BA!=B: A not equal to BA>B: A greater than B

Inputs and output can be independently specified as INTEGER or REAL.

See Also:


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SELECTORSELECTOR RANGE CHECKRANGE CHECK


FUNCTION: IfThen_else select blockRSCAD/Draft ICON: rtds_sharc_ctl_RANGE

LL

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SELECTORSELECTOR SIGNAL SELECTSIGNAL SELECT


FUNCTION: Signal select based on input logic

RSCAD/Draft ICON: rtds_sharc_ctl_SIGSW2

If (C1 > C2)

Out= A

Else

Out= B

A

B

C1 C2

Logic Options

C1 > C2

C1 >= C2

C1 == C2

C1 < C2

C1 C2: C1 greater than C2C1>=C2: C1 greater than or equal to C2C1==C2: C1 equal to C2C1

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SELECTORSELECTOR SIGNAL SWITCHSIGNAL SWITCH


FUNCTION: Signal select based on control signal

RSCAD/Draft ICON: rtds_sharc_ctl_SIGSW

A

B

Ctrl

Ctrl= 0

Description:

Output is set equal to the input signal A or B depending on the Ctrl signal value. IftheCtrl signal is equal to the specified value (Aparameter) then the output is set equalto the A signal, otherwise the output is set equal to the B signal.

The Ctrl signal must be INTEGER. Data flow signals A, B and output may bespecified as REAL or INTEGER.

See Also:


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LIMITERLIMITER FIXED LIMITSFIXED LIMITS

CLASS: LIMITER

FUNCTION: Fixed Limit

RSCAD/Draft ICON: rtds_sharc_ctl_LIMITS

+1.0

1.0

Description:

Output is limited to the specified range (upper and lower range values are specifiedas fixed values). Input and output may be specified as REAL or INTEGER.

See Also:


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LIMITERLIMITER DYNAMIC LIMITSDYNAMIC LIMITS

CLASS: LIMITER

FUNCTION: Dynamic Limit

RSCAD/Draft ICON: rtds_sharc_ctl_DYNLIMS

Max

Min

Description:

Output is limited to the specified range (upper and lower range values are inputsignals whichmay change dynamically). Input, output andmaximum andminimumlimits may be specified as REAL or INTEGER.

See Also:


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LIMITERLIMITER FIXED RATE LIMITSFIXED RATE LIMITS

CLASS: LIMITER

FUNCTION: Fixed Rate Limit

RSCAD/Draft ICON: rtds_sharc_ctl_RATELIMIT

+1.0

1.0Rate Limiter

Description:

Rate of change of output is limited to the specified range (upper and lower rangevalues are input signalswhichmay change dynamically). The lower range limitmustbe specified as a negative number. A positive or negative rate limit of 0.0 will resultin no change to the output if the input changes in the corresponding direction. Inputand output are REAL.

See Also:


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LIMITERLIMITER DYNAMIC RATE LIMITSDYNAMIC RATE LIMITS

CLASS: LIMITER

FUNCTION: Dynamic Rate Limit

RSCAD/Draft ICON: rtds_sharc_ctl_VRATELIMIT

max

min

Rate Limiter

Description:

Rate of change of output is limited to the specified range (upper and lower rangevalues are specified as fixed values). The lower range limit must be specified as anegative number. A positive or negative rate limit of 0.0 will result in no change tothe output if the input changes in the corresponding direction. Input and output areREAL.

See Also:


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LIMITERLIMITER DEADBANDDEADBAND

CLASS: LIMITER

FUNCTION: DeadBand

RSCAD/Draft ICON: rtds_sharc_ctl_DEADBAND

Description:

Output= Input only if the input is outside the specified limits. If the input is withinthe specified limits (THL parameter) the output is set equal to 0.0.

See Also:


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LIMITERLIMITER FIXED OUTPUT DEADBANDFIXED OUTPUT DEADBAND

CLASS: LIMITER

FUNCTION: Fixed Output DeadBand

RSCAD/Draft ICON: rtds_sharc_ctl_DEADFIX

Description:

Output= specified value when the input is outside the specified limits. If the inputis within the specified limits (UTH and LTH parameters) the output is set equal to0.0.

See Also:


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LIMITERLIMITER HYSTERSISHYSTERSIS

CLASS: LIMITER

FUNCTION: Hystersis Function

RSCAD/Draft ICON: rtds_sharc_ctl_HYSTER1

0

1

LowHigh

0

1

Description:

The Hystersis function allows inputs and outputs to be INTEGER or FLOAT. Theinitial state of the output can be set. The input values for trasnition to the output stateare selectable and the values of the output are selectable. Time at or above the inputvalue required to cause a transition to a high output as well as time at or below theinput level required to cause a transition to a low state are user selectable. Zeromeansno time at these levels is required.

See Also:


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DATA CONVERSIONDATA CONVERSION NEC>IEEENEC>IEEECLASS: DATA CONVERSION

FUNCTION: Convert NEC Format number to IEEE Format

RSCAD/Draft ICON: rtds_sharc_ctl_NEC2IEEE

NECIEEE

Description:

A NEC Format REAL input signal is converted to IEEE Format. NEC Formatsignals occur only for simulation cases which include TPC processor cards. RTDSsimulators which contain only 3PC processor cards do not use NEC format data.Control or power system signals IMPORTED from a TPC based processor must beconverted to IEEE format before being used as input to a SHARC controlcomponent.

See Also:


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DATA CONVERSIONDATA CONVERSION IEEE>NECIEEE>NECCLASS: DATA CONVERSION

FUNCTION: Convert IEEE Format number to NEC Format

RSCAD/Draft ICON: rtds_sharc_ctl_IEEE2NEC

IEEENEC

Description:

An IEEE Format REAL input signal is converted to NEC Format. NEC Formatsignals occur only for simulation cases which include TPC processor cards. RTDSsimulators which contain only 3PC processor cards do not use NEC format data.Control system signals EXPORTED from a 3PC based processor must be convertedto IEEE format before being used as input to TPC or 3PC based power systemcomponents when the simulation includes both TPC and 3PC cards.

See Also:


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DATA CONVERSIONDATA CONVERSION INT>REALINT>REALCLASS: DATA CONVERSION

FUNCTION: Convert INTEGER to IEEE Format number

RSCAD/Draft ICON: rtds_sharc_ctl_INT2IEEE

INTIEEE

Description:

An INTEGER input is converted to IEEE REAL.

See Also:


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DATA CONVERSIONDATA CONVERSION REAL>INTREAL>INTCLASS: DATA CONVERSION

FUNCTION: Convert an IEEE Format number to INTEGER

RSCAD/Draft ICON: rtds_sharc_ctl_IEEE2INT

IEEEINT

Description:

An IEEE REAL format number is converted to INTEGER. The OP parameter maybe set to round or truncate mode to control the conversion.

See Also:


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DATA CONVERSIONDATA CONVERSION RADDEGRADDEGCLASS: DATA CONVERSION

FUNCTION: Radian and Degree conversion

RSCAD/Draft ICON: rtds_sharc_ctl_DEGRAD

raddeg

degrad

Fun= deg>rad Fun= rad>deg

Description:

Converts degrees to radians (Fun=deg>rad)or radians to degrees (Fun= rad>deg).

See Also:


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DATA CONVERSIONDATA CONVERSION DBL2SGLDBL2SGL

CLASS: DATA CONVERSION

FUNCTION: Double to Single precision number conversion

RSCAD/Draft ICON: rtds_sharc_ctl_DBL2SGL

Description:

The input double precision floating point number is converted into a single precisionfloating point number using a user specified rounding mode. The resulting singleprecision floating point number is then converted back to a double precision floatingpoint number.

This component is very specific to number precision and in general will rarely beused.

The process in this model can be written in Pseudocode as shown below:

double dblInput;float floatInput;double dblOutput;

dblInput = ;floatInput = (float) dblInput; // specified rounding mode is useddblOutput = (double)floatInput;

Four different rounding modes are available;

Round tonearestRound towardzero (Truncate)Round up (Towards +Infinity)Round down (Towards Infinity)

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Below is an example using the different rounding modes.

DRAFT case

RUNTIME results

It is noted above that the same floating point input produces different resultsaccording to the rounding mode used.

Execution Time:25 nS (RPC)15 nS (GPC)

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I/OI/O DIGITAL INPUTDIGITAL INPUT

CLASS: INPUT/OUTPUT

FUNCTION: Digital Input

RSCAD/Draft ICON: rtds_sharc_ctl_DIGINP

.

.

.

.

.

.

.

.

.

.

.

DIGITALINPUT PORTProcessor #1

Description:

16 bit data is read from the processors digital input port. 3PC processors A and Bhave access to a digital input port. The C Processor does not have access to a digitalport. The digital input port component reads 16 bits and returns an INTEGER.Digital input port pins which are not connected to external equipment read a logic1. A value of 65535 (=0xFFFF) is returned if no connections aremade to the digitalinput port. Amask parameter is available to mask off unwanted bits from the digitalinput port. For example, a mask value of 000F will read only the four lowest orderbits.

The Del parameter is used to delay the read of the digital input port with respect tothe timestep. The delay time is specified in microseconds from the placement ofthe digital input port component within the processor. If the digital input componentis the first component executed in the assigned processor, the delay corresponds tothe time from the start of the timestep.See Also:

Execution Time: 0.2 + delay s

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I/OI/O DIGITAL OUTPUTDIGITAL OUTPUT

CLASS: INPUT/OUTPUT

FUNCTION: Digital Output

RSCAD/Draft ICON: rtds_sharc_ctl_DIGOUT

.

.

.

.

.

.

.

.

.

.

.

DIGITALOUTPUT PORTProcessor #1

Description:

16 bit data is written to the processors digital output port. 3PC processors A and Bhave access to a digital output port. TheC Processor does not have access to a digitalport. The digital output port component writes a 16 bit INTEGER to the digitaloutput port. Amask parameter is available tomask off unwanted bits from the digitaldata. For example, a mask value of 000F will cause only the four lowest order bitsto be written. All other bits will be logic 0.

See Also:


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I/OI/O ANALOGUE OUTPUTANALOGUE OUTPUT

CLASS: INPUT/OUTPUT

FUNCTION: Analogue Output

RSCAD/Draft ICON: rtds_sharc_ctl_AOUT

da1da #1

ICON= LARGE ICON= SMALL

Description:

Data is written to the specified analogue output channel on the assigned processor.Each 3PC processor has direct access to 8 analogue output channels. The analoguechannels output voltage range is +/ 10 volts peak. A digital signal with a value of+1.0 will result in an analogue output of +10 volts. An input signal outside the range+/1.0will result in clipping of the analogue output voltage to +/10 volts. The SCparameter is used to scale the input signal so that the specified value will result in ananalogue output voltage of 5 volts (half scale).

Dynamic offset and scale slidersmay be included (SLparameter). If enabled the useris able to create RSCAD/RunTime sliders to dynamically adjust the analogue outputoffset and scale. ARSCAD/RunTime switchmay also be created which controls theLED associated with the analogue output channel. The LED can be turned on by theswitch to help locate the analogue output port on the front of the RTDS.

The front panel analogue output channels use 12 bit D/As and do not include opticalisolation. For high precision, optically isolated analogue output see informationregarding the DAC16 component.

See Also: DAC16


CC BLOCKS


I/OI/O ANALOGUE INPUTANALOGUE INPUT

CLASS: INPUT/OUTPUT

FUNCTION: Analogue Input from OADC

RSCAD/Draft ICON: rtds_sharc_ctl_OADC

1

OADC Analogue Input

NS= 1

4

OADCAnalogue Input

NS= 6

5

2

3

1

6

Description:

Read data from the Optical Analogue Input Card (OADC). The OADC reads datafrom up to six analogue input channels and converts it to digital format for use by theRTDS. A separate scale value is included for each input signal (SC1 ... SC6). Scalevalues represent the analogue signal peak voltage (in volts) which will result in avalue of 1.0 to be present on the corresponding output signal wire (labelled 1 .. 6).For example, a scale value of SC1=5.0means that a voltage of 1 volt on the analogueinput channel #1 will result in a value of 1.0 on the output wire labelled 1. Themaximum input range of the OADC is +/ 10 volts peak.

See Also:


CC BLOCKS


I/OI/O FDAC DAC16FDAC DAC16

CLASS: INPUT/OUTPUT

FUNCTION: DAC16 Analogue Output

RSCAD/Draft ICON: rtds_sharc_ctl_DAC16rtds_sharc_ctl_FDAC

dac16

1

2

3

FDAC

Description:

These components write output signals to a DAC16 or an FDAC. These are highprecision analogue output boards providing 3 channels on theDAC16and 6 channelson the FDAC. BothD/A converters are optional RTDShardware components whichare mounted in the rear of the cubicle. The DAC16 interfaces to a digital I/O portwhile the FDAC interfaces to an optical output port. As a result, the FDACcommunicates through a C processor while the DAC16 communicates through anA or B processor.

Inputs to both components are REAL. Software converts and scales the input signalsto 16 bit and writes them out. Both components have an output range of +/10volts.The S1M, S2M, ... parameters are used to set the scale values such that the specifiedinput signal magnitude will result in an analogue output voltage of +5 volts (halfscale).

Both cards include optical isolation.

See Also: rtds_sharc_ctl_DDAC


CC BLOCKS


I/OI/O DITSDITS

CLASS: INPUT/OUTPUT

FUNCTION: Digital TimeStamp Card InputRSCAD/Draft ICON: rtds_sharc_ctl_DITS

EN

FP

ACT

Frac

DITS

Description:

The DITS component is an o

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