CCET - VLSI Desgn

8/21/2019 CCET - VLSI Desgn

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VLSI DESIGN

-EEE


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Unit-1

MOS Transistor Theory


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VLSI DESIGN

UNIT I

Contents:

1.1 Historical Perspective

1.2 What is VLSI? - Introduction

1.3 VLSI Design Flow

1.4 Design Hierarchy

1.5 Basic MOS Transistor

1.6 CMOS ChipFabrication

1.7 Layout Design Rules

1.8 Lambda Based Rules

1.9 Design Rules- MOSIS Scalable CMOS (SCMOS)


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Objective:

* To show the evolution of logic complexity in integrated circuits.

* To understand what is VLSI?

*To illustrate a design flow for logic chips using Y-chart.

* To understand the divide and conquer technique of dividing a module into sub-

modules for the simplicity of design.

* To know thestructure, symbol and operation of basic MOS Transistor.

* To know the process flow in chip fabrication and the interaction of various processing

steps.

* To have an overview about Advanced CMOS fabrication technologies.

* To specify the layout design rules in two ways i) Lambda rules ii)micron rules.


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1.1 Historical Perspective

The electronics industry has achieved a phenomenal growth over the last twodecades, mainly due to the rapid advances in integration technologies, large-scale systemsdesign - in short, due to the advent of VLSI. The number of applications of integratedcircuits in high-performance computing, telecommunications, and consumer electronics

has been rising steadily, and at a very fast pace. Typically, the required computationalpower (or, in other words, the intelligence) of these applications is the driving force forthe fast development of this field. Figure 1.1 gives an overview of the prominent trends ininformation technologies over the next few decades. The current leading-edgetechnologies (such as low bit-rate video and cellular communications) already provide theend-users a certain amount of processing power and portability. This trend is expected tocontinue, with very important implications on VLSI and systems design. One of the mostimportant characteristics of information services is their increasing need for very highprocessing power and bandwidth (in order to handle real-time video, for example). Theother important characteristic is that the information services tend to become more and

more personalized (as opposed to collective services such as broadcasting), which meansthat the devices must be more intelligent to answer individual demands, and at the sametime they must be portable to allow more flexibility/ mobility.

Figure-1.1: Prominent trends in information service technologies.

As more and more complex functions are required in various data processing andtelecommunications devices, the need to integrate these functions in a smallsystem/ package is also increasing. The level of integration as measured by the number oflogic gates in a monolithic chip has been steadily rising for almost three decades, mainly


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due to the rapid progress in processing technology and interconnect technology. Table 1.1shows the evolution of logic complexity in integrated circuits over the last three decades,and marks the milestones of each era. Here, the numbers for circuit complexity should beinterpreted only as representative examples to show the order-of-magnitude. A logicblock can contain anywhere from 10 to 100 transistors, depending on the function. State-of-the-art examples of ULSI chips, such as the DEC Alpha or the INTEL Pentium contain 3

to 6 million transistors.

ERA DATE COMPLEXITY(number of logic blocks per chip)

Single transistor 1959 less than 1

Unit logic (one gate) 1960 1

Multi-function 1962 2- 4

Complex function 1964 5- 20Medium Scale Integration 1967 20- 200 (MSI)

Large Scale Integration 1972 200 - 2000

(LSI)Very Large Scale Integration 1978 2000 - 20000

(VLSI)Ultra Large Scale Integration 1989 20000- ? (ULSI)

Table-1.1: Evolution of logic complexity in integrated circuits.

The most important message here is that the logic complexity per chip has been (andstill is) increasing exponentially. The monolithic integration of a large number offunctions on a single chip usually provides:

Less area/ volume and therefore, compactness

Less powerconsumption Less testing requirements at system level

Higher reliability, mainly due to improved on-chip interconnects

Higher speed, due to significantly reduced interconnection length Significant cost savings


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Figure-1.2: Evolution of integration density and minimum feature size, as seen in theearly 1980s.

Therefore, the current trend of integration will also continue in the foreseeable future.Advances in device manufacturing technology, and especially the steady reduction ofminimum feature size (minimum length of a transistor or an interconnect realizable onchip) support this trend. Figure 1.2 shows the history and forecast of chip complexity - andminimum feature size - over time, as seen in the early 1980s. At that time, a minimumfeature size of 0.3 microns was expected around the year 2000. The actual developmentof the technology, however, has far exceeded these expectations. A minimum size of 0.25

microns was readily achievable by the year 1995. As a direct result of this, the integrationdensity has also exceeded previous expectations- the first 64 Mbit DRAM, and the INTELPentium microprocessor chip containing more than 3 million transistors were alreadyavailable by 1994, pushing the envelope of integration density.

When comparing the integration density of integrated circuits, a clear distinction must bemade between the memory chips and logic chips. Figure 1.3 shows the level of integrationover time for memory and logic chips, starting in 1970. It can be observed that in terms oftransistor count, logic chips contain significantly fewer transistors in any given year mainlydue to large consumption of chip area for complex interconnects. Memory circuits are

highly regular and thus more cells can be integrated with much less area for interconnects.


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Figure-1.3: Level of integration over time, for memory chips and logic chips.

Generally speaking, logic chips such as microprocessor chips and digital signal processing(DSP) chips contain not only large arrays of memory (SRAM) cells, but also manydifferent functional units. As a result, their design complexity is considered much higherthan that of memory chips, although advanced memory chips contain some sophisticatedlogic functions. The design complexity of logic chips increases almost exponentially withthe number of transistors to be integrated. This is translated into the increase in the designcycle time, which is the time period from the start of the chip development until the mask-

tape delivery time. However, in order to make the best use of the current technology, thechip development time has to be short enough to allow the maturing of chipmanufacturing and timely delivery to customers. As a result, the level of actual logicintegration tends to fall short of the integration level achievable with the currentprocessing technology. Sophisticated computer-aided design (CAD) tools andmethodologies are developed and applied in order to manage the rapidly increasingdesign complexity.


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1.2 INTRODUCTION

What is VLSI?

VLSI stands for "Very Large Scale Integration". This is the field which involvespacking more and more logic devices into smaller and smaller areas. Thanks to VLSI,

circuits that would have taken boardfuls of space can now be put into a small space fewmillimeters across! This has opened up a big opportunity to do things that were notpossible before. VLSI circuits are everywhere ... your computer, your car, your brand newstate-of-the-art digital camera, the cell-phones, and what have you. All this involves a lotof expertise on many fronts within the same field.

VLSI has been around for a long time, there is nothing new about it ... but as a side effectof advances in the world of computers, there has been a dramatic proliferation of toolsthat can be used to design VLSI circuits. Alongside, obeying Moore's law, the capability ofan IC has increased exponentially over the years, in terms of computation power,utilizationof available area, yield. The combined effect of these two advances is thatpeople can now put diverse functionality into the IC's, opening up new frontiers.Examples are embedded systems, where intelligent devices are put inside everydayobjects, and ubiquitous computing where small computing devices proliferate to such anextent that even the shoes you wear may actually do something useful like monitoringyour heartbeats!

DEALING WITH VLSI CIRCUITS

Digital VLSI circuits are predominantly CMOS based. The way normal blocks like latches

and gates are implemented is different from what students have seen so far, but thebehavior remains the same. All theminiaturization involves new things to consider. A lotof thought has to go into actual implementations as well as design. Let us look at some ofthe factorsinvolved ...

1. Circuit Delays

Large complicated circuits running at very high frequencies have one big problemto tackle - the problem of delays in propagation of signals through gates and wires ... evenfor areas a few micrometers across! The operation speed is so large that as the delays add

up, they can actually become comparable to the clock speeds.

2. Power.

Another effect of high operation frequencies is increased consumption of power.This has two-fold effect - devices consume batteries faster, and heat dissipation increases.Coupled with the fact that surface areas have decreased, heat poses a major threat to thestability of the circuit itself.


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3. Layout.

Laying out the circuit components is task common to all branches of electronics.Whats so special in our case is that there are many possible ways to do this; there can bemultiple layers of different materials on the same silicon, there can be different

arrangements of the smaller parts for the same component and so on.

The power dissipation and speed in a circuit present a trade-off; if we try to optimise onone, the other is affected. The choice between the two is determined by the way wechose the layout the circuit components. Layout can also affect the fabrication of VLSIchips, making it either easy or difficult to implement the components on the silicon.

1.3VLSI Design Flow

The design process, at various levels, is usually evolutionary in nature. It starts with agiven set of requirements. Initial design is developed and tested against the requirements.When requirements are not met, the design has to be improved. If such improvement iseither not possible or too costly, then the revision of requirements and its impact analysismust be considered. The Y-chart (first introduced by D. Gajski) shown in Fig. 1.4illustrates a design flow for most logic chips, using design activities on three different axes(domains) which resemble the letter Y.


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Figure-1.4:Typical VLSI design flow in three domains (Y-chartrepresentation).

The Y-chart consists of three major domains, namely:

behavioral domain, structural domain,

geometrical layout domain.

The design flow starts from the algorithm that describes the behavior of the target chip.The corresponding architecture of the processor is first defined. It is mapped onto the chipsurface by floorplanning. The next design evolution in the behavioral domain definesfinite state machines (FSMs) which are structurally implemented with functional modulessuch as registers and arithmetic logic units (ALUs). These modules are then geometricallyplaced onto the chip surface using CAD tools for automatic module placement followedby routing, with a goal of minimizing the interconnects area and signal delays. The thirdevolution starts with a behavioral module description. Individual modules are thenimplemented with leaf cells. At this stage the chip is described in terms of logic gates (leafcells), which can be placed and interconnected by using a cell placement & routingprogram. The last evolution involves a detailed Boolean description of leaf cells followedby a transistor level implementation of leaf cells and mask generation. In standard-cellbased design, leaf cells are already pre-designed and stored in a library for logic designuse.


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Figure-1.5:A more simplified view of VLSI design flow.

Figure 1.5 provides a more simplified view of the VLSI design flow, taking into account thevarious representations, or abstractions of design - behavioral, logic, circuit and masklayout. Note that the verification of design plays a very important role in every step duringthis process. The failure to properly verify a design in its early phases typically causessignificant and expensive re-design at a later stage, which ultimately increases the time-

to-market.

Although the design process has been described in linear fashion for simplicity, in realitythere are many iterations back and forth, especially between any two neighboring steps,and occasionally even remotely separated pairs. Although top-down design flow providesan excellent design process control, in reality, there is no truly unidirectional top-downdesign flow. Both top-down and bottom-up approaches have to be combined. Forinstance, if a chip designer defined an architecture without close estimation of the


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corresponding chip area, then it is very likely that the resulting chip layout exceeds thearea limit of the available technology. In such a case, in order to fit the architecture intothe allowable chip area, some functions may have to be removed and the design processmust be repeated. Such changes may require significant modification of the originalrequirements. Thus, it is very important to feed forward low-level information to higherlevels (bottom up) as earlyas possible.

In the following, we will examine design methodologies and structured approaches whichhave been developed over the years to deal with both complex hardware and softwareprojects. Regardless of the actual size of the project, the basic principles of structureddesign will improve the prospects of success. Some of the classical techniques forreducing the complexity of IC design are: Hierarchy, regularity, modularity and locality.

1.4Design Hierarchy

The use of hierarchy, or divide and conquer technique involves dividing a module intosub- modules and then repeating this operation on the sub-modules until the complexityof the smaller parts becomes manageable. This approach is very similar to the softwarecase where large programs are split into smaller and smaller sections until simplesubroutines, with well-defined functions and interfaces, can be written. In Section 1.2, wehave seen that the design of a VLSI chip can be represented in three domains.Correspondingly, a hierarchy structure can be described in each domain separately.However, it is important for the simplicity of design that the hierarchies in differentdomains can be mapped into each other easily.

As an example of structural hierarchy, Fig. 1.6 shows the structural decomposition of aCMOS four-bit adder into its components. The adder can be decomposed progressivelyinto one- bit adders, separate carry and sum circuits, and finally, into individual logicgates. At this lower level of the hierarchy, the design of a simple circuit realizing a well-defined Boolean function is much more easier to handle than at the higher levels of thehierarchy.

In the physical domain, partitioning a complex system into its various functional blockswill provide a valuable guidance for the actual realization of these blocks on chip.

Obviously, the approximate shape and size (area) of each sub-module should beestimated in order to provide a useful floor plan. Figure 1.7 shows the hierarchicaldecomposition of a four-bit adder in physical description (geometrical layout) domain,resulting in a simple floor plan. This physical view describes the external geometry of theadder, the locations of input and output pins, and how pin locations allow some signals (inthis case the carry signals) to be transferred from one sub-block to the other withoutexternal routing. At lower levels of the physical hierarchy, the internal mask


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Figure-1.6: Structural decomposition of a four-bit adder circuit, showing the hierarchydown to gate level.

1.5 Basic MOS Transistor

The most basic element in the design of a large scale integrated circuit is the transistor.Metal-Oxide-Semiconductor Field Effect Transistors(MOSFET) are formed as asandwichconsisting of a semiconductor layer, usually a slice, or wafer, from a singlecrystal of silicon; a layer of silicon dioxide (the oxide) and a layer of metal. These layersare patterned in a manner which permits transistors to be formed in the semiconductor

material (the substrate); a diagram showing a typical (idealized) MOSFET is shown inFigure Silicon dioxide is a very good insulator, so a very thin layer, typically only a fewhundred molecules thick, is required. Actually, the transistors which we will use do notuse metal for their gate regions, but instead use polycrystalline silicon (poly). Polysilicongate FET's have replaced virtually all of the older devices using metal gates in large scaleintegrated circuits. (Both metal and polysilicon FET's are sometimes referred to asIGFET's--- insulated gate field effect transistors, since the silicon dioxide under the gateis an insulator.

Figure: MOS transistor


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The transistor consists of three regions, labeled thesource', the gate and the `drain''.The area labeled as the gate region is actually a `sandwich'' consisting of the underlyingsubstrate material, which is a single crystal of semiconductor material (usually silicon); athin insulating layer (usually silicon dioxide); and an upper metal layer. Electrical charge,or current, can flow from the source to the drain depending on the charge applied to thegate region. The semiconductor material in the source and drain region are ``doped''

with a different type of material than in the region under the gate, so an NPN or PNP typestructure exists between the source and drain region of a MOSFET.An MOS transistor is a majority-carrier device, in which the current in a conductingchannel between the source and thedrain is modulated by a voltage applied to the gate.

Symbols

NMOS (n-type MOS transistor)

(1) Majority carrier = electrons(2) A positive voltage applied on the gate with respect to the substrate enhances thenumber of electrons in the channel and hence increases the conductivity of the channel.(3) If gate voltage is less than a threshold voltage Vt , the channel is cut-off (very lowcurrent between source & drain).

PMOS (p-type MOS transistor)

(1) Majority carrier = holes(2) Applied voltage is negative with respect to substrate.Threshold voltage (Vt):The voltage at which an MOS device begins to conduct ("turnon")

Relationship between Vgs (gate-to-source voltage) and the source-to-drain current

(Ids) , given a fixed drain-to-source voltage (Vds).


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MOS Transistor typesbased on operation:

(1) Devices that are normally cut-off with zero gate bias are classified as"enhancement-mode "devices.(2) Devices that conduct with zero gate bias are called"depletion-mode "devices.

(3) Enhancement-mode devices are more popular in practical use.

1.4.1 NMOS Enhancement Transistor

Consist of

(1) Moderately doped p-type silicon substrate(2) Two heavily doped n+regions, the source and drain, arediffused.(3) Channel is covered by a thin insulating layer of silicon dioxide (SiO2) called " GateOxide "(4) Over the oxide is a polycrystalline silicon (polysilicon) electrode, referred to as the"Gate".

Features

(1) Since the oxide layer is an insulator, the DC current from the gate to channel isessentially zero.(2) No physical distinction between the drain and source regions.(3) Since SiO2 has low loss and high dielectric strength, the application of high gate fieldsis feasible.


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In operation

(1) Set Vds > 0 in operation(2) Vgs =0 no current flow between source and drain. They are insulated by tworeversed-biased PN junctions

(3) When Vg > 0 , the produced E field attracts electrons towardthe gate and repels holes.(4) If Vg is sufficiently large, the region under the gate changes from p-type to n-type(due to accumulation of attracted elections) and provides a conducting path between

source anddrain.>Thethin layer of p-type silicon is said to be"inverted".

(5) Three modesa. Accumulation mode (Vgs Vt)


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Electrically(1) An MOS device can be considered as a voltage-controlledswitch that conducts whenVgs >Vt (given Vds>0)(2) An MOS device can be considered as a voltage-controlledresistor

Effective gate voltage (Vgs-Vt)At the source end , the full gate voltage is effective in inverting the channel. At the drain

end , only the difference between the gate and drain voltage is effective.


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1.4.2 PMOS Enhancement Transistor(1) Vg < 0(2) Holes are major carrier(3) Vd < 0 , which sweeps holes from the source through the channel to the drain .

Current Voltage curves:


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1.4.3 Threshold voltage

The threshold voltage of a MOSFET is usually defined as the gate voltage where an

inversion layer forms at the interface between the insulating layer (oxide) and thesubstrate (body) of the transistor. The creation of this layer is describednext.

In an n-MOSFET the substrate of the transistor is composed of p-type silicon (see doping(semiconductor)), which has positively charged mobile holes as carriers. When a positivevoltage is applied on the gate, an electric field causes the holes to be repelled from theinterface, creating a depletion region containing immobile negatively charged acceptorions. A further increase in the gate voltage eventually causes electrons to appear at theinterface, in what is called an inversion layer, or channel. Historically the gate voltage atwhich the electron density at the interface is the same as the hole density in the neutralbulk material is called the threshold voltage. Practically speaking the threshold voltage isthe voltage at which there are sufficient electrons in the inversion layer to make a lowresistance conducting path between the MOSFET source and drain.

It is afunction of(1) Gate conductor material(2) Gate insulator material(3) Gate insulator thickness(4) Impurity at the silicon-insulator interface(5) Voltage between the source and the substrate Vsb(6) Temperaturea. -4 mV/ C high substrate doping

b. -2 mV/ C low substrate doping

MOS Transistor structureThe basic concept of aM OSTransistoris simple and best understood by looking at its

structure:


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It is always an integratedstructure, there are practically no single individual MOStransistors.

A MOStransistor is primarily a switch for digital devices. Ideally, it works as follows:

If the voltage at the gateelectrode is "on" , the transistor is "on", too, and current flow

between the source and drain electrodes is possible (almost) without losses. If thevoltage at the gate electrode is "off", the transistor is "off", too, and no current flowsbetween the source and drain electrode. In reality, this only works for a givenpolarity of

the gate voltage.Moreover, aMOStransistor needsverythingate dielectrics(around, or

better below 10 nm), and extreme control of materials and technologies if real MOS

transistors are to behave as they are expected to in "ideal" theory.

Understanding MOS transistor qualitatively is easy. We look at the example from aboveand apply some source-drain voltage VSD in either polarity, but no gate voltage yet. Whatwe have under these conditions is: A n-type Si substrate with a certain equilibrium density

of electrons ne(UG = 0), or ne(0) for short. Its value is entirely determined by doping(and the temperature, which we will neglect at the present, however) and is the sameeverywhere. We also have a much smaller concentration nh(0) of holes.Two pn-junctions, one of which is polarized in forward direction (the one with thepositive voltage pole), and the other one in reverse. This is true for any polarity; inparticular one junction will always be biased in reverse. Therefore no source-draincurrent ISD will flow (or only some small reverse current which we will neglect atpresent). There will also be no current in the forwardly biased diode, because the n-Si ofthe substrate in the figure is not electrically connected to anything (in reality, we mightsimply ground the positive USD pole and the substrate). For a gate voltage UG = 0 V,

there are no currents and everything is in equilibrium. But now apply a negative voltage atthe gate.The electrons in the substrate below the gate will be electrostatically repelled and driveninto the substrate. Their concentration directly below thegate will go down, ne (U) willbe a function of the depth coordinate z .

Since we still have equilibrium, the mass action law for carriers holds anywhere inthe Si, i.e. .

ne(z) nh(z) = ni2

With ni = intrinsic carrier density in SiThis gives usnh (z) = ni2 ne (z)

In other words: If the electron concentration below the gate goes down, the holeconcentration goes up.If we sufficiently decrease the electron concentration under the gate by cranking up thegate voltage, we will eventually achieve the condition nh (z = 0) = ne (z = 0) right underthe gate, i.e. at z = 0. If we increase the gate voltage even more, we will encounter the


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condition nh (z) > ne (z) for small values of z, ie. for zc > z > 0. In other words: Rightunder the gate we now have more holes than electrons; this is called a state of inversionfor obvious reasons. Si having more holes than electrons is also called p-type Si. What wehave now is a p-conducting channel (with width zc) connecting the p-conducting sourceand drain. There are no more pn-junctions preventing current flow under the gate-current can flow freely; only limited by the ohmic resistance of contacts, source/ drain and

channel. The resistivity of this channel will be determined by the amount of Si we haveinverted; it will rapidly come down with the voltage as soon as the threshold voltagenecessary for inversion is reached. If we reverse the voltage at the gate, we attractelectrons and their concentration under the gate increases. This is called a state ofaccumulation. The pn junctions at source and drain stay intact, and no source- draincurrent will flow. Obviously, if we want to switch a MOS transistor "on" with a positivegate voltage, we must now reverse the doping and use a p-doped substrates and n-dopedsource/ drain regions. The two basic types we call "n-channel MOS" and "p-channelMOS" according to the kind of doping in the channel upon inversion (or the source/ draincontacts).


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Voltage at the gate Conditions in

the Si

Voltage drop Charge

distribution

Zero gate voltage.

"Flat band" condition

Nothinghappens. The

band in thesubstrate isperfectly flat(and so is theband in thecontactelectrode, butthat is of nointerest).

We onlywould have a

voltage (orbetterpotential)drop, if theFermi energiesof substrateand gateelectrodewere different

There are nonetcharges

Posit ive gate volt age.

Accumulation

With a positivevoltage at thegate we attract

the electronsin thesubstrate. Thebands mustbend downsomewhat,and weincrease thenumber ofelectrons in

the conductionbandaccordingly.(There is a bitof a spacecharge region

(SCR) in the

contact,but

The voltagedrops mostlyin the oxide

There is somepositi ve charge

at the gate

electrodeinterface (withourSielectrode from

theSCR), and

negative

chargefromthe manyelectrons inthe (thin)

accumulationlayer on theother side ofthe gatedielectric.


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that is of nointerest).

Small negative gat e voltage.

Depletion

With a (small)

negativevoltage at thegate, we repelthe electronsin thesubstrate.Theirconcentrationdecreases, thehole

concentrationis still low - wehave a layerdepleted ofmobile carriersand therefore

aSCR.

The voltage

drops mostlyin the oxide,but also tosome extent in

theSCR.

There is some

negative

chargeat thegate electrodeinterface(accumulatedelectrons with

ourSi

electrode),andpositivecharge

smeared out inthe the(extended)

SCR layer on

the other sideof the gatedielectric.

Large negagive gate volt age.

Inversion

With a (large)negativevoltage at thegate, we repelthe electronsin thesubstrate verymuch. Thebands bend so

much, that theFermi energy(red line) is inthe lower halfof the bandclose to theinterface. Inthis regionholes are the

The voltagedrops mostlyin the oxide,but also tosome extent in

theSCRand

the inversionlayer.

There is morenegative

chargeat thegate electrodeinterface(accumulatedelectrons with

ourSi

electrode),

somepositivechargesmeared out inthe the(extended)

SCR layer on

the other sideof the gatedielectric, and


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majoritycarriers, wegave inversion.We still have a

SCR, too.

a lot ofpositivechargefromthe holes inthin inversionlayer.

1.6 CMOS CHIP FABRICATION

Contents :

1.5.1 Introduction

1.5.2 Fabrication Process Flow - Basic Steps

1.5.3 The CMOS n-Well Process

1.5.4 Advanced CMOS Fabrication Technologies

1.5.1 Introduction

In this topic, the emphasis will be on the general outline of the process flow and on theinteraction of various processing steps, which ultimately determine the device and thecircuit performance characteristics. The following chapters show that there are verystrong links between the fabrication process, the circuit design process and theperformance of the resulting chip. Hence, circuit designers must have a workingknowledge of chip fabrication to create effective designs and in order to optimize thecircuits with respect to various manufacturing parameters. Also, the circuit designer musthave a clear understanding of the roles of various masks used in the fabrication process,and how the masks are used to define various featuresof the devices on-chip.


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The following discussion will concentrate on the well-established CMOS fabricationtechnology, which requires that both n-channel (nMOS) and p-channel (pMOS)transistors be built on the same chip substrate. To accommodate both nMOS and pMOSdevices, special regions must be created in which the semiconductor type is opposite tothe substrate type. These regions are called wells or tubs. A p-well is created in an n-typesubstrate or, alternatively, an n- well is created in a p-type substrate. In the simple n-well

CMOS fabrication technology presented, the nMOS transistor is created in the p-typesubstrate, and the pMOS transistor is created in the n-well, which is built-in into the p-type substrate. In the twin-tub CMOS technology, additional tubs of the same type as thesubstrate can also be created for device optimization.

The simplified process sequence for the fabrication of CMOS integrated circuits on a p-type silicon substrate is shown in Fig. 2.1. The process starts with the creation of the n-well regions for pMOS transistors, by impurity implantation into the substrate. Then, athick oxide is grown in the regions surrounding the nMOS and pMOS active regions. Thethin gate oxide is subsequently grown on the surface through thermal oxidation. These

steps are followed by the creation of n+ and p+ regions (source, drain and channel-stopimplants) and by final metallization (creation of metal interconnects).

Figure-2.1: Simplified process sequence for fabrication of the n-well CMOS integratedcircuit with a single polysilicon layer, showing only major fabrication steps.


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The process flow sequence pictured in Fig. 2.1 may at first seem to be too abstract, sincedetailed fabrication steps are not shown. To obtain a better understanding of the issuesinvolved in the semiconductor fabrication process, we first have to consider some of thebasic steps in more detail.

1.5.2 Fabrication Process Flow- Basic Steps

Note that each processing step requires that certain areas are defined on chip byappropriate masks. Consequently, the integrated circuit may be viewed as a set ofpatterned layers of doped silicon, polysilicon, metal and insulating silicon dioxide. Ingeneral, a layer must be patterned before the next layer of material is applied on chip. Theprocess used to transfer a pattern to a layer on the chip is called lithography. Since eachlayer has its own distinct patterning requirements, the lithographic sequence must berepeated for every layer, using a different mask.

To illustrate the fabrication steps involved in patterning silicon dioxide through opticallithography, let us first examine the process flow shown in Fig. 2.2. The sequence startswith the thermal oxidation of the silicon surface, by which an oxide layer of about 1micrometer thickness, for example, is created on the substrate (Fig. 2.2(b)). The entireoxide surface is then covered with a layer of photoresist, which is essentially a light-sensitive, acid-resistant organic polymer, initially insoluble in the developing solution(Fig. 2.2(c)). If the photoresist material is exposed to ultraviolet (UV) light, the exposedareas become soluble so that the they are no longer resistant to etching solvents. Toselectively expose the photoresist, we have to cover some of the areas on the surface with

a mask during exposure. Thus, when the structure with the mask on top is exposed to UVlight, areas which are covered by the opaque features on the mask are shielded. In theareas where the UV light can pass through, on the other hand, the photoresist is exposedand becomes soluble (Fig. 2.2(d)).


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Figure-2.2: Process steps required for patterning of silicon dioxide.

The type of photoresist which is initially insoluble and becomes soluble after exposure toUV light is called positive photoresist. The process sequence shown in Fig. 2.2 usespositive photoresist. There is another type of photoresist which is initially soluble andbecomes insoluble (hardened) after exposure to UV light, called negative photoresist. Ifnegative photoresist is used in the photolithography process, the areas which are notshielded from the UV light by the opaque mask features become insoluble, whereas theshielded areas can subsequently be etched away by a developing solution. Negativephotoresists are more sensitive to light, but their photolithographic resolution is not ashigh as that of the positive photoresists. Therefore, negative photoresists are used lesscommonly in the manufacturing of high-density integrated circuits.

Following the UV exposure step, the unexposed portions of the photoresist can beremoved by a solvent. Now, the silicon dioxide regions which are not covered byhardened photoresist can be etched away either by using a chemical solvent (HF acid) orby using a dry etch (plasma etch) process (Fig. 2.2(e)). Note that at the end of this step,we obtain an oxide window that reaches down to the silicon surface (Fig. 2.2(f)). Theremaining photoresist can now be stripped from the silicon dioxide surface by using


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another solvent, leaving the patterned silicon dioxide feature on the surface as shown inFig. 2.2(g).

The sequence of process steps illustrated in detail in Fig. 2.2 actually accomplishes a singlepattern transfer onto the silicon dioxide surface, as shown in Fig. 2.3. The fabrication ofsemiconductor devices requires several such pattern transfers to be performed on silicon

dioxide, polysilicon, and metal. The basic patterning process used in all fabrication steps,however, is quite similar to the one shown in Fig. 2.2. Also note that for accurategeneration of high-density patterns required in sub-micron devices, electron beam (E-beam) lithography is used instead of optical lithography. In the following, the mainprocessing steps involved in the fabrication of an n-channel MOS transistor on p-typesilicon substrate will be examined.

Figure-2.3:The result of a single lithographic patterning sequence on silicon dioxide,

without showing the intermediate steps. Compare the unpatterned structure (top) andthe patterned structure (bottom) with Fig. 2.2(b) and Fig. 2.2(g), respectively.

The process starts with the oxidation of the silicon substrate (Fig. 2.4(a)), in which a

relatively thick silicon dioxide layer, also called field oxide, is created on the surface (Fig.2.4(b)). Then, the field oxide is selectively etched to expose the silicon surfaceon whichthe MOS transistor will be created (Fig. 2.4(c)). Following this step, the surface iscovered with a thin, high-quality oxide layer, which will eventually form the gate oxide ofthe MOS transistor (Fig. 2.4(d)). On top of the thin oxide, a layer of polysilicon(polycrystalline silicon) is deposited (Fig. 2.4(e)). Polysilicon is used both as gateelectrode material for MOS transistors and also as an interconnect medium in siliconintegrated circuits. Undoped polysilicon has relatively high resistivity. The resistivity ofpolysilicon can be reduced, however, by doping it with impurity atoms.


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After deposition, the polysilicon layer is patterned and etched to form the interconnectsand the MOS transistor gates (Fig. 2.4(f)). The thin gate oxide not covered by polysiliconis also etched away, which exposes the bare silicon surface on which the source and drainjunctions are to be formed (Fig. 2.4(g)). The entire silicon surface is then doped with ahigh concentration of impurities, either through diffusion or ion implantation (in this casewith donor atoms to produce n-type doping). Figure 2.4(h) shows that the doping

penetrates the exposed areas on the silicon surface, ultimately creating two n-typeregions (source and drain junctions) in the p-type substrate. The impurity doping alsopenetrates the polysilicon on the surface, reducing its resistivity. Note that the polysilicongate, which is patterned before doping actually defines the precise location of the channelregion and, hence, the location of the source and the drain regions. Since this procedureallows very precise positioning of the two regions relative to the gate, it is also called theself-aligned process.


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Figure-2.4:Process flow for the fabrication of an n-type MOSFET on p-type silicon.


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Once the source and drain regions are completed, the entire surface is again covered withan insulating layer of silicon dioxide (Fig. 2.4(i)). The insulating oxide layer is thenpatterned in order to provide contact windows for the drain and source junctions (Fig.2.4(j)). The surface is covered with evaporated aluminum which will form theinterconnects (Fig. 2.4(k)). Finally, the metal layer is patterned and etched, completingthe interconnection of the MOS transistors on the surface (Fig. 2.4(l)). Usually, a second

(and third) layer of metallic interconnect can also be added on top of thisstructure bycreating another insulating oxide layer, cutting contact (via) holes, depositing, andpatterning the metal.

1.5.3 The CMOS n-Well Process

Having examined the basic process steps for pattern transfer through lithography, andhaving gone through the fabrication procedure of a single n-type MOS transistor, we can

now return to the generalized fabrication sequence of n-well CMOS integrated circuits,as shown in Fig. 2.1. In the following figures, some of the important process stepsinvolved in the fabrication of a CM OS inverter will be shown by a top view of thelithographic masks and a cross-sectional view of the relevant areas.

The n-well CMOS process starts with a moderately doped (with impurity concentrationtypically less than 1015 cm-3) p-type silicon substrate. Then, an initial oxide layer is grownon the entire surface. The first lithographic mask defines the n-well region. Donor atoms,usually phosphorus, are implanted through this window in the oxide. Once the n-well iscreated, the active areas of the nMOS and pMOS transistors can be defined. Figures 2.5

through 2.10 illustrate the significant milestones that occur during the fabrication processof a CMOS inverter.


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Figure-2.5: Following the creation of the n-well region, a thick field oxide is grown in the

areas surrounding the transistor active regions, and a thin gate oxide is grown on top ofthe active regions. The thickness and the quality of the gate oxide are two of the mostcritical fabrication parameters, since they strongly affect the operational characteristics of

the MOS transistor, as well as its long-term reliability.


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Figure-2.6:The polysilicon layer is deposited using chemical vapor deposition (CVD) andpatterned by dry (plasma) etching. The created polysilicon lines will function as the gateelectrodes of the nMOS and the pMOS transistors and their interconnects. Also, thepolysilicon gates act as self-aligned masks for the source and drain implantations thatfollow this step.


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Figure-2.7: Using a set of two masks, the n+ and p+ regions are implanted into the

substrate and into the n- well, respectively. Also, the ohmic contacts to the substrate andto the n-well are implanted in this process step.


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Figure-2.8: An insulating silicon dioxide layer is deposited over the entire wafer using

CVD. Then, the contacts are defined and etched away to expose the silicon or polysiliconcontact windows. These contact windows are necessary to complete the circuitinterconnections using the metal layer, which is patterned in the next step.


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Figure-2.9: Metal (aluminum) is deposited over the entire chip surface using metal

evaporation, and the metal lines are patterned through etching. Since the wafer surface isnon-planar, the quality and the integrity of the metal lines created in this step are verycritical and are ultimately essential for circuit reliability.


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Figure-2.10: The composite layout and the resulting cross-sectional view of the chip,

showing one nMOS and one pMOS transistor (built-in n-well), the polysilicon and metalinterconnections. The final step is to deposit the passivation layer (for protection) overthe chip, except for wire-bonding pad areas.

The patterning process by the use of a succession of masks and process steps isconceptually summarized in Fig. 2.11. It is seen that a series of masking steps must besequentially performed for the desired patterns to be created on the wafer surface. Anexample of the end result of this sequence is shown as a cross-section on the right.


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1.5.4 Advanced CMOS Fabrication Technologies

In this section, two examples will be given for advanced CMOS processes which offeradditional benefits in terms of device performance and integration density. Theseprocesses, namely, the twin-tub CMOS process and the silicon-on-insulator (SOI)process, are becoming especially more popular for sub-micron geometries where device

performance and density must be pushed beyond the limits of the conventional n-wellCM OS process.

Twin-Tub (Twin-Well) CMOS Process

This technology provides the basis for separate optimization of the nMOS and pMOStransistors, thus making it possible for threshold voltage, body effect and the channeltransconductance of both types of transistors to be tuned independently. Generally, thestarting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. Thisepitaxial layer provides the actual substrate on which the n-well and the p-well are

formed. Since two independent doping steps are performed for the creation of the wellregions, the dopant concentrations can be carefully optimized to produce the desireddevice characteristics.

In the conventional n-well CM OS process, the doping density of the well region istypically about one order of magnitude higher than the substrate, which, among othereffects, results in unbalanced drain parasitics. The twin-tub process (Fig. 2.12) also avoidsthis problem.

Figure-2.12: Cross-section of nMOS and pMOS transistors in twin-tub CMOS process.

Silicon-on-Insulator (SOI) CMOS Process

Rather than using silicon as the substrate material, technologists have sought to use aninsulating substrate to improve process characteristics such as speed and latch-upsusceptibility. The SOI CMOS technology allows the creation of independent, completelyisolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate (forexample: sapphire). The main advantages of this technology are the higher integration


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density (because of the absence of well regions), complete avoidance of the latch-upproblem, and lower parasitic capacitances compared to the conventional n-well or twin-tub CMOS processes. A cross-section of nMOS and pMOS devices in created using SOIprocess is shown in Fig. 2.13.

The SOI CMOS process is considerably more costly than the standard n-well CMOS

process. Yet the improvements of device performance and the absence of latch-upproblems can justify its use, especially for deep-sub-micron devices.

Figure-2.13: Cross-section of nMOS and pMOS transistors in SOI CMOS process.

1.7 Layout Design Rules

The physical mask layout of any circuit to be manufactured using a particular process mustconform to a set of geometric constraints or rules, which are generally called layoutdesign rules. These rules usually specify the minimum allowable line widths for physicalobjects on-chip such as metal and polysilicon interconnects or diffusion areas, minimumfeature dimensions, and minimum allowable separations between two such features. If ametal line width is made too small, for example, it is possible for the line to break duringthe fabrication process or afterwards, resulting in an open circuit. If two lines are placed

too close to each other in the layout, they may form an unwanted short circuit by mergingduring or after the fabrication process. The main objective of design rules is to achieve ahigh overall yield and reliability while using the smallest possible silicon area, for anycircuit to be manufactured with a particular process.

Note that there is usually a trade-off between higher yield which is obtained throughconservative geometries, and better area efficiency, which is obtained throughaggressive, high- density placement of various features on the chip. The layout designrules which are specified for a particular fabrication process normally represent areasonable optimum point in terms of yield and density. It must be emphasized, however,

that the design rules do not represent strict boundaries which separate "correct" designsfrom "incorrect" ones. A layout which violates some of the specified design rules may stillresult in an operational circuit with reasonable yield, whereas another layout observing allspecified design rules may result in a circuit which is not functional and/ or has very lowyield. To summarize, we can say, in general, that observing the layout design rulessignificantly increases the probability of fabricating a successful product with high yield.


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The design rules are usually described in two ways :

Micronrules, in which the layout constraints such as minimum feature sizes andminimum allowable feature separations, are stated in terms of absolute dimensionsin micrometers, or,

Lambda rules, which specify the layout constraints in terms of a single parameter

(?) and, thus, allow linear, proportional scaling of all geometrical constraints.

1.8 Lambda Based Rules

Lambda-based layout design rules were originally devised to simplify the industry-standard micron-based design rules and to allow scaling capability for various processes. Itmust be emphasized, however, that most of the submicron CMOS process design rules donot lend themselves to straightforward linear scaling. The use of lambda-based designrules must therefore be handled with caution in sub-micron geometries.

Based on the assumption of:

half of the minimum feature size

0.75 worst case misalignment of a mask

1.5 worst case misalignment mask to mask

Gives the following rules for an NFET:

2 Minimum width of gate

2 Minimum width of contact

Minimum enclosure of contact by diff

2 Minimum extension of poly beyond diff

2 Minimum space of contact to polyAnd the following derived rules:

4 Minimum width of diff

5 Minimum length of diff

In the following, we present a sample set of the lambda-based layout design rules devisedfor the MOSIS CMOS process and illustrate the implications of these rules on a section asimple layout which includes two transistors


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MOSIS Layout Design Rules (sample set)

Rule number Description L-Rule

R1 Minimum active area width 3 LR2 Minimum active area spacing 3 L

R3 Minimum poly width 2 LR4 Minimum poly spacing 2 L

R5 Minimum gate extension of poly over active 2 L

R6 Minimum poly-active edge spacing 1 L

(poly outside active area)

R7 Minimum poly-active edge spacing 3 L

(poly inside active area)

R8 Minimum metal width 3 L

R9 Minimum metal spacing 3 L

R10 Poly contact size 2 L

R11 Minimum poly contact spacing 2 LR12 Minimum poly contact to poly edge spacing 1 L

R13 M inimum poly contact to metal edge spacing 1 LR14 M inimum poly contact to active edge spacing 3 L

R15 Active contact size 2 L

R16 Minimum active contact spacing 2 L

(on the same active region)

R17 M inimum active contact to active edge spacing 1 L

R18 M inimum active contact to metal edge spacing 1 LR19 M inimum active contact to poly edge spacing 3 LR20 Minimum active contact spacing 6L

(on different active regions)


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Figure-2.14:

Illustration of some of the typical M OSIS layout design rules listed above.


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1.9 DesignRules- MOSIS Scalable CMOS (SCMOS)

1.9.1 Introduction1.9.2 SCMOS Design Rules

1.9.3 Well Type

1.9.4 SCMOS Options

1.9.1 IntroductionMOSIS Scalable CMOS (SCMOS) is a set of logical layers together with their designrules, which provide a nearly process- and metric-independent interface to many CMOSfabrication processes available through MOSIS. The designer works in the abstractSCMOS layers and metric unit ("lambda"). He then specifies which process and featuresize he wants the design to be fabricated in. MOSIS maps the SCMOS design onto thatprocess, generating the true logical layers and absolute dimensions required by the

process vendor. The designer can often submit exactly the same design, but to a differentfabrication process or feature size. MOSIS alone handles the new mapping.

By contrast, using a specific vendor's layers and design rules ("vendor rules") will yield adesign which is less likely to be directly portable to any other process or feature size.Vendor rules usually need more logical layers than the SCMOS rules, even though bothfabricate onto exactly the same process. More layers means more design rules, a higherlearning curve for that one process, more interactions to worry about, more complexdesign support required, and longer layout development times. Porting the design to anew process will be burdensome.SCMOS designers access process-specific features by using MOSIS-provided abstractlayers which implement those features. For example, a designer wishing to use second-poly would use the MOSIS-provided second-poly abstract layer, but must then submit toa process providing for two polysilicon layers. In the same way, designers may accessmultiple metals, or different types of analog structures such as capacitors and resistors,without having to learn any new set of design rules for the more standard layers such asmetal-1. SCMOS is there for portability and simplicity. It is NOT there for fine-tunedlayout.

Vendor rules may be more appropriate when seeking maximal use of silicon area, moredirect control over analog circuit parameters, or for very large production runs, where theadded investment in development time and loss of design portability is clearly justified.However the advantages of using SCMOS rules may far outweigh such concerns, andshould be considered.

1.9.2 SCMOS Design RulesIn the SCMOS rules, circuit geometries are specified in the Mead and Conway'slambda based methodology. The unit of measurement, lambda, can easily bescaled to different fabrication processes as semiconductor technology advances.


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Each design has a technology-code associated with the layout file. Eachtechnology-code may have one or more associated options added for the purposeof specifying either (a) special features for the target process or (b) the presence ofnovel devices in the design. At the time of this revision, MOSIS is offering CMOSprocesses with feature sizes from 1.5 micron to 0.18 micron.

Standard SCMOSThe standard CMOS technology accessed by MOSIS is a single polysilicon, doublemetal, bulk CMOS process with enhancement-mode n-MOSFET and p-MOSFETdevices.

1.9.3 Well TypeThe Scalable CMOS (SC) rules support bothn-well andp-well processes.

SCN specifies ann-well process, SCP specifies ap-well process, and SCE indicatesthat the designer is willing to utilize a process of either n-well or p-well.

An SCE design must provide both a drawnn-well and a drawnp-well; MOSIS willuse the well that corresponds to the selected process and ignore the other well. Asa convenience, SCN and SCP designs may also include the other well (p-well in anSCN design or n-well in an SCP design), but it will always be ignored.

MOSIS currently offers onlyn-well processes or foundry-designatedtwin-wellprocesses that from the design and process flow standpoints are equivalent to n-well processes. These twin-well processes may have options (deepn-well) thatprovide independently isolatedp-wells. For all of these processes at this time use

thetechnology code SCN. SCP is currently not supported, and SCE is treatedexactly as SCN.

1.9.4 SCMOS OptionsSCMOS options are used to designate projects that use additional layers beyondthe standard single-poly, double metal CMOS. Each option is called out with adesignator that is appended to the basic technology-code. Please note that not allpossible combinations are available. The current list is shown in Table 1.

Table 1: SCMOS Technology Options

Designation Long Form Description

E Electrode Adds a second polysilicon layer (poly2) that can serve either asthe upper electrode of a poly capacitor or (1.5 micron only) as agate for transistors

A Analog Adds electrode (as in E option), plus layers for vertical NPNtransistor pbase


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3M 3 Metal Adds second via (via2) and third metal (metal3) layers

4M 4 Metal Adds 3M plus third via (via3) and fourth metal (metal4) layers

5M 5 Metal Adds 4M plus fourth via (via4) and fifth metal (metal5) layers

6M 6 Metal Adds 5M plus fifth via (via5) and sixth metal (metal6) layers

LC LinearCapacitor

Adds a cap_well layer for linear capacitors

PC Poly Cap Adds poly_cap, a different layer for linear capacitors

SUBM Sub-Micron Uses revised layout rules for better fit to sub-micron processes(see section 2.4)

DEEP Deep Uses revised layout rules for better fit to deep sub-micronprocesses (see section 2.4)

Table 3a: SCMOS and SCMOS Sub-micron DifferencesRule Description SCMOS SCMOS

sub-micron

1.1, 17.1 Well width 10 12

1.2, 17.2 Well space(different potential)

9 18

2.3 Well overlap(space) to transistor

5 6

3.2 Poly space 2 3

5.3, 6.3 Contact space 2 3

5.5b Contact to Polyspace to Poly

4 5

7.2 Metal1 space 2 3

7.4 Minimumspace(when metal line is wider than 10 lambda)

4 6

8.5 Via on flat 2 Unrestricted

11.1 Poly2 width 3 7

11.3 Poly2 overlap 2 5

11.5 Space to Poly2 contact 3 6

13.2 Poly2 contact space 2 3

15.1 Metal3 width(3 metal process only)

6 5

15.2 Metal3 space(3 metal process only)

4 3


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15.4 Minimum space(when metal line is wider than 10 lambda)(3 metal process only)

8 6

17.3 Minimum spacing to external Active 5 6

17.4 Minimum overlap of Active 5 6

Table 3b: SCMOS Sub-micron and SCMOS Deep Differences

Rule Description SCMOSsub-micron

SCMOSDEEP

3.2 Poly spaceover field

3 3

3.2.a Poly spaceover Active

4

3.3 Minimum

gate extensionof Active

2 2.5

3.4 Active extensionbeyond Poly

3 4

4.3 Select overlapof Contact

1 1.5

4.4 Select width and space(p+ to p+ or n+ to n+)

2 4

5.3, 6.3 Contact spacing 3 4

8.1 Via width 2 3


9.4 Minimum space(when metal line is wider than 10 lambda)

6 8

14.1 Via2 width 2 3



(for 4+ metal processes)

6 8

21.1 Via3 width 2 3

22.2 Metal4 space(for 5+ metal processes)

3 4


6 8

25.1 Exact size 2 x 2 3 x 3


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26.3 Minimum overlap of Via4(for 5 metal process only)

1 2

26.4 Via4 overlap 6 8

29.1 Exact size 3 x 3 4 x 4

30.3 Minimum overlap of Via5 1 2

Summary:Vlsi technology and its growth has been explained briefly in the early part of introduction. Thisfiled has witnessed tremendous growth in recent times and made a big impact in the human lifeand electronics industry last three decades.MOS transistor is the basic and fundamental unit of VLSI chips. We have covered extensivelyabout the working function of MOS transistor and the various modes of it.

There are different technologies adopted for chip fabrication (pmos,nmos,cmos,bicmos,twintub).

CCET - VLSI Desgn

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