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SOCSA Slides: LAN/SAN Switch

© Institute for Integrated Systems Technische Universität München www.lis.ei.tum.de

Case Study: LAN/SAN Switch

System-on-Chip

Solutions & Architectures A. Herkersdorf

© Institute for

Integrated Systems

A. Herkersdorf SoC - LAN/SAN Switch - 2

LAN/SAN Switch

Motivation

Evolution: From shared medium LAN to Switches

Different Switch Architectures

Examples for LAN/SAN Switch Products

IC Requirements for ATM Cell Switch

I/O & Package Requirements

Memory & FSM Requirements

Power

Summary: IC Requirements for Network Processors, L2 Switches and Framers

http://www.lis.ei.tum.de/


© Institute for

Integrated Systems


Real-World Case Studies

Sonet/SDH Transmission LAN/SAN

Switch

Internet Router

Sonet/SDH Transmission

Control Procesors

© Institute for

Integrated Systems


Traditional Shared-Medium LAN

Ethernet IEEE 802.3

Ubiquitous shared/switched-medium, packet-based Layer 2 local area network standard

10/100 Mb/s, 1 Gb/s, 10 Gb/s

Evolution towards VPN (security) and support for real-time streams

Bytes 7 1 2 x 6 2 46 – 1500 4

Data Addr’s CRC P’ble S L

Shared-medium

Single connection (@ full media speed)


© Institute for

Integrated Systems


Traditional Shared-Medium LAN

Ethernet IEEE 802.3


10/100 Mb/s, 1 Gb/s, 10 Gb/s


Bytes 7 1 2 x 6 2 46 – 1500 4


Shared-medium


Collisions

Fairness, QoS ?!

© Institute for

Integrated Systems


Evolution towards LAN/SAN Switches

Ethernet IEEE 802.3


10/100 Mb/s, 1 Gb/s, 10 Gb/s


Bytes 7 1 2 x 6 2 46 – 1500 4


Shared-medium


Collisions

Fairness, QoS ?!

Switched-medium

Multiple, simultaneous connections

Output contention -> queuing


© Institute for

Integrated Systems


Switch: Motivation / Challenges

Motivation for Switches Higher system throughput

through simultaneous connections

Better support for service differentiation

Support for different port speed rates in one system

Switch Challenges:

Port speed

Number of ports

Switch throughput

Contention resolution

OUT 1

IN N

IN 1

OUT N

© Institute for

Integrated Systems



© Institute for

Integrated Systems


Switch Architectures

N input buffers/queues with line rate Rd/Wr BW

Performance limited through “Head of line blocking”

Operated with speed-up

Input Buffered Switches

.

.

.

OUT 1

IN N

IN 1

OUT N

Frequently used in low-end (few Gb/s aggregate link capacity) LAN switches

Multi 10/100 and Gb EN switches

Load [%]

Nor

mal

ized D

ela

y

10

8

6

4

2

0 20 40 60 80 100

© Institute for

Integrated Systems



N output buffers/queues with Nx line rate Wr and 1x line rate Rd BW

Best performance, but “expensive” (memory BW)

Output Buffered Switches

.

.

.

OUT 1

IN N

IN 1

OUT N

Not implemented in this form in practice

Load [%]

Nor

mal

ized D

ela

y

10

8

6

4

2

0 20 40 60 80 100


© Institute for

Integrated Systems

A. Herkersdorf

Head of line blocking

Input Buffered Switches

OUT 1

IN 3

IN 1

OUT 3

IN 2 OUT 2

1

Packet slots Packet slots

2 3

2

Output Buffered Switches

OUT 1

IN 3

IN 1

OUT 3

IN 2 OUT 2

1 1

2

3

2 2

3

3 3

2

1 2 1 2

3 1

3

1

1 2

3

3

L= 2 2 2 1 0

2 2

2 1

1

∑ L= 14

∑ L= 7

L= 2 2 2 1 0

0 0

0 0

Blue packets of slot 1 block packets of slot 2 with free OUT ports

SoC - LAN/SAN Switch - 11

© Institute for

Integrated Systems



1 shared output buffer /queue with Nx line rate Wr and Nx line rate Rd BW

Behaves like output buffer switch for ≥ 16 pkts/port memory capacity

Shared Output Buffered Switches

OUT 1

IN N

IN 1

OUT N

Dynamic association of memory capacity to outputs

Used in high-capacity, low latency SAN/WAN switches

Load [%]

Nor

mal

ized D

ela

y

10

8

6

4

2

0 20 40 60 80 100

Memory size [pkts/port]

0 8 ∞


© Institute for

Integrated Systems


Anatomy of Switch/Router Systems

Terminates physical media: SDH, EN, FC

Determines box function: Switch, Router, Gateway, etc.

Controls entire box

Connects multiple adapter cards

Line Interface

Network Processor Switch

Fabric System Processor

Backplane

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