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Transcript of CAS Open Column
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8/9/2019 CAS Open Column
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90
Liming Xiu
OpenColumn
In the article The Concept of Time-Average-Frequency
and Mathematical Analysis of Flying-Adder Frequency
Synthesis Architecture, a new type of component
Digital-to-Frequency Converter (DFC) is introduced [1].
The DFC is built upon two corner stones: a circuit tech-
nique called Flying-Adder frequency synthesis architec-
ture and a rigorously formed concept of Time-Average-
Frequency (please refer to Figure 2 of [1]). The first cor-ner stone (Flying-Adder architecture) is the hardware,
which is the implementation circuitry [2][8]. It is a
mature technique with almost ten years history of com-
mercial usage [9]. The second corner stone, Time-Aver-
age-Frequency concept, is only formally introduced
recently [1]. Using the Time-Average-Frequency concept,
the theoretical foundation for Digital-to-Frequency Con-
verter is established in [1].
There are two important determinants behind the cre-
ation of this new component of Digital-to-Frequency Con-
verter: a) long period of time of studying and designing
with existing PLL techniques, such as integer-N PLL[10][13] and fractional-N PLL [14][17]. b) the new chal-
lenges raised by the various emerging applications. Espe-
cially, the new requirements presented by these new
applications are the true driving force behind this inno-
vation, as illustrated by some of the examples in [9].
Although the DFC and the time-average-frequency have
already been used in many commercial products, there
are still several associated mathematical problems which
remain unsolved. These problems are important. If
solved, it will have profound impact on future electronic
system design. These problems are difficult. Their resolu-
tions are beyond the authors capability. Therefore, using
this open column, the author is actively seeking help from
capable researchers on these open problems.
In this article, the circuit-related content has been
reduced to a minimum. The main focus lies in the mathe-
matical understanding. Anyone who has a background in
electrical engineering shall be able to understand the
problems and make a contribution if interested.
The Background
This open column paper is closely tied to the refer-
ence [1], which appears in the same issue of CAS Mag-
azine as this one. The goal of this paper is to provide
further detailed description on the issues raised in
that accompanying paper. As described in Section II.E
of [1], the Flying-Adder frequency synthesizers oper-
ation depends heavily on the fractional number usedin that system. When a fractional number is used in
the frequency control word of a Flying-Adder synthe-
sizer, the synthesizers output is in the fashion of
time-average-frequency. In other words, in the output
clock waveform, there is a prolonged cycle every
once in a while. These prolonged cycles are caused by
the fractional carry-in overflows. Table 1 of [1] lists
the resulting patterns from some commonly used frac-
tions. For convenience, this table is presented in here
(Table 1) as well. The left column is the fraction num-
ber, while the right column is the corresponding pat-
tern of the cycles. Letter A represents the normal
Digital Object Identifier 10.1109/MCAS.2008.928422
Some Open Issues Associated with the New Type of Component:Digital-To-Frequency Converter
Fraction r Combination Pattern
0.1 AAAAAAAAAB
0.2 AAAAB
0.3 AABAABAAAB
0.4 ABAAB
0.5 AB
0.6 ABABB
0.7 ABBABBABBB
0.8 ABBBB
0.9 ABBBBBBBBB
0.25 AAAB
0.75 ABBB
0.33333333 AAB
0.66666667 ABB
0.125 AAAAAAAB
0.875 ABBBBBBB
Table 1.The combination patterns for some fractions.
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cycle, letter B is the prolonged
cycles caused by the accumula-
tion of the fraction. The pattern
repeats forever.
In the simplest case of frac-
tion r taking the form of
r= 1/(N+ 1), there is one pro-longed cycle and N normal
cycles for every N+ 1 cycles.
And the clock waveform repeats
itself for every such N+ 1
cycles. This phenomenon is
shown in Figure 1. In the figure,
TA is the period of a normal
cycle; TB is the period of a pro-
longed cycle. As a group, these
N+ 1 cycles repeat themselves
at period of Tm.
For easier mathematicaltreatment without losing the
spirit of main focus, a sinusoidal
wave will be used for analysis.
Figure 2 shows the 1st harmonic,
S(t), of the clock waveform of
Figure 1.
To further assist the mathematical analysis, signal
S(t) can be decomposed intoS1(t) andS2(t) by superim-
position, as depicted in Figure 3. This decomposition
could be helpful when Fourier analysis is carried out on
these signals.
Where Is the Most Energy?
A clock signal is used to drive the electronic system. Its
energy distribution has great impact on the quality of the
end system. Ideally, for a clock pulse (square wave) of
frequency f, all its cycles have the length-in-time of
T= 1/f. Consequently, its energy is concentrated at fand
its harmonics, as illustrated in Figure 4. For a clock pulse
of close to 50% duty cycle, the magnitudes of the even-
term harmonics are reduced.
The clock waveform of the Flying-Adder synthesizer is
different. It is composed of two types of cycles:
TA = I and TB = (I+ 1) , where I is an integer
and is a constant used to represent a small time dura-
tion. Obviously, the energy distribution of this type of
clock will be significantly different than for the case of
Figure 4.
The occurrence of typeB cycle TB is dependent on the
fractional number rused in the frequency control word,
as evident from the examples in Table 1. Therefore, for a
Flying-Adder clock waveform, its energy distribution is
affected by three parameters: TA, TB and r. TA = 2/1and TB = 2/2 represent the sizes of the two types of
cycles. ris used to represent the frequency, or possibility,
that typeB occurs.
When r takes its simplest form of r= 1/(N+ 1),
there are N type-A cycles TA and one type-B cycle TBfor every N+ 1 cycles. This simplest case has been
graphically illustrated by Figures 1, 2 and 3. From thefigures, it is understandable that the waveform is a peri-
odic signal with a period of Tm. Accordingly, the funda-
mental frequency of its spectrum should be
m = 2/Tm. By applying Fourier analysis on the sinu-
soidal signal of Figure 2 (or Figure 3), we can obtain the
Fourier series coefficients in analytic form (please refer
to Section III.D of [1]).
Using the resulting analytic form, for any given 1, 2
and r, we can numerically and graphically prove that
the main stem is at (N+ 1) m. This also agrees with
91THIRD QUARTER 2008 IEEE CIRCUITS AND SYSTEMS MAGAZINE
One Cycle
t2LtbTm
NCycles of 1
S(t)
2
0
Figure 2. Sinusoidal wave is used for mathematical processing.
OneCycle
t2LtbTm0
N Cycles of 1
S1(t)
S2(t)
2
Figure 3. S(t) = S1(t)+ S2(t) by superimposition.
Normal Cycle
TA TA TA
N+1 CyclesTm=2 / m
TA TB TA TA TBTA TA
Longer Cycle Due to Fractional Carry-In
Figure 1. The clock waveform when r= 1/(N+ 1).
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intuition. Further, the simulation result by using the Dis-
crete Fourier Transform indicates the same conclusion
(Section IV.C of [1]).
In summary, it seems to us that:
When r= 1/(N+ 1), the main stem of signal S(t)sspectrum lies in the location of (N+1) m.
statement #1
Thus, problem #1 is: can an analytical proof be pro-
vided to statement #1?
In general, a fractional number can be classified as
one of the two types: rational and irrational. For the
case of rational, r can be expressed as r= a/b where
both a and b are whole numbers. r= 1/(N+ 1) of prob-
lem #1 is a special case of rational where a= 1. When
r= a/b is used as the base for accumulation, the carry-
in overflows occur in such a pattern: for every b opera-tions (accumulation), there are a carry-in overflows. In
other words, for every b cycles, there are a type-B
cycles and b-a type-A cycles. For example, when
r= 3/7, the pattern is AB AB AAB . Figure 5 graphically
shows the scenario.
When r= a/b, the main stem of signal S(t)s spectrum
lies in the location of b m
statement #2
Problem #2 is: can an analytical proof be provided to
statement #2?
This is a more generic statement which covers
statement #1. The solution of problem #1, which suppos-
edly is easier to obtain, could potentially provide some
insight to the resolution of this one.
This statement has also been confirmed by the numer-
ical approach we used in Section III of [1] and the simula-
tion result in Section IV.D of [1]. We believe it is true, butthe proof is out of reach at the current time.
Naturally, the next question is:
Problem #3: when ris irrational, how to carry out the
frequency spectrum analysis analytically?
Unlike the cases in problem #1 and #2, the signal S(t)
is not periodic any more when r is irrational. Hence, the
frequency spectrum should be continuous. The simula-
tion result in Section IV.E of [1] shows this characteristic
of continuousness in a certain degree. However, the true
picture of the spectrum can not be accurately obtainedsince an irrational number can not be presented by finite
digitals used in a computer. The understanding on this
problem needs to come from analysis.
For all the three aforementioned problems, we only
need to consider the case of r 0.5 since type-A and
type-B cycles are symmetric in mathematical analysis, as
evident from Table 1. Also, if needed, I> 3 can be
assumed when searching the solutions for these prob-
lems. Smaller Iis never used in a real circuit since it will
increase the implementation difficulty.
The resolutions of these three problems are all related
to one key issue of time-average-frequency: where is themost clock energy located? This has profound impact on
the usage of the clock signal.
Convert the Spurious Energy to Noise
Fractional numbers are used in DFC to generate fre-
quencies. In a real circuit, the fractions are used as the
base for accumulation. From time to time, the accu-
mulation result will overflow. When overflows happen,
the corresponding cycles will be prolonged by one .
Mathematically, the overflows occur regularly. Or,
they are periodic events which result in spurious sig-
nals in the frequency spectrum
as illustrated by examples in
Section IV of [1]. For certain
applications, the spurious sig-
nals have negative impact on
system performance, and are
thus undesired. Theoretically, if
the periodic characteristic
could be broken by one way or
another, the spurious signals
would be converted into noise.
92 IEEE CIRCUITS AND SYSTEMS MAGAZINE THIRD QUARTER 2008
Frequency
Magnitude (db)
(Hz)f 2f 3f 4f 6f5f
Figure 4. The energy distribution of ideal clock pulse.
bCycles (Including aLonger Cycles)
Normal Cycle Longer Cycle Due to Fractional Carry-In
Tm=2 / m
Figure 5. The clock waveform when r= a/b.
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manipulate the clock spectrum. This issue has been
discussed intensively in Section VI of the accompanying
paper. The modulation signals used for real application
are either triangular or sawtooth waveforms.
Problem #7: can a mathematical model be created to
describe the triangular/sawtooth waveform modulationfor spreading the energy?
This problem is similar to problem #5. Three parame-
ters are available for adjustment: the magnitude of the
waveform, the magnitude of each step and the update
rate. In problem #5, the goal is to convert the spurious
signals to noise; while in here, the goal is to spread its
center energy to a boarder band. The mathematical chal-
lenge still lies in the question of how to relate the type-A
and type-B events to the final clock output spectrum.
Figures 35, 36 and 38 of the accompanying paper
show some real spectrums by using the Flying-Adderspread spectrum technique. As shown, this technique is
very effective. However, quantitatively, the relationship
between the magnitude of the frequency spread and the
three knobs (the magnitude of the waveform, the magni-
tude of each step and the update rate) is not well under-
stood. In practice, large amount of trial-and-errors are
carried out. The mathematical understanding can surely
shine some light on this kind of shoot-in-the-dark
work.
Conclusion
In this paper, seven unsolved mathematical problemshave been presented which all relate to a new type of
electronic component: Digital-to-Frequency Converter.
These problems are parts of the theoretical foundation
of this new component. Even though theoretical in
nature, these problems will have profound impact on
future real electronic system design. These problems
present themselves as an excellent example of demon-
strating the significance of mathematical analysis in cir-
cuit design applications. They show the importance of
fundamental research on directing the real world work.
The author truly hopes that interested and capable
researchers take this challenge and provide help. The
joy of conquering the unknowns could be the reward of
well worth.
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Liming Xiu is an IC design lead in Texas
Instruments Inc. He has been working for
Texas Instruments since his graduation
from Texas A&M University in 1995. Dur-
ing his TI career, he has done significant
amount of work/research in PLL-related
areas. He is the principal inventor of
Flying-Adder frequency synthesis architecture which has
been used in many commercial products. He has pub-
lished many IEEE journal papers and conference papers
and holds twelve granted and pending US patents. He is
also an expert on VLSI SoC integration with battle-proven
integration experience on several very large chips in
advanced CMOS nodes. In this area, he has one book
published in Nov. 2007 by IEEE-Wiley, VLSI Circuit Design
Methodology Demystified: A Conceptual Taxonomy. Liming
Xiu is a Senior Member of Technical Staff of Texas Instru-
ments. He was general chair of IEEE CASS Dallas Chapter
2006 and 2007. Currently, he is activity chair of IEEE Dal-
las Section.
94 IEEE CIRCUITS AND SYSTEMS MAGAZINE THIRD QUARTER 2008